CN103531629A - 用于mos晶体管的设备和方法 - Google Patents

用于mos晶体管的设备和方法 Download PDF

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CN103531629A
CN103531629A CN201310001060.0A CN201310001060A CN103531629A CN 103531629 A CN103531629 A CN 103531629A CN 201310001060 A CN201310001060 A CN 201310001060A CN 103531629 A CN103531629 A CN 103531629A
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conductivity
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CN103531629B (zh
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周学良
伍震威
苏柏智
柳瑞兴
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Abstract

本发明涉及了一种MOS晶体管，其包括第一导电性的衬底、形成在该衬底上方的第一导电性的第一区域、形成在第一区域中的第一导电性的第二区域、形成在第二区域中的第二导电性的第一漏极/源极区域、第二导电性的第二漏极/源极区域、以及第一导电性的主体接触区域，其中，从上向下看去，该主体接触区域和第一漏极/源极区域以交替的方式形成。本发明还提供了一种用于MOS晶体管的设备和方法。

Description

用于MOS晶体管的设备和方法
技术领域
本发明涉及半导体领域，更具体地，本发明涉及一用于MOS晶体管的设备和方法。
背景技术
由于各种电子部件(例如，晶体管、二极管、电阻器、电容器等)的集成密度的发展，半导体集成电路(IC)工业经历了迅速的发展。大多数情况下，集成密度的这种发展源于半导体工艺节点的缩小(例如，将工艺节点缩小接近亚20纳米节点)。半导体器件被按比例缩小，从一代到下一代需要新的技术来保持电子部件的性能。例如，为了功率应用而期望晶体管的低栅极漏极电容和高击穿电压。
随着半导体技术的发展，金属氧化物半导体场效应晶体管(MOSFET)已广泛地应用在现今的集成电路中。MOSFET是电压控制器件。当向MOSFET的栅极施加控制电压并且该控制电压大于MOSFET的阈值时，在MOSFET的漏极和源极之间建立起了导电沟道。因此，电流在MOSFET的漏极和源极之间流动。换言之，当控制电压小于MOSFET的阈值时，MOSFET相应地断开。
MOSFET可以包括两个主类别。一种是n沟道MOSFET；另一种是p沟道MOSFET。根据结构的不同，MOSFET可以进一步被分成两个次类别，即，沟槽型功率MOSFET和横向功率MOSFET。
随着工艺节点的持续缩小，MOSFET的物理尺寸按比例缩小。MOSFET的按比例缩小结构可能导致MOSFET的电特性由于短沟道效应而变化。例如，为了获得低导通电阻MOSFET，使用更短的沟道长度来减小导通电阻。然而，这种更短的沟道长度可能导致短沟道效应。更具体地，由于MOSFET的漏极区域和源极区域更为接近，由此可能增大了穿通(punch-through)故障的风险。
发明内容
为了解决现有技术中所存在的问题，根据本发明的一个方面，提供了一种半导体器件，包括：第一导电性的衬底；所述第一导电性的第一区域，形成在所述衬底上方；所述第一导电性的第二区域，形成在所述第一区域中，其中，所述第二区域的掺杂密度高于所述第一区域的掺杂密度；第二导电性的第一漏极/源极区域，形成在所述第二区域中；所述第二导电性的第二漏极/源极区域，形成在所述衬底中并且远离所述第一源极/漏极区域；以及所述第一导电性的拾取区域，形成在所述第二区域中并且邻近所述第一漏极/源极区域。
在所述半导体器件中，还包括：所述第一导电性的主体接触区域，其中，从上向下看去，所述主体接触区域和所述第一漏极/源极区域以交替方式形成。
在所述半导体器件中，所述第一漏极/源极区域与所述主体接触区域的比例在10∶1至大约2∶1的范围内。
在所述半导体器件中，还包括：栅电极，形成在所述第一漏极/源极区域和所述第二漏极/源极区域之间。
在所述半导体器件中，还包括：第一轻掺杂漏极/源极区域，形成为与所述第二区域中的所述第一漏极/源极区域邻近。
在所述半导体器件中，还包括：第二轻掺杂漏极/源极区域，形成为与所述衬底中的所述第二漏极/源极区域邻近，其中，所述第二轻掺杂的漏极/源极区域位于所述栅电极下方。
在所述半导体器件中，还包括：相对于所述栅电极对称的第一轻掺杂漏极/源极区域和第二轻掺杂漏极/源极区域。
在所述半导体器件中，所述第一漏极/源极区域和所述拾取区域由电介质隔离部件分隔开。
在所述半导体器件中，所述拾取区域围绕所述第一漏极/源极区域和所述第二漏极/源极区域。
在所述半导体器件中，所述第一漏极/源极区域是源极；并且所述第二漏极/源极区域是漏极。
根据本发明的另一方面，提供了一种器件，包括：第一导电性的衬底；栅电极，位于所述衬底上方；第一漏极/源极区域和第二漏极/源极区域，在所述衬底中设置在所述栅电极的相对侧，其中，所述第一漏极/源极区域和所述第二漏极/源极区域具有第二导电性；第一掺杂阱，具有所述第一导电性，形成在所述第一漏极/源极区域下方；第二掺杂阱，具有所述第一导电性，形成在所述第一漏极/源极区域下方，其中，所述第一掺杂阱嵌在所述第二掺杂阱中，并且所述第一掺杂阱和所述第二掺杂阱被配置成使得掺杂密度从所述第一漏极/源极区域到所述第二漏极/源极区域逐渐减小；以及所述第一导电性的主体接触区域，形成为与所述衬底中的所述第一漏极/源极区域邻近，其中，从上向下看去，所述主体接触区域和所述第一漏极/源极区域以交替的方式形成。
在所述器件中，还包括：所述第一导电性的主体拾取环，围绕所述第一漏极/源极区域。
在所述器件中，还包括：第一轻掺杂漏极/源极区域，在至少一个掺杂阱中形成为与所述第一漏极/源极区域邻近。
在所述器件中，还包括：相对于所述栅电极对称并且分别与所述第一漏极/源极区域和所述第二漏极/源极区域邻近的第一轻掺杂漏极/源极区域和第二轻掺杂漏极/源极区域。
在所述器件中，所述第一漏极/源极区域与所述主体接触区域的比例在10∶1至大约2∶1的范围内。
根据本发明的又一方面，提供了一种晶体管，包括：第一晶体管，包括第一栅极、第一源极、第一漏极和第一主体接触件，其中：从上向下看去，所述第一主体接触件和所述第一源极以交替方式形成；并且所述第一源极形成在第一堆叠阱区域中，其中，所述第一堆叠阱区域包括：第一导电性的第一区域，形成在所述第一导电性的衬底上方；和所述第一导电性的第二区域，嵌在所述第一区域中；第二晶体管，包括第二栅极、第二源极、第二漏极和第二主体接触件，其中，所述第一漏极和所述第二漏极连接在一起，并且其中：从上向下看去，所述第二主体接触件和所述第二源极以交替的方式形成；并且所述第二源极形成在第二堆叠阱区域中，其中，所述堆叠阱区域包括：所述第一导电性的第三区域，形成在所述衬底上方；和所述第一导电性的第四区域，嵌在所述第三区域中；以及主体拾取环，围绕所述第一晶体管和所述第二晶体管。
在所述晶体管中，还包括：所述第一导电性的主体拾取环，在所述衬底中围绕所述第一晶体管和所述第二晶体管。
在所述晶体管中，还包括：第一轻掺杂源极/漏极区域，带有所述第一导电性，在所述第二区域中邻近所述第一源极。
在所述晶体管中，还包括：第二轻掺杂漏极/源极区域，带有所述第一导电性，形成为邻近所述衬底中的所述第一漏极，其中，所述第二轻掺杂漏极/源极区域位于所述第一栅极下方。
在所述晶体管中，所述第二区域的掺杂密度高于所述第一区域的掺杂密度。
附图说明
为了更全面地理解实施例及其优势，现将结合附图所进行的描述作为参考，其中：
图1示出了根据一个实施例的带有叠加阱的MOS晶体管的简化截面图；
图2示出了两条曲线，这两条曲线示出了传统的带有5V的p阱的MOS晶体管与带有两个叠加p阱的MOS晶体管之间的掺杂密度的区别；
图3示出了根据另一个实施例的带有叠加阱的MOS晶体管的简化截面图；
图4示出了两条曲线，这两条曲线示出了传统的带有5V的p阱的MOS晶体管与图3中所示出的MOS晶体管之间的掺杂密度的区别；
图5示出了根据一个实施例的MOS晶体管阵列的简化俯视图；
图6示出了根据一个实施例图5中所示的MOS晶体管阵列的截面图；
图7示出了根据一个实施例图5中所示的MOS晶体管阵列的另一截面图；
图8示出了根据另一个实施例的MOS晶体管阵列的简化俯视图；
图9示出了根据一个实施例的图8中所示的MOS晶体管阵列的截面图；以及
图10示出了根据一个实施例的图8中所示的MOS晶体管阵列的另一截面图。
除非另有说明，不同附图中的相应标号和符号通常指相应部件。将附图绘制成清楚地示出实施例的相关方面而不必须成比例绘制。
具体实施方式
下面，详细讨论本发明各实施例的制造和使用。然而，应该理解，本发明提供了许多可以在各种具体环境中实现的可应用的概念。所讨论的具体实施例仅仅示出了制造和使用本发明的具体方式，而不用于限制本发明的范围。
将在具体的语境，即，带有叠加阱的横向金属氧化物半导体(MOS)器件中借助实施例来描述本公开。然而，本公开的实施例可以应用于多种半导体器件。
图1示出了根据一个实施例的带有叠加阱(superimposed well)的MOS晶体管的简化截面图。MOS晶体管100包括衬底102(优选地是P型的)、形成在该衬底102中的第一P型区域104，和第二P型区域106。更具体地，第二P型区域106嵌在第一P型区域104中。
P+区域132和第一N+区域122形成在第二P型区域106中。第二N+区域124和第二P+区域132形成在衬底102中。如图1所示，第一N+区域122和第二N+区域124形成在栅电极128的相对侧上。
为了改进MOS晶体管的性能，两个轻掺杂的漏极/源极(LDD)区域126与其相应的N+区域(第一N+区域122和第二N+区域124)邻近地形成。根据一个实施例，第一N+区域122作为MOS晶体管100的源极区域；第二N+区域124作为MOS晶体管100的漏极区域。LDD区域126用作其对应的漏极区域124和源极区域122的延长。MOS晶体管100还包括栅极介电层127和形成在该栅极电介质127上方的栅电极128。
衬底102可以由硅、硅锗、碳化硅等等形成。可选地，衬底102可以是绝缘体上硅(SOI)衬底。该SOI衬底可以包括形成在绝缘体层(例如，埋置的氧化物等)上的半导体材料层(例如，硅、锗等)，该绝缘体层形成在衬底中。可以使用的其他衬底包括多层的衬底、梯度衬底、混合取向衬底等。
可以通过注入p型掺杂材料(诸如，硼、镓、铝、铟、其组合，或类似的)来形成第一P型区域104和第二P型区域106。可选地，可以通过扩散工艺来形成P型区域106。根据一个实施例，使用5V的互补金属氧化物半导体(CMOS)工艺来形成第一P型阱104。使用1.8V的CMOS工艺来形成第二P型阱106。
由于第二P型阱106嵌在第一P型阱104中，组合掺杂密度高于由一个5V的CMOS工艺形成的传统的P阱。P阱的组合掺杂密度在大约1017/cm3至大约1018/cm3的范围内。应该注意，第一P型区域104和第二P型区域106的形成工艺与现存的MOS晶体管制造工艺相适合。换言之，可以在不引入额外的制造步骤的条件下形成图1所示的叠加阱。
第一N+区域122形成在第二P型阱106上方。根据一个实施例，第一N+区域122用作MOS晶体管100的源极。可以通过在大约1019/cm3至大约1020/cm3的浓度下注入掺杂物(诸如，磷)来形成该源极区域。另外，可以在第一N+区域122上方形成源极接触件(未示出)。
第二N+区域形成在衬底102中。根据一个实施例，第二N+区域124可以是MOS晶体管100的漏极。可以通过在大约1019/cm3和大约1020/cm3之间的浓度下注入n型掺杂物(诸如，磷)来形成漏极区域。如图1所示，漏极区域与源极(第一N+区域122)形成在相对侧上。
图1所示的P+区域132可以是P+拾取环(P+pickup ring)的一部分。该P+拾取环可以围绕着MOS晶体管的漏极和源极区域。由此，如图1中的MOS晶体管100的截面图所示，具有两个P+区域。第一P+区域132与第一N+区域122邻近地形成并且通过隔离区域144与第一N+区域122分隔开。第二P+区域132与第二N+区域124邻近地形成并且通过另一个隔离区域116与第二N+区域124分隔开。
可以通过在大约1019/cm3和大约1020/cm3之间的浓度下注入p型掺杂物(诸如，硼)来形成P+区域132。P+区域132可以通过第二P型阱106和第一P型阱104与MOS晶体管的p型主体(衬底102)相连接。为了消除主体效应，P+区域132可以直接通过源极接触件(未示出)与源极122相连接。
栅极介电层127形成在第一N+区域122和第二N+区域124之间。栅极介电层127可以由氧化硅、氮氧化硅、氧化铪、氧化锆等等形成。根据实施例，栅极介电层127的厚度在大约
Figure BDA00002700571200071
和大约
Figure BDA00002700571200072
之间。栅电极128形成在栅极介电层127上。栅电极128可以由多晶硅、多晶硅锗、硅化镍或其他金属、金属合金材料等形成。
如图1所示，存在四个隔离区域，即，第一隔离区域112、第二隔离区域114、第三隔离区域116，以及第四隔离区域118。隔离区域被用于隔离有缘区域，从而防止流经邻近的有缘区域的电流泄漏。隔离区域(例如，第一隔离区域112)可以通过多种方式(例如，热生长、沉积)和材料(例如，氧化硅、氮化硅)来形成。在该实施例中，可以通过浅沟槽隔离(STI)技术来制造隔离区域。
图2示出了两条曲线，这两条曲线示出了传统的带有5V的p阱的MOS晶体管与图1所示的带有两个叠加的p阱的MOS晶体管之间的掺杂密度的区别。图2的水平轴线代表的是从图1所示的MOS晶体管100的源极区域(第一N+区域122)到漏极区域(第二N+区域124)的距离。换言之，水平轴线的起点代表的是与源极(图1中所示的第一N+区域122)邻近的P阱。水平轴线的终点代表的是与漏极(图1中所示的第二N+区域124)邻近的衬底区域。图2的纵向轴线代表的是掺杂密度。
曲线202和曲线204示出了传统的带有5V的p阱的MOS晶体管与图1所示的带有两个叠加的p阱的MOS晶体管之间的掺杂密度的区别。如图2所示，在具有两个叠加的p阱的区域中，图1中所示的MOS晶体管100的掺杂密度高于传统的MOS晶体管。换言之，在没有5V的p阱(诸如，与MOS晶体管100的漏极邻近)的区域中，图1所示的MOS晶体管100的掺杂密度低于传统的MOS晶体管，这是因为在传统的MOS晶体管的漏极下面可能形成了5V的p阱。
根据实施例，图2中所示的传统的MOS晶体管的掺杂密度几乎是不变的。掺杂密度在大约8×1016/cm3至大约6×1017/cm3的范围内。相比之下，图1中所示的MOS晶体管100的掺杂密度是斜线，在与源极相连的区域中该斜线具有较高的掺杂密度而在与漏极邻近的区域中则具有较低的掺杂密度。根据实施例，图1中所示的MOS晶体管的掺杂密度在大约8×1015/cm3至大约8×1017/cm3的范围内。应该注意到，与第一p型阱104相比，第二p型阱106具有更高的掺杂浓度，这是因为第二P型阱106是由1.8V的CMOS工艺形成的，而第一P型阱是由5V的CMOS工艺形成的。
图2示出：具有叠加的p阱的MOS晶体管在与源极邻近的区域中可以获得更高的掺杂密度。这种较高的掺杂密度有助于改善MOS晶体管100的穿通窗口。由此，可以使用较短的沟道长度来进一步减小节距(pitch)以及MOS晶体管100的导通电阻。
另外，图2示出了MOS晶体管100的主体区域从P型阱到第二N+区域124的掺杂密度低于传统的MOS晶体管。主体区域中的较低的掺杂密度有助于减小MOS晶体管100的主体电阻。该减小的主体电阻有助于防止寄生的主体晶体管错误地导通。由此可以改善MOS晶体管100的可靠性，诸如，安全工作区域(SOA)。
图3示出了根据另一实施例的带有叠加阱的MOS晶体管的简化截面图。除了图3中所示的MOS晶体管300是p型MOS晶体管而不是图1中所示的n型MOS晶体管100以外，图3的截面图与图1的截面图类似。例如，图1中所示的p阱分别被其相应的n阱304和306所替代。
图3的源极和漏极区域分别被P+区域322和324所替代。同样地使用了N+区域来实现主体接触件332。图3中所示的每个元件的具体的结构和制造工艺与图1中的类似，因此，在此处不再详细论述。应该注意到，图3中的5V的n阱大于图1中所示的其相应的部分。如图3中所示，5V的n阱形成在源极区域(P+区域322)以及漏极区域(P+区域324)以下。由此，除了区域306以外，图3中所示的MOS晶体管300的掺杂密度与传统的MOS晶体管的类似。
图4示出了两条曲线，这两条曲线示出了传统的带有5V的p阱的MOS晶体管与图3中所示的MOS晶体管之间的掺杂密度的区别。图4的水平轴线代表了图3中所示的MOS晶体管300从源极区域(P+区域322)到漏极区域(P+区域324)的距离。图4的纵向轴线代表了掺杂浓度。
曲线402和曲线404示出了传统的带有5V的p阱的MOS晶体管与带有叠加的n阱的MOS晶体管之间的掺杂密度的区别。如图4所示，在具有叠加的n阱的区域中，图3中所示的MOS晶体管300的掺杂密度高于传统的MOS晶体管。换言之，图3中所示的MOS晶体管300的其余区域的掺杂密度均与传统的MOS晶体管的类似。
根据实施例，图4中所示的传统的MOS晶体管的掺杂密度几乎是不变的。掺杂密度在大约1×1017/cm3至大约6×1017/cm3的范围内。相比之下，图3中所示的MOS晶体管300的掺杂密度却在更大范围内变化，其在与源极(P+区域322)相连的区域中具有更高的掺杂密度。根据实施例，图3所示的MOS晶体管300的掺杂密度在大约1×1017/cm3至大约8×1017/cm3的范围内。
图4示出：具有叠加的p阱的MOS晶体管在与源极(P+区域322)邻近的区域中可以获得更高的掺杂密度。这种更高的掺杂密度有助于改善MOS晶体管100的穿通窗口。例如，可以使用更短的沟道长度来进一步减小节距以及MOS晶体管300的导通电阻。
图5示出了根据实施例的MOS晶体管阵列的简化俯视图。可以通过N型晶体管形成MOS晶体管阵列。该MOS晶体管阵列可以包括两个MOS晶体管，每个均包括两个叠加的p阱(未示出但在图1中示出)。这些MOS晶体管共用漏极区域，即，N+区域514。第一MOS晶体管包括栅电极512，通过多个N+区域(诸如，502、506和510)所形成的源极区域，以及通过多个P+区域(诸如，504和508)所形成的主体接触件。
同样地，第二MOS晶体管包括栅电极516，通过多个N+区域(诸如，522、526和530)所形成的源极区域。第二MOS晶体管还包括通过多个P+区域(诸如，524和528)所形成的主体接触件。应该注意，N+区域(例如，N+区域502)和P+区域(例如，P+区域504)未按比例绘制。根据实施例，N+区域(例如，N+区域502)和其邻近的P+区域(例如，P+区域504)之间的实际比例在大约10∶1至大约2∶1的范围内。
MOS晶体管阵列另外包括围绕着第一MOS晶体管和第二MOS晶体管的P+拾取环532。P+拾取环532可以与MOS晶体管阵列的源极相连接。P+拾取环532有助于减小MOS晶体管阵列的主体效应。
与传统的MOS晶体管相比，图5的俯视图示出：以交替方式形成源极区域(例如，N+区域502、506和510)和主体接触件(例如，P+区域504和508)。因此，主体接触件(例如P+区域504)更接近源极区域(例如，N+区域502)。主体接触件和源极区域相接近有助于改善主体电流渗透效率(sink efficiency)。由此，可以减小主体电阻。另外，以交替的方式形成源极区域和主体接触件有助于减小MOS晶体管的节距。
图6示出了根据一个实施例的图5中所示的MOS晶体管阵列的截面图。沿着图5中所示的线A-A’获得该截面图。第一MOS晶体管和第二MOS晶体管共用相同的漏极(N+区域514)。每个MOS晶体管的结构均与图1中所示的类似，由此，为了避免重复此处不再对其进行详细论述。
图7示出了根据一个实施例的图5中所示的MOS晶体管的另一截面图。沿着图5中所示的线B-B’获得该截面图。除了N+区域502和522被P+区域508和528所替代以外，图7的截面图与图6类似。正如上面参考图5所描述的那样，P+区域508和528作为主体接触件。通过将主体接触件与N+区域502和522邻近设置(未相应地示出但图5中有所展示)，可以由此改善主体电流渗透效率。
图8示出了根据另一个实施例的MOS晶体管的简化俯视图。可以通过P型晶体管来形成图8中所示的MOS晶体管阵列。该MOS晶体管阵列可以包括两个MOS晶体管，每个包括两个叠加的n阱(未示出但图3中有所展示)。这些MOS晶体管共用漏极区域，即，P+区域814。
第一MOS晶体管包括栅电极812，通过多个P+区域(诸如，804和808)所形成的源极区域，以及通过多个N+区域(诸如，802、804和810)所形成的主体接触件。同样地，第二MOS晶体管包括栅电极816，通过多个P+区域(诸如，824和828)所形成的源极区域，以及通过多个N+区域(诸如，822、826和830)所形成的主体接触件。应该注意到，N+区域(例如，N+区域802)和P+区域(例如，P+区域804)未按比例绘制。N+区域和其邻近的P+区域之间的实际尺寸比例在大约2∶1至大约1∶10的范围内。
MOS晶体管阵列另外包括围绕着第一MOS晶体管和第二MOS晶体管的N+拾取环832。N+拾取环832可以与MOS晶体管阵列的高电压电势(未示出)相连接。N+拾取环532有助于减小MOS晶体管阵列的主体效应(bodyeffect)。
与图8的结构类似，以交替的方式形成源极区域(例如，P+区域804和808)和主体接触件(例如，N+区域802、806和808)。因此，主体接触件更接近源极区域。主体接触件和源极区域相接近有助于改善主体电流下沉效应。由此可以减小主体电阻。另外，以交替的方式形成源极区域和主体接触件有助于减小MOS晶体管的节距。
图9示出了根据一个实施例的图8中所示的MOS晶体管阵列的截面图。沿着图8中所示的线A-A’获得该截面图。第一MOS晶体管和第二MOS晶体管共用相同的漏极。另外，第一MOS晶体管和第二MOS晶体管相对于漏极(P+区域814)对称。每个MOS晶体管的结构均与图3中所示的类似，因此为了避免重复此处不再对其进行论述。
图10示出了根据一个实施例的图8中所示的MOS晶体管阵列的另一截面图。沿着图8中所示的线B-B’获得该截面图。除了N+区域802和822被P+区域808和828所替代以外，图10的截面图与图9类似。因此，在此处不再论述。
尽管已经详细地描述了本发明及其优势，但应该理解，可以在不背离所附权利要求限定的本发明主旨和范围的情况下，做各种不同的改变，替换和更改。
而且，本申请的范围并不仅限于本说明书中描述的工艺、机器、制造、材料组分、装置、方法和步骤的特定实施例。作为本领域普通技术人员应理解，通过本发明，现有的或今后开发的用于执行与根据本发明所采用的所述相应实施例基本相同的功能或获得基本相同结果的工艺、机器、制造，材料组分、装置、方法或步骤根据本发明可以被使用。因此，所附权利要求应该包括在这样的工艺、机器、制造、材料组分、装置、方法或步骤的范围内。

Claims (10)

1.一种半导体器件，包括：
第一导电性的衬底；
所述第一导电性的第一区域，形成在所述衬底上方；
所述第一导电性的第二区域，形成在所述第一区域中，其中，所述第二区域的掺杂密度高于所述第一区域的掺杂密度；
第二导电性的第一漏极/源极区域，形成在所述第二区域中；
所述第二导电性的第二漏极/源极区域，形成在所述衬底中并且远离所述第一源极/漏极区域；以及
所述第一导电性的拾取区域，形成在所述第二区域中并且邻近所述第一漏极/源极区域。
2.根据权利要求1所述的半导体器件，还包括：
所述第一导电性的主体接触区域，其中，从上向下看去，所述主体接触区域和所述第一漏极/源极区域以交替方式形成。
3.根据权利要求2所述的半导体器件，其中，所述第一漏极/源极区域与所述主体接触区域的比例在10∶1至大约2∶1的范围内。
4.根据权利要求1所述的半导体器件，还包括：
栅电极，形成在所述第一漏极/源极区域和所述第二漏极/源极区域之间。
5.根据权利要求4所述的半导体器件，还包括：
第一轻掺杂漏极/源极区域，形成为与所述第二区域中的所述第一漏极/源极区域邻近。
6.根据权利要求4所述的半导体器件，还包括：
第二轻掺杂漏极/源极区域，形成为与所述衬底中的所述第二漏极/源极区域邻近，其中，所述第二轻掺杂的漏极/源极区域位于所述栅电极下方。
7.根据权利要求4所述的半导体器件，还包括：
相对于所述栅电极对称的第一轻掺杂漏极/源极区域和第二轻掺杂漏极/源极区域。
8.根据权利要求1所述的半导体器件，其中，所述第一漏极/源极区域和所述拾取区域由电介质隔离部件分隔开。
9.一种器件，包括：
第一导电性的衬底；
栅电极，位于所述衬底上方；
第一漏极/源极区域和第二漏极/源极区域，在所述衬底中设置在所述栅电极的相对侧，其中，所述第一漏极/源极区域和所述第二漏极/源极区域具有第二导电性；
第一掺杂阱，具有所述第一导电性，形成在所述第一漏极/源极区域下方；
第二掺杂阱，具有所述第一导电性，形成在所述第一漏极/源极区域下方，其中，所述第一掺杂阱嵌在所述第二掺杂阱中，并且所述第一掺杂阱和所述第二掺杂阱被配置成使得掺杂密度从所述第一漏极/源极区域到所述第二漏极/源极区域逐渐减小；以及
所述第一导电性的主体接触区域，形成为与所述衬底中的所述第一漏极/源极区域邻近，其中，从上向下看去，所述主体接触区域和所述第一漏极/源极区域以交替的方式形成。
10.一种晶体管，包括：
第一晶体管，包括第一栅极、第一源极、第一漏极和第一主体接触件，其中：
从上向下看去，所述第一主体接触件和所述第一源极以交替方式形成；并且
所述第一源极形成在第一堆叠阱区域中，其中，所述第一堆叠阱区域包括：
第一导电性的第一区域，形成在所述第一导电性的衬底上方；和
所述第一导电性的第二区域，嵌在所述第一区域中；
第二晶体管，包括第二栅极、第二源极、第二漏极和第二主体接触件，其中，所述第一漏极和所述第二漏极连接在一起，并且其中：
从上向下看去，所述第二主体接触件和所述第二源极以交替的方式形成；并且
所述第二源极形成在第二堆叠阱区域中，其中，所述堆叠阱区域包括：
所述第一导电性的第三区域，形成在所述衬底上方；和
所述第一导电性的第四区域，嵌在所述第三区域中；以及
主体拾取环，围绕所述第一晶体管和所述第二晶体管。
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