CN103515324B - 集成高压器件的方法 - Google Patents

集成高压器件的方法 Download PDF

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Publication number
CN103515324B
CN103515324B CN201310257452.3A CN201310257452A CN103515324B CN 103515324 B CN103515324 B CN 103515324B CN 201310257452 A CN201310257452 A CN 201310257452A CN 103515324 B CN103515324 B CN 103515324B
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conduction type
trap
region
lightly doped
deeply
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CN103515324A (zh
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秀明土子
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Alpha and Omega Semiconductor Cayman Ltd
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Alpha and Omega Semiconductor Inc
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Priority claimed from US13/539,360 external-priority patent/US20130069157A1/en
Priority claimed from US13/539,339 external-priority patent/US20130071994A1/en
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Abstract

本发明主要提出了一种多个有源零部件的制备方法，例如双极晶体管、MOSFET、二极管等，在半导体衬底上，使工作电压较高的有源零部件可以与工作电压较低的器件一起形成在一个公共衬底上，并且引入制备工作电压较低的有源零部件的现有成熟的工艺流程。本发明还涉及一种器件的制备方法，通过在现有器件原有的制备过程中增加一些步骤，而不会对器件性能产生很大的影响，所制成的器件的工作电压高于具有相同功能的现有器件。

Description

集成高压器件的方法
技术领域
本发明涉及高压半导体器件及其制备过程，使工作电压较高的器件可以与工作电压较低的器件一起形成在公共衬底上，从而提供集成高压器件和低压器件的半导体器件及其制备方法，尤其是在半导体器件现有的工艺流程中增加高压器件的模块化工艺。
背景技术
比现有器件的额定电压更高的器件，通常需要集成在现有器件的芯片上，以满足新应用的需求。在许多情况下，要将电压较高的器件集成到现有的电压较低的器件中，需要彻底改变现有的电压较低的器件的成熟的制备工艺流程和/或制备条件，这会损害现有的低压器件的性能，器件模块也必须升级。为了避免新技术研发的冗长设计周期以及高成本，我们关注仅需对现有低压器件的工艺条件做细微更改的技术，从而对现有电压较低的器件性能产生最小的影响。
一般而言，在BCD（双极CMOS DMOS）或BiCMOS（双极CMOS）技术中，最高的工作电压受到PN结垂直结构的穿通击穿的局限。这种垂直结击穿是外延层厚度、掺杂浓度以及结深度的函数。图1A表示一种现有的垂直NPN晶体管（VNPN）（图中没有表示出N+发射极和P+基极传感器）器件300的示例，形成在由P衬底14构成的半导体芯片中。器件300是通过非外延工艺形成的，也就是说器件直接形成在P衬底14中，而不用在P衬底上方生长一个外延层。因此，轻掺杂的很深的N阱首先形成在P衬底的顶部，如图1A所示，在P衬底顶部，形成不同的器件结构，例如VNPN晶体管。轻掺杂的深N阱35形成在P衬底14的顶部，而器件300的详细结构并没有表示出来。多个N-阱22和P-阱26形成在深N阱35顶部，构成VNPN器件结构20。P阱48形成在P衬底的顶部，包围着很深的N型阱35，因此作为器件300的绝缘环，隔离半导体芯片的剩余区域，其他器件就形成在这些区域中。
图1B表示另一种现有的垂直NPN晶体管（VNPN）（图中没有表示出N+发射极和P+基极）器件301，形成在由P衬底14构成的半导体芯片中。器件301的结构除了器件301可选包含N掩埋层37之外，其他都与上述图1A中所示的器件300的结构类似，N掩埋层37形成在深N阱35底部、在P-阱26的下方附近。在这种情况下，N掩埋层37防止P-阱26和P衬底14之间发生增大器件301的最大工作电压的穿通。控制P-阱26的深度45，使器件301的性能达到最优。然而，P-阱26的底部在掩埋N层37的顶部附近，从而限制了垂直击穿电压，限制了器件301的工作电压。
器件300的制备过程从P衬底材料14开始，然后轻掺杂N型掺杂物，以便在P衬底14的顶部形成深N阱35。还可选择，通过在深N阱35底部，注入高能量、高密度的N-型掺杂物，制备器件301的N掩埋层37。然后，在深N阱35中，形成多个N-阱和P-阱，从衬底的顶面开始向下延伸，形成具有特定功能的双极晶体管或MOSFET。如果在同一个衬底上的单独区域中，集成工作电压较高的器件，需要彻底改变器件300的制备工艺流程和/条件。如果器件300的制备工艺和制备条件仍然不变的话，将会影响现有器件300的性能和绝缘性。
另一种方法是引入一个较轻掺杂层，降低掺杂浓度和浅P阱结。例如，HideakiTsuchiko在专利申请案US7019377中提出了一种含有高压肖特基势垒二极管和低压器件的集成电路。肖特基势垒二极管包括一个轻掺杂的浅p-阱，作为保护环，利用标准的、较重掺杂的较深的p-阱制备低压器件。通过包括轻掺杂的浅p-阱以及增加厚度的N-外延层等工艺，提高高压器件的穿通击穿电压，进而提高最大工作电压。每种方法都可以使击穿电压升高15V至30V。利用这两种方法制备的肖特基势垒二极管，可以使击穿电压升高30V至60V，而不会显著影响其他器件和结构的性能。
将这两种方法和器件布局相结合，可以在同一个芯片上集成高压和低压器件。然而，这些方法经常对现有的器件性能有轻微影响。这些器件需要对SPICE模块进行微调。因此，十分有必要研发一种新技术，仅需要在现有的低压工艺流程中插入几个步骤，而不会对低压器件的性能产生影响，就可以将高压器件集成到低压芯片中。
发明内容
本发明提出了一种在半导体衬底上，制备双极晶体管、MOSFET、二极管等多种有源器件的方法，使工作电压较高的有源器件可以和工作电压较低的有源器件一起形成在一个公共衬底上，并且引入制备工作电压较低的有源器件现有的成熟的工艺流程。
本发明还提出了一种通过在现有器件的原有制备工艺中增加一些步骤，无需改变器件性能，就能用于工作电压高于现有器件的器件制备方法。确切地说，该方法包括制备第一导电类型的衬底材料；制备第二导电类型的深掩埋区，包括一个轻掺杂区和一个重掺杂区，对高压器件来说，重掺杂区被衬底上方的轻掺杂区包围；在衬底上方，生长一个第一导电类型的外延层；在外延层的顶部，制备第二导电类型的轻掺杂深阱；并且制备高压和低压器件。
本发明提供的一种用于在半导体衬底上制备高压器件和低压器件的方法，包括以下步骤：提供一个第一导电类型的半导体衬底；在衬底的顶面上，生长一个第一导电类型的外延层，其中外延层的掺杂浓度与衬底的掺杂浓度相同；在低压器件区和高压器件区中，分别制备一个第二导电类型的轻掺杂阱，其中形成在低压器件区中的第二导电类型的轻掺杂阱，其深度从外延层的顶面开始到外延层厚度的一半，形成在高压器件区中的第二导电类型的轻掺杂阱，其深度从外延层的顶面开始一直延伸到半导体衬底；在高压器件区域中的轻掺杂阱的底部，制备与第一导电类型相反的第二导电类型的深掩埋重掺杂区；并且从轻掺杂阱的顶面开始，制备多个掺杂区，在低压器件区和高压器件区中，分别制备低压器件和高压器件。
上述的方法，在高压器件区域中的轻掺杂阱的底部，制备与第一导电类型相反的第二导电类型的深掩埋重掺杂区，还包括在衬底的顶面上生长一个第一导电类型的外延层之前，在高压器件的区域中半导体衬底顶部，制备一个与第一导电类型相反的第二导电类型的深掩埋重掺杂区。
上述的方法，第二导电类型的深掩埋注入区还包括，注入第二导电类型的第一离子，以及第二导电类型的第二离子，第一离子的扩散速度大于第二离子的扩散速度。
上述的方法，制备第二导电类型的深掩埋注入区还包括，一个或多个扩散工艺，扩散第一离子，从而向上延伸，与形成在外延层顶面上的轻掺杂深区合并在一起，构成一个很深的轻掺杂阱（很深是相对于形成在外延层顶面上的未与第一离子合并的原轻掺杂阱的原始深度而言）。
上述的方法，其中一个或多个热扩散工艺，还激活并扩散了衬底和外延层之间交界面附近的周围区域中的第二离子，构成一个被深掩埋轻掺杂区包围的深掩埋重掺杂区。
上述的方法，在低压器件区和高压器件区中的轻掺杂阱顶面上，形成多个掺杂区还包括，在深掩埋重掺杂区上方，形成一个第一导电类型的掺杂阱，距离深掩埋重掺杂区有一段底部距离，用于控制高压器件的击穿。
上述的方法，还包括在高压器件和低压器件的有源区周围，制备绝缘区。
在一种实施例中，本发明提供一种用于在半导体芯片上制备多个器件的方法，包括以下步骤：提供一个第一导电类型的衬底层；在第一器件有源区中衬底的顶部，注入与第一导电类型相反的第二导电类型的第一和第二离子，第一离子扩散得比第二离子更快；在衬底上方，生长一个第一导电类型的外延层；在第一器件和第二器件有源区中各制备一个第二导电类型的轻掺杂阱，其深度从外延层的顶面开始到第一器件和第二器件有源区中的外延层厚度的一半；在第一有源区中进行一次或多次热扩散工艺，使第一离子扩散，向上延伸并且与形成在外延层顶面上的轻掺杂阱合并在一起，构成一个很深的轻掺杂阱，使第二离子扩散成一个被所述的很深的轻掺杂阱包围着的深掩埋重掺杂区；并且从包围着深掩埋重掺杂区所述的很深的轻掺杂阱的顶面开始，制备一个第一导电类型的第一掺杂阱。
上述的方法，还包括调节第一导电类型的第一掺杂阱的底部和第二导电类型的深掩埋重掺杂区之间的间距，以设置第一器件的工作电压。
上述的方法，还包括制备一个第一导电类型的掩埋掺杂区，设置在第二导电类型的深掩埋重掺杂区上方，配置成一个降低表面电场层。
上述的方法，还包括制备绝缘区，包围着第一器件有源区，在第二器件有源区中的轻掺杂阱底部，制备第二导电类型的重掺杂掩埋注入区；并且在第二器件有源区中的重掺杂掩埋注入区上方，轻掺杂阱的顶面上，制备第一导电类型的第二掺杂阱。
在另一种实施方式中，本发明提供一种设置有第一器件和第二器件的半导体芯片，所述的半导体芯片包括：一个第一导电类型的衬底层；一个在衬底层顶面上的第一导电类型的外延层，其中外延层的掺杂浓度与衬底层的掺杂浓度相同；一个第二导电类型的很深的轻掺杂阱，形成于外延层的顶面，延伸到第一器件区域的衬底层的顶部；以及一个第二导电类型的轻掺杂阱，形成于外延层的顶面，深度为第二器件区域的外延层厚度的一半；以及一个第一导电类型的第一掺杂阱，形成在第一器件区域中很深的轻掺杂阱的顶部，以及一个第一导电类型的第二掺杂阱，形成在第二器件区域中的轻掺杂阱的顶部；其中第一器件的工作电压高于第二器件。
上述的半导体芯片，还包括一个与第一导电类型相反的第二导电类型的深掩埋重掺杂区，在衬底层和外延层之间的交界面处，被第一器件区域中很深的轻掺杂阱包围着，其中第一导电类型的第一掺杂阱的底部和第二导电类型很深的重掺杂植入区之间的距离，控制着第一器件的工作电压。
上述的半导体芯片，第一器件是由一个NPN双极晶体管构成的，其中第一掺杂阱配置成NPN双极晶体管的基极。
上述的半导体芯片，第一器件是由一个PNP双极晶体管构成的，第一掺杂阱作为PNP双极晶体管的集电极。
上述的半导体芯片，第一器件是由一个PN二极管构成的，第一掺杂阱作为PN二极管的阳极。
上述的半导体芯片，第一器件是由一个N通道DMOS晶体管构成的，第一掺杂阱作为DMOS晶体管的基极（或本体区）。
上述的半导体芯片，N通道DMOS晶体管还包括一个第一导电类型的掩埋掺杂区，设置在第二导电类型的深掩埋重掺杂区上方，作为一个降低表面电场层。
上述的半导体芯片，第一器件是由一个P通道DMOS晶体管构成的，第一掺杂阱作为DMOS晶体管的漏极。
下面将详细介绍这些和其他实施例。
附图说明
图1A和1B表示利用非外延工艺，在衬底上制备现有器件的剖面图。
图2表示依据本发明的一个方面，工作电压较高的器件与图1A所示的工作电压较低的器件制备在同一个公共衬底上的剖面图；
图3表示图2所示结构的制备方法的流程图；
图4-8表示在图3所示的制备工艺的各个不同的步骤中，图2所示的有源器件的剖面图。
图9表示依据本发明，工作电压较高的垂直NPN双极晶体管的剖面图；
图10表示依据本发明，工作电压较高的横向PNP双极晶体管的剖面图；
图11表示依据本发明，工作电压较高的PN二极管的剖面图；
图12表示依据本发明，工作电压较高的N-通道DMOS的剖面图；
图13表示依据本发明，工作电压较高的P-通道DMOS的剖面图；以及
图14表示依据本发明，带有三重降低表面电场的工作电压较高的横向N-通道DMOS的剖面图。
具体实施方式
依据本发明，参见图2，额定工作电压不同的第一器件和第二器件10和11形成在一个具有衬底14的公共半导体芯片上，外延层16生长在衬底14上方。掺杂外延层16，其掺杂的导电类型和浓度都与衬底材料14大致相同。对于图2所示的VNPN器件10和11（图中没有表示出N+发射极和P+基极传感器来），衬底14和外延层16为p-型。
器件10的低压器件结构20形成在衬底14中。没有表示出器件10的详细结构，轻掺杂的深N阱35形成在外延层16的顶部。多个N-阱22和P-阱26形成在深N阱35的顶部，P-阱48形成在外延层16的顶部，包围着深N阱35，作为器件结构20的绝缘区。P阱26和48中的掺杂浓度大于外延层16和衬底14。还可选择，一个n-型掺杂物的掩埋层（图中没有表示出）形成在深N阱35的底部，在P-型阱26下方附近。
除了器件10具有一个额外的外延层16形成在衬底14上方之外，其他都与图1A所示的器件300相同。由于外延层16的掺杂浓度与衬底14相同，外延层16可以看出是衬底14的延伸物，所以器件10的性能与器件300相同。器件300现有的制备工艺和制备条件可以整个作为制备器件10的一个工艺模块。
依据本发明，器件11也形成在衬底14和外延层16中。器件11包括一个形成在外延层16中的高压器件结构120。器件11包括轻掺杂的深N阱134，形成在外延层16的顶面上，向下延伸到衬底14的顶部。轻掺杂的深N阱134可以通过高能注入形成。还可选择，在深N阱134的底部和周围，制备一个n-型掺杂物的重掺杂掩埋层，也称为深掩埋层136，深N阱134在衬底14和外延层16之间延伸，从而进一步提高器件的最大工作电压。如下所述，制备深N阱134和掩埋层136：首先，在衬底14的顶面上注入一个深掩埋层，包括两个不同的种类，一个重掺杂的第一n-型部分，也称为深掩埋重掺杂区136，以及一个轻掺杂的第二n-型部分，也称为深掩埋轻掺杂区（图中没有表示出），第二部分包围着第一部分136；然后在衬底14上方生长外延层16，在外延层16的顶部制备一个轻掺杂的深N阱。我们希望，重掺杂的第一n-型部分136局限在衬底材料14和p-外延层16之间的交界面附近的区域。然后进行扩散过程。在指定的温度下，第二n-型掺杂物比第一n-型掺杂物部分扩散地更快。在本示例中，第一n-型掺杂物部分136中的掺杂物为锑或砷，第二n-型掺杂物部分中的掺杂物为磷。因此，第二n-型部分向上延伸，一部分P-型外延层16转换成轻掺杂的N型，同时形成在外延层16顶部的轻掺杂的深N阱从外延层16的表面开始向下，与第二n-型部分合并在一起，构成轻掺杂的深N阱134。然后，在深N阱134上方，形成多个N-阱122和P-阱126，在深N阱134周围的外延层16的顶部制备P-阱148。阱126和148的P-型掺杂物浓度大于外延层16和衬底14中的浓度。P-阱148作为器件120的绝缘环。还可选择，当绝缘环必须全部密封高压器件120时，绝缘环还包括一个与P阱148重叠的很深的P掩埋区（图中没有表示出）。应明确，绝缘环用作使器件120与周围器件绝缘，其中周围器件中的一个作为形成在衬底14和外延层16上的有源区20。
器件11需要考虑两种击穿电压。其一是掩埋区134和/或掩埋区136到有源区120外部的衬底材料14的击穿电压，可以通过134、136和14的掺杂浓度以及134和136的掺杂分布来控制该击穿电压。其二是有源器件120内部的垂直击穿电压，可以通过区域136和区域126之间的垂直距离51以及区域134、136和126的掺杂浓度和分布来控制该击穿电压。如果省去掩埋区136，那么可以通过区域126的底部和掩埋区134底部之间的垂直间距，以及区域134和126的掺杂浓度和分布来控制有源器件120内部的垂直击穿电压。器件120的最大工作电压受到第二垂直击穿的限制。
为了在半导体芯片上制备器件10和11，提供p-型衬底14，并且如图3-5所示，在步骤200中，在衬底14的顶面上，制备深掩埋区101。利用人们熟知的注入和掩膜工艺，注入掺杂物，获得所需的掺杂浓度。为了制备不带有深重掺杂掩埋区136的高压器件，深掩埋区101仅含有n-型掺杂物（例如磷）。为了制备带有深重掺杂掩埋区136的高压器件，深掩埋区101含有两种不同类型的n-型掺杂物，在指定温度下具有不同比例的扩散系数。在本例中，第一n-型掺杂物为锑或砷，第二掺杂物为磷，它们通过两步注入，都注入到衬底14上的同一个深掩埋区101中。低压器件区被光致抗蚀剂覆盖，阻止在此步骤中的离子注入。
参见图3和6，在步骤202中，外延层16生长在衬底14上方，覆盖所有的区域。我们希望，外延层16和衬底14一样，具有相同的p-型掺杂物和相同的掺杂浓度。在步骤204中，轻掺杂的深N阱13和103形成在外延层16上方，如图7所示。接下来进行热退火，在深掩埋区101中的掺杂物扩散到衬底和第一外延层16中，如图6所示，构成区域108和109，如图8所示。确切地说，锑和磷之间的扩散系数之差，也就是说，磷扩散得比锑快，使得区域109包围着区域108，如上所述。在步骤206中，参见图8A，p-型掺杂物分别注入到很深的N阱34、134顶部中的子区26、126中，以及外延层16顶部中的子区48、148中，然后将n-型掺杂物分别注入到很深的N阱34、134中的子区22、122中。然后，利用热循环将掺杂剂充分驱动到外延层16中，足以提供所需的掺杂浓度和布局。
就其本身而言，区域109中的轻掺杂磷向上延伸到P阱126，并且将P-型外延层16的一部分转变成轻掺杂N型，而形成在外延层16顶部的轻掺杂的深N阱103从外延层16的表面开始向下，与区域109合并在一起，构成轻掺杂的深N阱134。通过P阱148形成绝缘环。还可选择，如图8B所示，绝缘环也可以包括一个很深的P掩埋区146，当进行扩散步骤时，延伸并且与P阱148合并在一起。
参见图2，区域136（如果省去136的话，就是134的底部）和区域126之间的垂直间距51是可控的。因此，器件120具有较高的垂直击穿电压，因此，工作电压高于器件20的工作电压。
参见图3和图8A，在步骤206中，通过离子注入到N-阱区22和P-阱区26，构成器件10的有源区，配置器件10的特殊器件结构，通过离子注入到N-阱区122和P-阱区126，配置器件11的特殊器件结构。应明确，尽管为了便于讨论，只介绍了一个单独的步骤，但是在步骤206中的n-型和p-型掺杂物注入发生在传统的掩膜工艺、离子注入和高温驱动的多个步骤中。如上所述，制备器件300的成熟的工艺和条件可以整体转移到从步骤204开始进行。应明确，具有较低额定电压的现有器件以及本发明具有较高额定电压的新增的器件，都将在同一个衬底材料上同时存在，而不会相互影响。
如图8A所示的工艺步骤，电压较高的器件与电压较低的器件集成在一个半导体芯片上。应明确，器件10或11可以是二极管、双极晶体管、MOSFET或其他器件。还应明确，利用本发明所述工艺，任意器件组合都可以集成在一起，而不相互影响。图9表示器件11的实施例，作为一个高压垂直NPN晶体管（VNPN）400，与现有电压器件（图中没有表示出）集成在一起。除了器件400的有源区含有一个设置在高压P-阱126中的重掺杂N+区130之外，其他都与器件11相同。重掺杂N+区130、P-阱126以及P-阱126下方的深掩埋N区134构成一个垂直NPN，N+区130作为发射极、P-阱126作为基极，HVPW126下方的N区作为集电极。设置在HVPW126中的P+区128为基极提供接触传感器，而设置在HVPW126外部的外延层16顶部的N区122为集电极提供接触传感器。基极和集电极接触传感器可以作为布局中的环形。基极区126的底部和深掩埋重掺杂区136（如果省去136的话，就是134的底部）的顶部之间的间距51，控制NPN晶体管的垂直集成，从而限制NPN晶体管400的工作电压。
图10表示器件11的一个实施例，作为一个高压横向PNP晶体管（LPNP）410，与现有的低压器件（图中没有表示出）集成在一起。除了器件410的有源区配置成横向PNP，包括P区127作为发射极，P环125作为集电极，包围着中心P发射极区127，N环123作为基极接触传感器（base contact pickup），包围着集电极P环125和发射极P区127。基极区包括深N阱134和深掩埋重掺杂区136，围在轻掺杂深N阱134中。P集电极区125的底部和深掩埋重掺杂区136的顶部（或者如果136省去的话，就是134的底部）之间的间距51，控制PNP晶体管的垂直击穿，从而限制PNP晶体管410的工作电压。
图11表示器件11的一个可选实施例，作为一个高压PN二极管420，与现有的低压器件（图中没有表示出）集成在一起。除了器件420的有源区配置成一个PN二极管之外，包括P区162作为阳极，N区160作为含有一部分深N阱134的阴极的接触传感器（contact pickup for the cathode），其他都与器件11相同。P阳极区162的底部和深掩埋重掺杂区136的顶部（或者如果136省去的话，就是134的底部）之间的间距51，控制二极管的垂直击穿，从而限制二极管420的工作电压。
图12表示器件11的一个可选实施例，作为一个高压N-通道横向DMOS（LDMOS），与现有的低压器件（图中没有表示出）集成在一起。除了器件430的有源区配置成N-通道LDMOS，包括一个设置在P-阱156中的N+源极区157以及一个设置在N-阱154中的N+漏极接触传感区155之外，其他都与器件11相同。P-阱156作为本体，含有N-阱154和深N阱134的N区作为漏极。场氧化物152形成在N-阱154上方，紧挨着漏极接触传感区155，绝缘栅极150设置在P-阱156和N-阱154上方，从重叠的一部分源极区157开始，延伸到重叠的一部分场氧化物152。P本体区156的底部和深掩埋重掺杂区136的顶部（或者如果省去136的话，就是134的底部）之间的间距51，控制N-通道LDMOS的垂直击穿，从而限制LDMOS430的工作电压。
如图13所示，除了P+源极区175设置在作为本体的N-阱174中，P+漏极接触传感器177设置在作为漏极的P-阱176中之外，可以利用相同的方式制备P-通道LDMOS440。P漏极区176的底部和很深的掩埋重掺杂区136的顶部（或者如果省去136的话，就是134的底部）之间的间距51，控制P-通道LDMOS的垂直击穿，从而限制LDMOS440的工作电压。
图14表示器件11的一个可选实施例，作为一个电压很高的N-通道横向DMOS（LDMOS），与现有的低压器件（图中没有表示出）集成在一起。器件450中除去降低表面电场区（RESURF region）137在深N阱134的顶部中作为很深的P-阱（DeepP-Well，简称DPW）之外，其他都与器件430相同。DPW区137在反向偏压下耗尽，起到三重降低表面电场的功能，从而提高上述器件430的性能。利用高能注入机，从外延层16的顶面上离子注入，在制备P阱156和N阱154之前，形成DPW区137。我们希望，浮动DPW区137在P本体区156附近。P本体区156的底部和很深的掩埋重掺杂区136的顶部（或者如果省去136的话，就是134的底部）之间的间距51，控制N-通道LDMOS的垂直击穿，从而限制LDMOS450的工作电压。
应明确，以上说明仅仅是本发明的一个示例，在不违背本发明意图及范围内的修正，都不应让为是对本发明范围的局限。因此，本发明的范围应由所附的权利要求书及其全部范围内的等效内容所限定。

Claims (19)

1.一种用于在半导体衬底上制备高压器件和低压器件的方法，其特征在于，包括以下步骤：
提供一个第一导电类型的半导体衬底；
在衬底的顶面上，生长一个第一导电类型的外延层，其中外延层的掺杂浓度与衬底的掺杂浓度相同；
在低压器件区和高压器件区中，分别制备一个第二导电类型的轻掺杂阱，其中形成在低压器件区中的第二导电类型的轻掺杂阱，其深度从外延层的顶面开始到外延层厚度的一半，形成在高压器件区中的第二导电类型的轻掺杂阱，其深度从外延层的顶面开始一直延伸到半导体衬底；
在高压器件区域中的轻掺杂阱的底部，制备与第一导电类型相反的第二导电类型的深掩埋重掺杂区；
并且从轻掺杂阱的顶面开始，制备多个掺杂区，在低压器件区和高压器件区中，分别制备低压器件和高压器件。
2.根据权利要求1所述的方法，其特征在于，在高压器件区域中的轻掺杂阱的底部，制备与第一导电类型相反的第二导电类型的深掩埋重掺杂区，还包括在衬底的顶面上生长一个第一导电类型的外延层之前，在高压器件的区域中半导体衬底顶部，制备一个与第一导电类型相反的第二导电类型的深掩埋重掺杂区。
3.根据权利要求2所述的方法，其特征在于，第二导电类型的深掩埋重掺杂区还包括，注入第二导电类型的第一离子，以及第二导电类型的第二离子，第一离子的扩散速度大于第二离子的扩散速度。
4.根据权利要求3所述的方法，其特征在于，制备第二导电类型的深掩埋重掺杂区还包括，一个或多个扩散工艺，扩散第一离子，从而向上延伸，与形成在外延层顶面上的轻掺杂深区合并在一起，构成一个很深的轻掺杂阱。
5.根据权利要求4所述的方法，其特征在于，其中一个或多个扩散工艺，还激活并扩散了衬底和外延层之间交界面附近的周围区域中的第二离子，构成一个被深掩埋轻掺杂区包围的深掩埋重掺杂区。
6.根据权利要求5所述的方法，其特征在于，在低压器件区和高压器件区中的轻掺杂阱顶面上，形成多个掺杂区还包括，在深掩埋重掺杂区上方，形成一个第一导电类型的掺杂阱，距离深掩埋重掺杂区有一段底部距离，用于控制高压器件的击穿。
7.根据权利要求1所述的方法，其特征在于，还包括在高压器件和低压器件的有源区周围，制备绝缘区。
8.一种用于在半导体芯片上制备多个器件的方法，其特征在于，包括以下步骤：
提供一个第一导电类型的衬底层；
在第一器件有源区中衬底层的顶部，注入与第一导电类型相反的第二导电类型的第一和第二离子，第一离子扩散得比第二离子更快；
在衬底层上方，生长一个第一导电类型的外延层，其中外延层的掺杂浓度与衬底层的掺杂浓度相同；
在第一器件和第二器件有源区中各制备一个第二导电类型的轻掺杂阱，其深度从外延层的顶面开始到第一器件和第二器件有源区中的外延层厚度的一半；
在第一器件有源区中进行一次或多次热扩散工艺，使第一离子扩散，向上延伸并且与形成在外延层顶面上的轻掺杂阱合并在一起，构成一个很深的轻掺杂阱，使第二离子扩散成一个被所述的很深的轻掺杂阱包围着的深掩埋重掺杂区；并且
从包围着深掩埋重掺杂区所述的很深的轻掺杂阱的顶面开始，制备一个第一导电类型的第一掺杂阱。
9.根据权利要求8所述的方法，其特征在于，还包括调节第一导电类型的第一掺杂阱的底部和第二导电类型的深掩埋重掺杂区之间的间距，以设置第一器件的工作电压。
10.根据权利要求8所述的方法，其特征在于，还包括制备一个第一导电类型的掩埋掺杂区，设置在第二导电类型的深掩埋重掺杂区上方，配置成一个降低表面电场层。
11.根据权利要求8所述的方法，其特征在于，还包括制备绝缘区，包围着第一器件有源区，在第二器件有源区中的轻掺杂阱底部，制备第二导电类型的重掺杂掩埋注入区；并且在第二器件有源区中的重掺杂掩埋注入区上方，轻掺杂阱的顶面上，制备第一导电类型的第二掺杂阱。
12.一种设置有第一器件和第二器件的半导体芯片，其特征在于，所述的半导体芯片包括：
一个第一导电类型的衬底层；
一个在衬底层顶面上的第一导电类型的外延层，其中外延层的掺杂浓度与衬底层的掺杂浓度相同；
一个第二导电类型的很深的轻掺杂阱，形成于外延层的顶面，延伸到第一器件区域的衬底层的顶部；以及
一个第二导电类型的轻掺杂阱，形成于外延层的顶面，深度为第二器件区域的外延层厚度的一半；以及
一个第一导电类型的第一掺杂阱，形成在第一器件区域中很深的轻掺杂阱的顶部，以及一个第一导电类型的第二掺杂阱，形成在第二器件区域中的轻掺杂阱的顶部；其中第一器件的工作电压高于第二器件。
13.根据权利要求12所述的半导体芯片，其特征在于，还包括一个与第一导电类型相反的第二导电类型的深掩埋重掺杂区，在衬底层和外延层之间的交界面处，被第一器件区域中很深的轻掺杂阱包围着，其中第一导电类型的第一掺杂阱的底部和第二导电类型的深掩埋重掺杂区之间的距离，控制着第一器件的工作电压。
14.根据权利要求12或13所述的半导体芯片，其特征在于，第一器件是由一个NPN双极晶体管构成的，其中第一掺杂阱配置成NPN双极晶体管的基极。
15.根据权利要求12或13所述的半导体芯片，其特征在于，第一器件是由一个PNP双极晶体管构成的，第一掺杂阱作为PNP双极晶体管的集电极。
16.根据权利要求12或13所述的半导体芯片，其特征在于，第一器件是由一个PN二极管构成的，第一掺杂阱作为PN二极管的阳极。
17.根据权利要求12或13所述的半导体芯片，其特征在于，第一器件是由一个N通道DMOS晶体管构成的，第一掺杂阱作为DMOS晶体管的基极。
18.根据权利要求17所述的半导体芯片，其特征在于，N通道DMOS晶体管还包括一个第一导电类型的掩埋掺杂区，设置在第二导电类型的深掩埋重掺杂区上方，作为一个降低表面电场层。
19.根据权利要求12或13所述的半导体芯片，其特征在于，第一器件是由一个P通道DMOS晶体管构成的，第一掺杂阱作为DMOS晶体管的漏极。
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