CN103515256A - 用于制造芯片封装的方法、芯片封装和晶圆级封装 - Google Patents
用于制造芯片封装的方法、芯片封装和晶圆级封装 Download PDFInfo
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Abstract
本发明涉及用于制造芯片封装的方法、芯片封装和晶圆级封装。提供了一种用于制造芯片封装的方法。该方法包括:在载体之上形成层;在该层之上形成进一步载体材料;选择性地移除进一步载体材料的一个或者多个部分,由此从进一步载体材料释放该层的一个或者多个部分;和,经由该层将包括一个或者多个接触垫的芯片附着到载体。
Description
技术领域
各种实施例一般地涉及一种用于制造芯片封装的方法、一种用于制造晶圆级封装的方法、一种芯片封装和一种晶圆级封装。
背景技术
芯片可以以面板形式或者晶圆形式例如以重构晶圆形式、以芯片封装结构诸如以嵌入晶圆级球栅阵列(eWLB)一起地规则地布置。可以被称作重分布层(RDL)的金属层可以用作到外部连接垫的电连接。嵌入晶圆级封装例如嵌入晶圆级球栅阵列(eWLB)可能具有几个相关的问题,其中大部分可以归因于塑封材料(mold compound)。问题可以包括翘曲、变形例如x-y变形、从材料除气、温度循环对板(TCoB)循环耐久性的问题、不良导热率和与接触相关的困难例如IC的后侧引起接触。
发明内容
各种实施例提供一种用于制造芯片封装的方法,该方法包括在载体之上形成层;在该层之上形成进一步载体材料;选择性地移除进一步载体材料的一个或者多个部分由此从进一步载体材料释放该层的一个或者多个部分;和,经由该层将包括一个或者多个接触垫的芯片附着到载体。
附图说明
在图中,类似的附图标记贯穿不同视图地一般地引用相同的部分。附图不是必要地按照比例的,相反一般地着重于示意本发明的原理。在以下说明中,参考以下的图描述了本发明的各种实施例,其中:
图1根据一个实施例示出一种用于制造芯片封装的方法;
图2A到2G根据一个实施例示出一种用于制造芯片封装的方法;
图3根据一个实施例示出一种用于制造晶圆级封装的方法;
图4根据一个实施例示出一种用于制造芯片封装的方法;
图5根据一个实施例示出一种芯片封装;
图6根据一个实施例示出一种芯片封装;并且
图7根据一个实施例示出一种用于制造芯片封装的方法;
图8A到8D根据一个实施例示出一种用于制造芯片封装的方法;以及
图9根据一个实施例示出一种芯片封装。
具体实施方式
以下详细说明参考通过示意方式示出其中可以实践本发明的具体细节和实施例的附图。
单词“示例性”在这里用于意味着“用作一个实例、事例或者示意”。在这里描述为“示例性”的任何实施例或者设计并不是必要地被理解为相对于其它实施例或者设计是优选的或者有利的。
在这里用于描述在侧面或者表面“之上”形成一种特征例如层的单词“之上”可以用于意味着该特征例如该层可以“直接地在所指侧面或者表面上”例如与其直接接触地形成。在这里用于描述在侧面或者表面“之上”形成一种特征例如层的单词“之上”可以用于意味着该特征例如该层可以带有在所指侧面或者表面和所形成的层之间布置的一个或者多个另外的层地“间接地在所指侧面或者表面上形成”。
各种实施例提供一种用于执行晶圆和/或面板的重构的方法。
各种实施例提供一种可以不要求塑封材料的嵌入晶圆级封装。
各种实施例提供一种重构晶圆,其中可以在金属薄板和/或箔片和/或板的空穴中精确地和/或弹性地和/或平坦地布置集成电路芯片。
各种实施例提供一种可以包括其中可以在金属薄板和/或箔片和/或板中构造空穴的、例如包括铜和/或不锈钢的金属薄板和/或金属箔片和/或金属板的嵌入晶圆级封装,其中空穴可以稍微大于所要安装的集成电路(IC)芯片。金属薄板和/或金属箔片和/或金属板可以通过蚀刻或者喷砂构造,并且通过所述构造产生的空穴可以至少部分地填充有胶合剂例如导电胶、焊接材料或者膏剂。
根据各种实施例,蚀刻终止层可以用于精确地在金属薄板和/或金属箔片和/或金属板中形成空穴,并且蚀刻终止层还可以被用作用于将IC芯片附着到金属薄板和/或金属箔片和/或金属板的附着层。
图1根据一个实施例示出用于制造芯片封装的方法100。方法100可以包括:
在载体之上形成层(在110中);
在该层之上形成进一步载体材料(在120中);
选择性地移除进一步载体材料的一个或者多个部分由此从进一步载体材料释放该层的一个或者多个部分(在130中);和
经由该层将包括一个或者多个接触垫的芯片附着到载体(在140中)。
图2A到2G根据一个实施例示出用于制造芯片封装的方法200。
方法200可以包括如在图2A的210中所示在载体204之上形成层202。载体204可以包括导电薄板。载体204可以包括导电箔片。载体204可以包括导电板。载体204可以包括金属。载体204可以包括选自以下一组材料的至少一种材料,该组材料包括:铜、镍、铁、银、金、钯、铜合金、镍合金、铁合金、银合金、金合金、钯合金。例如,载体204可以包括CuFe2P,例如载体204可以包括CuFe01P。载体204可以包括引线框架材料。载体204可以包括不锈钢。载体204可以包括范围从大约50μm到大约1000μm、例如大约100μm到大约800μm、例如大约100μm到大约300μm的厚度。载体204可以包括但是不限于包括以下尺寸。如果具有圆形或者圆状形式,则载体204可以具有例如大约200mm或者大约300mm或者大约450mm的直径。如果具有矩形或者正方形形式,则载体204可以具有例如200mmx200mm或者300mmx450mm或者450x600mm的长度x宽度。载体的这些尺寸可以依赖于设备。
可以在载体204之上形成层202并且可以在层202之上形成进一步载体材料206。层202可以在进一步载体材料206的蚀刻期间用作蚀刻终止层,例如用于载体204的保护层。层202可以进一步用作将进一步载体材料206附着到载体204的附着层。进而,除了用作蚀刻终止层和用作在进一步载体材料206和载体204之间的附着层,层202还可以用作将芯片附着到载体204的贴片材料的支撑层。因此,可以理解,在这里描述的层202可以不仅包括单层,而且根据各种其它实施例可以包括多于一个层,例如多层布置,从而实现上述功能。
层202(单层或者多层)可以用作用于将进一步载体材料206附着到载体204的附着层的一个部分、用作用于载体204的蚀刻终止保护层,并且最终用作芯片到载体204的附着层。根据各种实施例的层202在图8A到8E中示出并且将在下面进一步详细地描述。
层202可以包括范围从大约1μm到大约50μm、例如大约10μm到大约40μm、例如大约15μm到大约35μm的厚度。可以理解,这些厚度可以依赖于层202的材料和用于沉积层202的沉积方法。此外,这些厚度可以依赖于载体204的粗糙度。可以进一步在下面描述这些厚度。层202可以具有尽可能均匀的厚度。
通常,可以利用选自以下一组方法的至少一种方法沉积层202,该组方法包括:电镀、化学镀、电流沉积、层叠、箔片层叠、溅射、蒸发、化学汽相沉积、等离子体增强化学汽相沉积、旋涂、喷射。这些方法可以被选择性地用于沉积单层202或者层202的多层。
根据在芯片后侧(在以后示出)和载体204之间是否要求导电连接,可以相应地选择用于层202的材料。例如,根据各种实施例,层202可以包括导电材料。根据其它实施例,层202可以包括电绝缘材料例如电绝缘层。可以理解,逻辑芯片可以允许或者电绝缘贴片或者导电贴片,而带有电后侧触点的功率半导体芯片可以仅仅允许导电贴片。因此,如果芯片218包括逻辑芯片,则除了上述功能,层202可以在芯片附着侧和载体204之间提供电绝缘或者电路径。如果芯片218包括功率半导体芯片,则层202可能要求在芯片218附着到载体204的一侧和载体204之间的导电连接。因此,层202可以根据芯片封装的要求而被选择和/或处理。
图8A示出根据各种实施例的部分层202布置。
根据一个实施例,层202可以包括单一导电层。层202可以包括例如可以例如通过电流沉积而沉积的单一焊料层202A。作为焊料层202A的层202可以用作在进一步载体材料206和载体204之间的焊接联结层。在随后的过程中,焊料层202A可以用作蚀刻终止层。可以理解,在蚀刻之后,可能不适合于再熔化的金属间相例如Cu-Sn界面可以在焊料层202A上形成,并且可以随后沉积粘结层(在以后描述)以例如通过附着或者烧结在芯片和载体204之间提供联结。
根据另一个实施例,替代焊料层202A地,层202可以包括单层的导电胶合剂202B。导电胶合剂202B可以用作在进一步载体材料206和载体204之间的附着层,并且进一步用作蚀刻终止层。在蚀刻之后,可以可选地要求另外的粘结层以经由单层202B将芯片附着到载体204。
根据另一个实施例,层202可以包括单层202C。作为一个实例,层202C可以包括可以用作在进一步载体材料206和载体204之间的烧结联结层并且进一步用作蚀刻终止层的纳米膏剂例如银纳米膏剂。烧结层202C可能需要在以后被进一步处理,或者可能需要执行随后的过程以确保芯片可以经由单一烧结层202C附着到载体204。这种进一步的过程可以包括在烧结层202C之上形成例如包括导电胶合剂或者焊料或者导电膏剂的附着层。
图8B示出根据各种实施例的层202布置。根据一个实施例,层202可以包括电绝缘胶合剂202D。电绝缘胶合剂层202D可以包括电绝缘材料,例如包括选自以下一组材料的至少一种材料,该组材料包括:聚酰亚胺、苯并环丁烯(BCB)、环氧树脂。可以利用选自以下一组方法的至少一种方法在载体204之上形成电绝缘胶合剂层202D,该组方法包括:旋涂、喷射、印刷、层叠。
电绝缘胶合剂层202D可以用作蚀刻终止层、用于将进一步载体材料206附着到载体204的附着层和进一步用于将芯片附着到载体204的贴片中的至少一个。
特别地,聚酰亚胺可以通过固化实现所有的三个功能,例如用于将进一步载体材料206附着到载体204,用作蚀刻终止层,并且然后再加热,例如用于将芯片附着到载体204。
图8C示出根据一个实施例的芯片封装的一个部分。根据各种其它实施例,层202可以包括多层。根据该实施例,可以在载体204和层202A、202B或者202C中的至少一个之间形成可选的导电层202E。
可以理解,根据各种实施例,不同类型的层202A、202B、202C、202D可以被组合,或者各自地或者与其它层相组合地使用,以形成可以提供在进一步载体材料206和载体204之间的附着层、作为用于载体204的蚀刻终止层和作为在芯片和载体204之间的粘结层的功能的层202布置。
进一步参考过程210,在根据关于图8A到8D中的至少一幅描述的过程在载体204之上沉积层202之后,可以在层202之上形成进一步载体材料206。
进一步载体材料206可以包括范围从大约60μm到大约200μm、例如大约80μm到大约180μm、例如大约100μm到大约150μm的厚度。进一步载体材料206可以包括与载体204相同的材料或者不同的材料。
通常,可以利用选自以下一组方法的至少一种方法沉积进一步载体材料206,该组方法包括:层叠、烧结、胶接或者印刷。当选择用于进一步载体材料206的沉积方法时,层202材料可以被加以考虑。
根据各种实施例,进一步载体材料206可以包括可以被层叠和/或烧结到层202的层例如箔片,诸如铜箔。
例如,如果层202包括作为最顶层的包括纳米膏剂诸如银纳米膏剂的层202C,则进一步载体材料206可以被烧结到层202的烧结层202C。
根据另一个实施例,例如,如果层202包括作为最顶层的包括胶合剂的层202B或者层202D,则进一步载体材料206可以附着到例如被胶合剂例如经由层202的电绝缘胶合剂层202D或者导电胶合剂202B胶合到载体204。
根据一个实施例,例如,如果层202包括作为最顶层的焊料层202A,则进一步载体材料206可以被焊料层例如层202的焊料层202A焊接到载体204。
根据各种实施例,可以甚至能够替代在分离的过程中形成层202和进一步载体材料206地,可以在载体204之上一起地形成层202和进一步载体材料206。例如,层202和进一步载体材料206可以形成可以附着到例如层叠到载体204的单一箔片例如树脂涂覆铜(RCC)箔片的一个部分。箔片可以包括包括电绝缘层和铜涂层即206的树脂。在此情形中,可以通过箔片层叠在载体204之上与进一步载体材料206一起地同时地形成层202(见图8D)。
根据各种实施例,可以甚至能够在于载体之上形成层202和进一步载体材料206之前,可以例如根据与在过程210中描述的类似的方法在进一步载体材料206之上沉积层202。
根据各种其它实施例,特别地在要求大的数量时,可以通过卷到卷过程将进一步载体材料206结合或者附着到载体204。进一步载体材料206的卷的一个部分可以经由可以在载体204和进一步载体材料206之间例如经由喷射而沉积的层202而被结合到载体204的卷的进一步的部分。根据各种实施例,可以甚至能够在于载体之上形成层202和进一步载体材料206之前,可以例如根据与在过程210中描述的类似的方法在进一步载体材料206之上沉积层202。
方法200可以包括选择性地移除进一步载体材料206的一个或者多个部分208由此如在图2B的220中所示从进一步载体材料206释放层202的一个或者多个部分212。进一步载体材料206的一个或者多个部分208可以被选择性地蚀刻,其中可以包括层202A、202B、202C、202D、202E中的至少一个的层202可以用作蚀刻终止层。换言之,通过选择性地耐受被用于蚀刻进一步载体材料206的蚀刻剂,层202可以防止载体204的蚀刻,即可以保护载体204以免被蚀刻。可以利用选自以下一组方法的至少一种方法选择性地移除进一步载体材料206的一个或者多个部分208,该组方法包括:化学蚀刻、喷砂。特别地当层202包括胶合剂时可以使用喷砂。换言之,层202可以耐受用于选择性地移除一个或者多个部分208的这些方法。
从进一步载体材料206释放的层202的一个或者多个部分212可以共同地被由进一步载体材料206覆盖的层202的进一步部分214结合。换言之,进一步部分214可以被进一步载体材料206的、未被选择性移除过程移除的部分覆盖。所移除的一个或者多个部分208可以稍微地大于将被置于该一个或者多个部分208内的芯片218的尺寸。可以理解,移除一个或者多个部分208可以被称作在堆叠的载体204-层202-进一步载体材料206布置中形成一个或者多个空穴208。
可以理解,除了形成一个或者多个空穴208,还可以在蚀刻过程期间在进一步载体材料206中形成其它孔908(见图9)。孔908可以小于空穴208并且可以被用于通过进一步载体材料206在孔908中形成到载体204的电连接956。
在蚀刻后,如果要求的话,则可以在层202的所释放的一个或者多个部分212上执行中间过程,以经由层202将芯片附着到载体。根据层202并且根据蚀刻材料,层202的所释放的一个或者多个部分212可以能够或者可以不能够在蚀刻之后用作芯片附着材料。
在层202可以不能够用作芯片附着材料的情形中,可以在层202之上形成附着层216。在其它情形中,可以移除层202的某些部分。例如,如果层202包括单层例如聚酰亚胺箔片202D,则可以是可以移除层202D的某些部分的情形。可选地,如在图9中所示,可以移除层202D的、可以通过形成空穴208而被暴露的部分,并且进而还可以移除层202D的、通过形成孔908而被暴露的部分。可以例如使用背溅射(back-sputtering),如果层202D是薄的,或者例如激光作用来执行移除。随后,可以例如通过印刷在空穴208中在载体204之上形成附着层216,例如导电胶合剂或者焊料或者纳米膏剂。在以后,可以在孔908中形成进一步导电材料956以通过进一步载体材料206形成到载体204的电连接956。可以理解,通过蚀刻,除了移除进一步载体材料206的一个或者多个部分,还可以能够选择性地移除载体204的一个或者多个部分。换言之,可以选择性地移除载体204和进一步载体材料206中的至少一个的一个或者多个部分。可以理解,载体204和进一步载体材料206中的至少一个甚至可以被如此构造,使得至少一个可以包括导电重分布层,例如,如果层202包括电绝缘层的话。
附着层216可以是导电胶合剂和/或焊接材料并且可以在空穴208中沉积。可以如此选择附着层216,使得芯片218可以经由层202和附着层216附着到载体204。
可以利用一系列方法例如焊接、扩散焊接或者粘结剂结合而将芯片218附着到载体204。
对于焊接例如扩散焊接,附着层216可以包括焊接材料,该焊接材料包括选自以下一组材料的至少一种材料,该组材料包括:银、银合金、铅、铜、锡、锡合金。
如果使用粘结剂结合,则附着层216可以包括导电材料例如导电粘结剂。附着层216可以包括例如环氧树脂、带有导电颗粒例如金、银、铜颗粒的聚合物。例如,附着层216可以包括导电材料,该导电材料包括选自以下一组材料的至少一种材料,该组材料包括:导电胶合剂、导电粘结剂、导电聚合物、导电有机聚合物、导电环氧树脂。进而,附着层216可以被丝网印刷到层202上。
对于非导电附着,附着层216可以包括电绝缘材料例如粘结剂,例如胶合剂,包括选自以下一组材料的至少一种材料,该组材料包括:聚合物、有机聚合物、环氧树脂。如果层202已经包括电绝缘材料202C,例如durimide聚酰亚胺例如苯并环丁烯,则附着层216可以是不必要的,因为电绝缘材料202C可以在芯片和载体204之间被用作蚀刻终止层以及粘结胶合剂这两者。
可以在层202的、从进一步载体材料206释放的一个或者多个部分212之上,即在堆叠的载体204-层202-进一步载体材料206布置的一个或者多个空穴208内形成附着层216。可以通过印刷的发展和切片刮刀(sliced squeegee)克服在空穴中印刷的难题。附着层216可以不限于具有特定厚度,而是根据各种实施例可以具有范围从大约3μm到大约70μm、例如大约15μm到大约60μm、例如大约20μm到大约40μm的厚度。可以利用选自利用以下一组方法的至少一种方法在上面沉积附着层216,该组方法包括:印刷或者箔片联结或者墨水喷射或者分配。附着层216可以在层202的、从进一步载体材料208释放的一个或者多个部分212之上形成,并且芯片218可以经由附着层216附着到载体204。
在图2C的230中,可以执行芯片联结。可以通过附着例如胶接、焊接来执行芯片联结。包括一个或者多个接触垫222的芯片218可以经由层202,例如层202的、从进一步载体材料202释放的一个或者多个部分212附着到载体204。可以理解,芯片218可以经由附着层216附着到载体204。例如附着层216可以将芯片218附着到可以在载体204之上形成并且附着到载体204的层202。根据其它实施例,替代或者除了在一个或者多个部分212之上沉积地,附着层216可以在芯片218的、将被附着到层202的一侧(称作被附着侧)之上形成例如沉积。被附着侧可以包括芯片218的后侧或者芯片218的前侧。图2C特别地示出被附着侧可以包括芯片218的后侧,并且一个或者多个接触垫222可以在芯片218的前侧之上形成。根据其它实施例,层202例如层202C,聚酰亚胺,可以是将芯片218附着到层202的附着层216。
芯片218可以不限于具有特定厚度,然而,各种实施例可以包括具有范围从大约20μm到大约250μm、例如大约50μm到大约150μm、例如大约60μm到大约100μm的厚度的芯片218。所要安装的IC芯片218可以可替代地或者另外地在它们的后侧上携带可以被预先送至晶圆例如包括IC芯片的硅晶圆的贴片薄膜或者箔片(附着层216)。IC芯片越大并且金属箔片(附着层216)越坚固,利用可以具有更小的杨氏模量(E)例如3MPA的胶合剂例如粘结剂越加重要。如果优先地具有更高的电流密度,则可以替代胶接地使用焊接方法,例如扩散焊接方法或者纳米膏剂。因此,可以在焊接过程之后新布置导电箔片,并且芯片可以在自由空间即空穴中在中心地得到调节。
方法200可以进一步包括如在图2D的240中所示在载体204和芯片218之上沉积钝化材料224。钝化材料224可以在层202之上和/或在层202的进一步部分214之上形成。钝化材料224可以在进一步载体材料206之上形成。钝化材料224可以在面对与被附着侧面对的方向相反的方向的一侧之上,例如在芯片218的前侧之上形成。钝化材料224可以在一个或者多个接触垫222之上形成。钝化材料224可以在芯片218的一个或者多个侧壁226之上形成,其中该一个或者多个侧壁226被布置在芯片前侧和芯片后侧之间,例如,一个或者多个侧壁226可以连接芯片前侧和芯片后侧。钝化材料224可以在芯片218的一个或者多个侧壁226和进一步载体材料206的一个或者多个侧壁228之间形成。钝化材料224可以不限于具有特定厚度,而是根据各种实施例可以具有范围从大约10μm到大约20μm的厚度。钝化材料224可以包括选自以下一组材料的至少一种材料,该组材料包括:聚酰亚胺、环氧树脂、聚合物。可以利用酰亚胺处理技术例如旋涂,例如箔片层叠,例如喷射涂覆来沉积钝化材料224。酰亚胺例如聚酰亚胺处理可以包括用于封装的管芯嵌入(持续大致5秒),以增强高电压隔离。贴片工具可以通过空穴边缘而被用于高度控制。可以执行嵌入晶圆级球栅阵列(eWLB)处理,例如可以执行球阵列(BA)或者岸面栅阵列(LGA)精整。换言之,可以利用例如光敏聚酰亚胺来精整重构晶圆,并且载体204、IC芯片218和IC芯片218周围的间隙可以填充有聚酰亚胺。可替代地,可以使用可光构造的或者可激光构造的永久箔片。
方法200可以进一步包括如在240中所示选择性地移除钝化材料224的一个或者多个部分232由此从钝化材料224释放一个或者多个接触垫222。可以利用选自以下一组方法的至少一种方法选择性地移除钝化材料224的一个或者多个部分232,该组方法包括:化学蚀刻、等离子体蚀刻、激光构造、光构造。可以理解,一个或者多个部分232可以是钝化材料224的、在一个或者多个接触垫222之上例如在其上间接地或者在其上直接地形成的部分。因此,钝化材料224可以将芯片218从载体204、附着层216、层202和进一步载体材料206电绝缘。如在图7中所示,钝化材料224可以包括可以被用于间隙填充,例如填充在芯片218的一个或者多个侧壁226和进一步载体材料206的一个或者多个侧壁228之间的间隙754的聚酰亚胺。间隙754不被特别地限制为具有特定宽度或者高度,然而根据各种实施例,间隙754可以具有范围从大约30μm到大约100μm、例如50μm到大约80μm的宽度。
在曝光和显影之后,到IC芯片218的过孔和可能地到载体204的过孔可以被释放例如形成。重分布线(RDL)238、242可以例如在过孔中类似在eWLB中沉积,其中聚酰亚胺或者其它钝化材料224可以用作焊接掩模。随后,晶圆级封装例如晶圆级球栅阵列(WLB)根据设计可以设置有焊球,或者被设置为岸面栅阵列(LGA)。这在250中示出,其中可以在钝化材料224之上并且在一个或者多个接触垫222之上,例如在一个或者多个部分232中形成导电材料234。换言之,可以在被暴露的一个或者多个接触垫222之上形成导电材料234。导电材料234可以包括选自以下一组材料的至少一种材料,该组材料包括:铜、镍、铁、银、金、钯、铜合金、镍合金、铁合金、银合金、金合金、钯合金。导电材料234可以被称作重分布层和/或电互连。另外地,可以重复240和250,例如可以在钝化材料224之上形成进一步钝化材料236,可以选择性地移除进一步钝化材料236的一个或者多个部分238,并且可以在进一步钝化材料236的一个或者多个被选择性地移除的部分238中形成进一步导电材料242,其中进一步导电材料242(进一步重分布层)可以与导电材料234电连接。可以根据需要在芯片218之上形成任何数目的重分布层238、242,并且可以以为了实现必要数目的重分布层而有必要的次数一样多的次数重复过程240和250。可以在包括芯片218的整个封装之上形成最终钝化层,例如224或者236。最终钝化层用作焊接掩模。导电材料例如234或者242的一个或者多个部分244可以被暴露。导电材料的这些部分可以与一个或者多个接触垫222电连接,并且可以例如被以扇入或者扇出构形从一个或者多个接触垫222的初始位置重分布例如重定位。如在图2G中所示,根据各种实施例,重分布线238、242可以如此形成,使得至少一条重分布线238、242可以被远离芯片地向外布置,以使得接触垫222接触远离芯片的结合材料246。进而,至少一条重分布线238、242可以被向内地布置,例如以使得另一个接触垫222接触在芯片之上的结合材料246。进而,重分布线238、242可以被形成为例如在进一步接触垫222和载体204之间提供接地分布。
如在图2F中所示,结合材料246可以被添加到导电材料例如234或者242的、被暴露的一个或者多个部分244。结合材料246可以包括选自以下一组结合结构的至少一种,该组结合结构包括:焊球和焊接凸点。结合材料246可以包括焊球栅阵列。结合材料246可以包括选自以下一组材料的至少一种的焊接材料,该组材料包括:银、铅、锌、锡和/或其一种或者多种合金。
在不添加任何模具材料时,该布置可以被个体化(通过切割线248分离)以从相邻芯片封装例如270a分离每一个芯片封装270。方法200可以包括通过经过载体204、进一步载体材料206和层202分离而个体化芯片封装270。可以通过经过载体204、进一步载体材料206、钝化材料例如224例如236和层202分离例如切割而个体化芯片封装270。
根据各种实施例,芯片封装270、280可以包括:载体204;在载体204之上形成的层202;在层202之上形成的进一步载体材料206;层202的、被从进一步载体材料206释放的一个或者多个部分212;和包括一个或者多个接触垫222的芯片218,其中芯片218经由层202附着到载体204。
图3示出用于制造晶圆级封装的方法300。方法300可以包括
在载体之上形成层(在310中);
在该层之上形成进一步载体材料(在320中);
选择性地移除进一步载体材料的多个部分由此从进一步载体材料释放该层的多个部分(在330中);和
经由该层的、被从进一步载体材料释放的该多个部分将包括一个或者多个接触垫的多个芯片附着到载体;其中该多个芯片共同地被该层保持(在340中)。
方法300可以包括已经关于方法200描述的一个或者多个或者所有的特征。根据一个实施例,方法300可以包括一种用于制造晶圆级封装(例如,如在图2C中所示)的方法,该方法包括:
在载体204之上形成层202;在层202之上形成进一步载体材料206;选择性地移除进一步载体材料206的多个部分208由此从进一步载体材料206释放层202的多个部分212;经由层202的、被从进一步载体材料206释放的多个部分212将包括一个或者多个接触垫222的多个芯片218附着到载体204;其中多个芯片218共同地被层202保持。被共同地保持可以被理解为意味着该多个芯片218可以被布置在同一连续层202之上。晶圆级封装可以被理解为包括被以重构晶圆的形式保持的多个芯片。虽然在传统上重构晶圆可以包括在模具材料中嵌入的多个芯片,但是根据各种实施例的晶圆级封装可以包括不带模具材料地在载体202和/或进一步载体材料206内保持该多个芯片。换言之,根据各种实施例的芯片封装和晶圆级封装可以不像传统芯片封装那样要求模具材料。
各种实施例提供一种晶圆级封装(如在图2C中所示),该晶圆级封装包括载体204;在载体204之上形成的层202;在层202之上形成的进一步载体材料206;层202的、被从进一步载体材料206释放的多个部分212;每一个包括一个或者多个接触垫222的多个芯片218,其中多个芯片218经由层202的、被从进一步载体材料206释放的多个部分212附着到载体204;其中多个芯片218共同地被层202保持。
图4根据一个实施例示出用于制造芯片封装的方法400。方法400可以包括:
在芯片载体内形成多个空穴(在410中);
在该多个空穴中置放多个芯片,每一个芯片包括一个或者多个接触垫(在420中);
在芯片载体和该多个芯片之上沉积钝化材料(在430中);
选择性地移除钝化材料的一个或者多个部分,由此从钝化材料释放该多个芯片的一个或者多个芯片接触垫(在440中);和
在该一个或者多个芯片接触垫之上并且在该钝化材料之上形成导电材料(在450中)。
方法400可以包括:在芯片载体204、206内形成多个空穴208;在多个空穴208中置放多个芯片218,每一个芯片218包括一个或者多个接触垫222;在芯片载体204、206和多个芯片218之上沉积钝化材料224;选择性地移除钝化材料224的一个或者多个部分232,由此从钝化材料224释放多个芯片218的一个或者多个芯片接触垫222;和,在一个或者多个芯片接触垫222之上并且在钝化材料224之上形成导电材料234。
图5示出根据一个实施例的芯片封装510。芯片封装510可以包括:包括在芯片载体例如204和/或206内形成的至少一个空穴208的芯片载体例如204和/或206;包括一个或者多个接触垫222并且置放在该至少一个空穴208中的至少一个芯片218;在芯片载体例如204和/或206和至少一个芯片218之上形成的钝化材料224,其中至少一个芯片218的一个或者多个芯片接触垫222被从钝化材料224释放;和在一个或者多个芯片接触垫222之上形成的导电材料234,其中导电材料234在钝化材料224之上形成。
图6示出根据一个实施例的芯片封装610。除了芯片封装可以不包括任何结合材料246,例如焊球,例如焊接凸点等之外,芯片封装610可以包括芯片封装210、510的一个或者多个或者所有的特征。芯片封装610可以因此提供一种特殊的低成本型式,其中可以省略RDL,并且可能地,可以例如在载体204之上仅仅施加隔离剂即钝化材料224。可以特别地当尺寸是小的并且IC具有焊盘时实现芯片封装610。
载体204的选定部分648可以被用作电互连而无需在载体204的选定部分648之上形成钝化材料,例如224,例如236,和进一步重分布材料例如234,例如242。这些选定部分648可以例如包括源极触点222S。如果芯片218包括功率半导体芯片,则替代在芯片218的前侧之上形成的源极/漏极触点222S地,被附着侧例如后侧可以包括源极/漏极触点223S。可以在芯片218的前侧上形成进一步源极/漏极接触垫222D。可以在芯片218的前侧上形成栅极接触垫222G。后侧源极/漏极触点223S可以经由层202和附着层216而被电连接到载体204。因此,载体204的选定部分648可以被用作到后侧源极/漏极触点223S的直接电相互连接触点222S。这可以降低成本,因为为了形成到后侧源极/漏极触点223S的进一步结合结构互连244,例如焊球,可以不需要重分布层例如234,例如242,和钝化材料例如224,例如236。可以如根据以前的实施例描述地形成用于前侧源极/漏极触点222D和前侧栅极触点222G的重分布层例如234,例如242,和钝化材料例如224,例如236,和被电连接到前侧源极/漏极触点222D和前侧栅极触点222G的结合结构246(未在图6中示出)。可以在载体204和/或进一步载体材料206的一个或者多个侧壁之上形成钝化材料652,其中钝化材料652可以被用于增强高电压(HV)隔离。对于功率应用而言,芯片封装610可以包括低成本、相对小的eWLB芯片封装。
可以理解,根据各种实施例,每一个芯片封装例如芯片封装270,例如芯片封装510,例如芯片封装610,可以不限于包括仅仅一个芯片。例如,根据一个实施例的芯片封装可以包括半桥芯片布置。因此,在个体化例如切割之后,每一个芯片封装可以包括层202的、被从进一步载体材料206释放的多个例如两个部分212;可以例如被以半桥布置布置的多个芯片218例如两个芯片,每一个芯片218包括一个或者多个接触垫222,例如222S,例如222D,其中芯片218可以经由层202的、被从进一步载体材料206释放的部分212附着到载体204;其中芯片218共同地被层202保持。
各种实施例提供一种可靠的并且175°C兼容的、用于制造芯片封装和/或晶圆级封装的方法,即在175°C下兼容的过程。根据各种实施例的芯片封装和晶圆级封装可以呈现低热阻。各种实施例提供一种eWLB前端(FE)兼容的、用于制造芯片封装和/或晶圆级封装的方法。各种实施例提供一种用于制造芯片封装和/或晶圆级封装的方法,其中提供了一种带有高电流后侧触点的集成电路(IC)。
各种实施例提供一种用于制造芯片封装的方法,该方法包括:在载体之上形成层;在该层之上形成进一步载体材料;选择性地移除进一步载体材料的一个或者多个部分,由此从进一步载体材料释放该层的一个或者多个部分;经由该层将包括一个或者多个接触垫的芯片附着到载体。
根据一个实施例,载体包括导电薄板。
根据一个实施例的,载体包括选自以下一组材料的至少一种材料,该组材料包括:铜、镍、铁、银、金、钯、铜合金、镍合金、铁合金、银合金、金合金、钯合金。
根据一个实施例,载体包括范围从大约50μm到大约1000μm的厚度。
根据一个实施例,该层包括导电材料,该导电材料包括选自以下一组材料的至少一种材料,该组材料包括:银、银合金、金、金合金、镍、钯。
根据一个实施例,在载体之上形成层包括利用选自以下一组方法的至少一种方法在载体之上形成该层,该组方法包括:电镀、化学镀、电流沉积、层叠、箔片层叠、溅射、蒸发、化学汽相沉积、等离子体增强化学汽相沉积、印刷。
根据一个实施例,在载体之上形成层包括形成导电层,该导电层包括导电胶合剂和导电纳米膏剂中的至少一种。
根据一个实施例,在载体之上形成层包括在载体之上形成导电层并且在导电层之上形成烧结层。
根据一个实施例,在载体之上形成层包括在载体之上形成导电层和电绝缘层中的至少一个。
根据一个实施例,电绝缘层包括电绝缘粘结剂,电绝缘粘结剂包括选自以下一组材料的至少一种材料,该组材料包括:聚酰亚胺、苯并环丁烯、环氧树脂。
根据一个实施例,进一步载体材料包括范围从大约60μm到大约200μm的厚度。
根据一个实施例,进一步载体材料包括与载体相同的材料。
根据一个实施例,在该层之上形成进一步载体材料包括利用选自以下一组方法的至少一种方法在该层之上形成进一步载体材料,该组方法包括:层叠、烧结、胶接。
根据一个实施例,在载体之上形成层并且在该层之上形成进一步载体材料包括将包括该层和进一步载体材料的箔片附着到载体。
根据一个实施例,选择性地移除进一步载体材料的一个或者多个部分由此从进一步载体材料释放该层的一个或者多个部分包括选择性地蚀刻进一步载体材料的一个或者多个部分,其中该层用作蚀刻终止层。
根据一个实施例,选择性地移除进一步载体材料的一个或者多个部分由此从进一步载体材料释放该层的一个或者多个部分包括选择性地蚀刻进一步载体材料的一个或者多个部分,其中该层防止载体的蚀刻。
根据一个实施例,选择性地移除进一步载体材料的一个或者多个部分由此从进一步载体材料释放该层的一个或者多个部分包括利用选自以下一组方法的至少一种方法选择性地移除进一步载体材料的一个或者多个部分,该组方法包括:化学蚀刻、等离子体蚀刻、喷砂。
根据一个实施例,该层的、被从进一步载体材料释放的该一个或者多个部分共同地被该层的、被进一步载体材料覆盖的进一步部分结合。
根据一个实施例,经由该层将包括一个或者多个接触垫的芯片附着到载体包括经由该层的、被从进一步载体材料释放的一个或者多个部分将包括一个或者多个接触垫的芯片附着到载体。
根据一个实施例,该方法进一步包括在该层的、被从进一步载体材料释放的一个或者多个部分之上形成附着层,并且经由附着层将芯片附着到载体。
根据一个实施例,附着层包括导电材料,该导电材料包括选自以下一组材料的至少一种材料,该组材料包括:导电胶合剂、导电粘结剂、导电聚合物、导电有机聚合物、导电环氧树脂。
根据一个实施例,附着层包括电绝缘材料,该电绝缘材料包括选自以下一组材料的至少一种材料,该组材料包括:聚合物、有机聚合物、环氧树脂。
根据一个实施例,附着层包括导电胶合剂和导电纳米膏剂中的至少一种。
根据一个实施例,附着层包括范围从大约3μm到大约70μm的厚度。
根据一个实施例,该方法进一步包括在载体和芯片之上沉积钝化材料;和,选择性地移除钝化材料的一个或者多个部分由此从钝化材料释放该一个或者多个接触垫。
根据一个实施例,该方法进一步包括在该层之上沉积钝化材料。
根据一个实施例,该方法进一步包括在钝化材料之上并且在该一个或者多个接触垫之上形成导电材料。
根据一个实施例,该方法进一步包括通过经过载体、进一步载体材料和该层分离而个体化芯片封装。
根据一个实施例,在载体之上形成层包括在载体之上形成电绝缘层;并且该方法进一步包括选择性地移除载体和进一步载体材料中的至少一个的一个或者多个部分,其中载体和进一步载体材料中的至少一个包括导电重分布层。
各种实施例提供一种芯片封装,该芯片封装包括:载体;在载体之上形成的层;在该层之上形成的进一步载体材料;该层的、被从进一步载体材料释放的一个或者多个部分;包括一个或者多个接触垫的芯片,其中芯片经由该层附着到载体。
各种实施例提供一种用于制造晶圆级封装的方法,该方法包括在载体之上形成层;在该层之上形成进一步载体材料;选择性地移除进一步载体材料的多个部分由此从进一步载体材料释放该层的多个部分;经由该层的、被从进一步载体材料释放的该多个部分将包括一个或者多个接触垫的多个芯片附着到载体;其中该多个芯片共同地被该层保持。
各种实施例提供一种晶圆级封装,该晶圆级封装包括载体;在载体之上形成的层;在该层之上形成的进一步载体材料;该层的、被从进一步载体材料释放的多个部分;每一个包括一个或者多个接触垫的多个芯片,其中该多个芯片经由该层的、被从进一步载体材料释放的该多个部分附着到载体;其中该多个芯片共同地被该层保持。
虽然已经特别地参考具体实施例示出并且描述了本发明,但是本领域技术人员应该理解,在不偏离如由所附权利要求限定的本发明的精神和范围的情况下,可以在其中作出在形式和细节方面的各种改变。本发明的范围因此由所附权利要求指示并且因此旨在涵盖落入权利要求的等价性的含义和范围内的所有的改变。
Claims (32)
1.一种用于制造芯片封装的方法,所述方法包括
在载体之上形成层;
在所述层之上形成进一步载体材料;
选择性地移除所述进一步载体材料的一个或者多个部分,由此从所述进一步载体材料释放所述层的一个或者多个部分;
经由所述层将包括一个或者多个接触垫的芯片附着到所述载体。
2.根据权利要求1所述的方法,
其中所述载体包括导电薄板。
3.根据权利要求1所述的方法,
其中所述载体包括选自以下一组材料的至少一种材料,所述一组材料包括:铜、镍、铁、银、金、钯、铜合金、镍合金、铁合金、银合金、金合金、钯合金。
4.根据权利要求1所述的方法,
其中所述载体包括范围从大约50μm到大约1000μm的厚度。
5.根据权利要求1所述的方法,
其中所述层包括导电材料,所述导电材料包括选自以下一组材料的至少一种材料,所述一组材料包括:银、银合金、金、金合金、镍、钯。
6.根据权利要求1所述的方法,
其中在所述载体之上形成层包括利用选自以下一组方法的至少一种方法在所述载体之上形成所述层,所述一组方法包括:电镀、化学镀、电流沉积、层叠、箔片层叠、溅射、蒸发、化学汽相沉积、等离子体增强化学汽相沉积、印刷。
7.根据权利要求1所述的方法,
其中在所述载体之上形成层包括
形成导电层,所述导电层包括导电胶合剂和导电纳米膏剂中的至少一种。
8.根据权利要求1所述的方法,
其中在所述载体之上形成层包括
在所述载体之上形成导电层并且在所述导电层之上形成烧结层。
9.根据权利要求1所述的方法,
其中在所述载体之上形成层包括
在所述载体之上形成导电层和电绝缘层中的至少一个。
10.根据权利要求9所述的方法,
其中所述电绝缘层包括电绝缘粘结剂,所述电绝缘粘结剂包括选自以下一组材料的至少一种材料,所述一组材料包括:聚酰亚胺、苯并环丁烯、环氧树脂。
11.根据权利要求1所述的方法,
其中所述进一步载体材料包括范围从大约60μm到大约200μm的厚度。
12.根据权利要求1所述的方法,
其中所述进一步载体材料包括与所述载体相同的材料。
13.根据权利要求1所述的方法,
其中在所述层之上形成进一步载体材料包括利用选自以下一组方法的至少一种方法在所述层之上形成进一步载体材料,所述一组方法包括:层叠、烧结、胶接。
14.根据权利要求1所述的方法,
其中在载体之上形成层并且在所述层之上形成进一步载体材料包括
将包括所述层和进一步载体材料的箔片附着到所述载体。
15.根据权利要求1所述的方法,
其中选择性地移除所述进一步载体材料的一个或者多个部分由此从所述进一步载体材料释放所述层的一个或者多个部分包括选择性地蚀刻所述进一步载体材料的一个或者多个部分,其中所述层用作蚀刻终止层。
16.根据权利要求1所述的方法,
其中选择性地移除所述进一步载体材料的一个或者多个部分由此从所述进一步载体材料释放所述层的一个或者多个部分包括选择性地蚀刻所述进一步载体材料的一个或者多个部分,其中所述层防止所述载体的蚀刻。
17.根据权利要求1所述的方法,
其中选择性地移除所述进一步载体材料的一个或者多个部分由此从所述进一步载体材料释放所述层的一个或者多个部分包括利用选自以下一组方法的至少一种方法选择性地移除所述进一步载体材料的一个或者多个部分,所述一组方法包括:化学蚀刻、等离子体蚀刻、喷砂。
18.根据权利要求1所述的方法,
其中所述层的、被从所述进一步载体材料释放的所述一个或者多个部分共同地被所述层的、被所述进一步载体材料覆盖的进一步部分结合。
19.根据权利要求1所述的方法,
其中经由所述层将包括一个或者多个接触垫的芯片附着到所述载体包括
经由所述层的、被从所述进一步载体材料释放的一个或者多个部分将包括一个或者多个接触垫的所述芯片附着到所述载体。
20.根据权利要求1所述的方法,进一步包括
在所述层的、被从所述进一步载体材料释放的所述一个或者多个部分之上形成附着层,并且经由所述附着层将所述芯片附着到所述载体。
21.根据权利要求18所述的方法,
其中所述附着层包括导电材料,所述导电材料包括选自以下一组材料的至少一种材料,所述一组材料包括:导电胶合剂、导电粘结剂、导电聚合物、导电有机聚合物、导电环氧树脂。
22.根据权利要求18所述的方法,
其中所述附着层包括电绝缘材料,所述电绝缘材料包括选自以下一组材料的至少一种材料,所述一组材料包括:聚合物、有机聚合物、环氧树脂。
23.根据权利要求18所述的方法,
其中所述附着层包括导电胶合剂和导电纳米膏剂中的至少一种。
24.根据权利要求18所述的方法,
其中所述附着层包括范围从大约3μm到大约70μm的厚度。
25.根据权利要求1所述的方法,进一步包括
在所述载体和所述芯片之上沉积钝化材料;和
选择性地移除所述钝化材料的一个或者多个部分由此从所述钝化材料释放所述一个或者多个接触垫。
26.根据权利要求25所述的方法,进一步包括
在所述层之上沉积钝化材料。
27.根据权利要求26所述的方法,进一步包括
在所述钝化材料之上并且在所述一个或者多个接触垫之上形成导电材料。
28.根据权利要求1所述的方法,进一步包括
通过经过所述载体、所述进一步载体材料和所述层分离而个体化芯片封装。
29.根据权利要求1所述的方法,
其中在所述载体之上形成层包括在所述载体之上形成电绝缘层;并且
所述方法进一步包括选择性地移除所述载体和所述进一步载体材料中的至少一个的一个或者多个部分,其中所述载体和所述进一步载体材料中的至少一个包括导电重分布层。
30.一种芯片封装,包括:
载体;
在所述载体之上形成的层;
在所述层之上形成的进一步载体材料;
所述层的、被从所述进一步载体材料释放的一个或者多个部分;
包括一个或者多个接触垫的芯片,其中所述芯片经由所述层附着到所述载体。
31.一种用于制造晶圆级封装的方法,所述方法包括:
在载体之上形成层;
在所述层之上形成进一步载体材料;
选择性地移除所述进一步载体材料的多个部分由此从所述进一步载体材料释放所述层的多个部分;
经由所述层的、被从所述进一步载体材料释放的所述多个部分将包括一个或者多个接触垫的多个芯片附着到所述载体;
其中所述多个芯片共同地被所述层保持。
32.一种晶圆级封装,包括:
载体;
在所述载体之上形成的层;
在所述层之上形成的进一步载体材料;
所述层的、被从所述进一步载体材料释放的多个部分;
每一个包括一个或者多个接触垫的多个芯片,其中所述多个芯片经由所述层的、被从所述进一步载体材料释放的所述多个部分附着到所述载体;
其中所述多个芯片共同地被所述层保持。
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US10522447B2 (en) | 2019-12-31 |
US20160190044A1 (en) | 2016-06-30 |
US20130334712A1 (en) | 2013-12-19 |
CN103515256B (zh) | 2017-04-26 |
US9917036B2 (en) | 2018-03-13 |
US9111847B2 (en) | 2015-08-18 |
US20180158759A1 (en) | 2018-06-07 |
DE102013106271A1 (de) | 2013-12-19 |
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