WO2017102230A1 - Insulated die - Google Patents

Insulated die Download PDF

Info

Publication number
WO2017102230A1
WO2017102230A1 PCT/EP2016/077915 EP2016077915W WO2017102230A1 WO 2017102230 A1 WO2017102230 A1 WO 2017102230A1 EP 2016077915 W EP2016077915 W EP 2016077915W WO 2017102230 A1 WO2017102230 A1 WO 2017102230A1
Authority
WO
WIPO (PCT)
Prior art keywords
chip
insulated
package
electrically insulating
insulating layer
Prior art date
Application number
PCT/EP2016/077915
Other languages
French (fr)
Inventor
Jürgen Högerl
Horst Theuss
Gottfried Beer
Original Assignee
Infineon Technologies Ag
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Infineon Technologies Ag filed Critical Infineon Technologies Ag
Publication of WO2017102230A1 publication Critical patent/WO2017102230A1/en

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • H01L23/3128—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation the substrate having spherical bumps for external connection
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/561—Batch processing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/29—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the material, e.g. carbon
    • H01L23/293—Organic, e.g. plastic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3114—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed the device being a chip scale package, e.g. CSP
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3135—Double encapsulation or coating and encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3157—Partial encapsulation or coating
    • H01L23/3171—Partial encapsulation or coating the coating being directly applied to the semiconductor body, e.g. passivation layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3157—Partial encapsulation or coating
    • H01L23/3185—Partial encapsulation or coating the coating covering also the sidewalls of the semiconductor body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49503—Lead-frames or other flat leads characterised by the die pad
    • H01L23/49513—Lead-frames or other flat leads characterised by the die pad having bonding material between chip and die pad
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49541—Geometry of the lead-frame
    • H01L23/49548—Cross section geometry
    • H01L23/49551—Cross section geometry characterised by bent parts
    • H01L23/49555—Cross section geometry characterised by bent parts the bent parts being the outer leads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5389—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates the chips being integrally enclosed by the interconnect and support structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L24/19—Manufacturing methods of high density interconnect preforms
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L24/20—Structure, shape, material or disposition of high density interconnect preforms
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/96—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being encapsulated in a common layer, e.g. neo-wafer or pseudo-wafer, said common layer being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/568—Temporary substrate used as encapsulation process aid
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04042—Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04105—Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
    • H01L2224/241—Disposition
    • H01L2224/24135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/24137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/48137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/48145—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73267—Layer and HDI connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/82—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI]
    • H01L2224/82009—Pre-treatment of the connector or the bonding area
    • H01L2224/8203—Reshaping, e.g. forming vias
    • H01L2224/82035—Reshaping, e.g. forming vias by heating means
    • H01L2224/82039—Reshaping, e.g. forming vias by heating means using a laser
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
    • H01L2224/9222—Sequential connecting processes
    • H01L2224/92242—Sequential connecting processes the first connecting process involving a layer connector
    • H01L2224/92244—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a build-up interconnect
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06506—Wire or wire-like electrical connections between devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/0651—Wire or wire-like electrical connections from device to substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49503—Lead-frames or other flat leads characterised by the die pad
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0655—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00 the devices being arranged next to each other
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0657—Stacked arrangements of devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/102—Material of the semiconductor or solid state bodies
    • H01L2924/1025—Semiconducting materials
    • H01L2924/10251—Elemental semiconductors, i.e. Group IV
    • H01L2924/10252—Germanium [Ge]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/102—Material of the semiconductor or solid state bodies
    • H01L2924/1025—Semiconducting materials
    • H01L2924/10251—Elemental semiconductors, i.e. Group IV
    • H01L2924/10253—Silicon [Si]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/102—Material of the semiconductor or solid state bodies
    • H01L2924/1025—Semiconducting materials
    • H01L2924/1026—Compound semiconductors
    • H01L2924/1027—IV
    • H01L2924/10272—Silicon Carbide [SiC]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/102—Material of the semiconductor or solid state bodies
    • H01L2924/1025—Semiconducting materials
    • H01L2924/1026—Compound semiconductors
    • H01L2924/1032—III-V
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/102—Material of the semiconductor or solid state bodies
    • H01L2924/1025—Semiconducting materials
    • H01L2924/1026—Compound semiconductors
    • H01L2924/1032—III-V
    • H01L2924/1033—Gallium nitride [GaN]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H01L2924/141—Analog devices
    • H01L2924/142—HF devices
    • H01L2924/1421—RF devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H01L2924/143—Digital devices
    • H01L2924/1431—Logic devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/146—Mixed devices
    • H01L2924/1461—MEMS
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/35—Mechanical effects
    • H01L2924/351—Thermal stress
    • H01L2924/3511—Warping

Definitions

  • Pa c kages may oe denoted as encapsulated electronic chips with electrical connects extending out of the encapsalant and being mounted to an electronic periphery, for instance on a. chip, carrier such as a printed circuit board.
  • electronic power packages for instance half bridge circuits or current. sensors, may comprise semiconductor chips which need to be mounted in an electrically insulated manner fin particular with regard to neighbored traces, other chips or other electric potentials in the environmen 5 ⁇
  • semiconductor chips are mounted on a mounting base via non-conductive glue body to provide an insulation of at least one metal pad on the semiconductor chip.
  • a bulk encapsulant may contribute to the electric insulation.
  • an electrically insulated, chip which comprises a semiconductor chip (for instance a naked, urepackaged die singulated direccly from a semiconductor wafer.) comprising at least one chip pad (for instance a metallic chip pad) and an electrically insulating layer surrounding sin particular covering, more particularly covering in direct contact with semiconductor material of the semiconductor chip) at least part (in particular at least 60%, more particularly at least 901, of an external surface) of the semiconduc or chip.
  • a semiconductor chip for instance a naked, urepackaged die singulated direccly from a semiconductor wafer.
  • chip pad for instance a metallic chip pad
  • an electrically insulating layer surrounding sin particular covering more particularly covering in direct contact with semiconductor material of the semiconductor chip
  • at least part in particular at least 60%, more particularly at least 901, of an external surface
  • a method of manufacturing an insulated chip comprises providing a semiconductor chip comprising at least one chip pad, and surrounding (in particular coating, more particularly conformally coating) at least part of the semiconductor chip (in particular including side surfaces of the semiconductor chip; with an electrically insulating layer .
  • a packa e is provided which comprises an insulated chip having the above-mentioned features, and an encapsulant encapsulating at least part of the insulated chip (in particular covering at least part of the electrically insulating layer) .
  • a method of: manufacturing a package comprises manufacturing an. insulated chip by a method having the above-mentioned features, and encapsulating at least part of the insulated chip by an encapsulant.
  • a packaqe which comprises an insuiaoed chip having the above-mentioned features, a further semiconduc or chip (which may be configured as an insulated chip having the above- mentioned features, or as a packaged or non-packaged chip without electrically insulating layer), and at least one bond wire electrically connecting the insulated chip with the fu r the r s em i c onduc to r chip.
  • An exemplary embodiment has the advantage that a thin dielectric layer (rather than a bulk material) is applied onto the entire surface or at least onto a significant portion of the surface of the unpackaged semiconductor chip- to provide for a very compact and reliable dielectric isolation within an encapsulation.
  • a dielectric shell directly contacting or covering the exterior semiconductor surface of the semiconductor chip, there is a high freedom to select the material of the electrically insulating layer for the purpose of a reliable electric insulation for suppressing creep current and increasing disruptive strength.
  • a procedure of conformaliy applying this electrically insulating layer is precisely controllable and is compatible with a batch processing on wafer level.
  • Phis architecture of electrically isolating a naked die also allows to provide for a reliable isolation of sidewalls and/or an active chip side of the semiconductor ch p, thereby providing an efficient protection against undesired creep currents and voltage induced degradation along an interface 5 between semiconductor chip and encapsulation (in particular in the event of delamination at this interface) .
  • Such parasitic phenomena which are conventionally promoted by moisture, can be efficiently suppressed by the electrically insulating layer encasing the semiconductor chip,
  • a procedure of exposing one or more pads of the insulated chip for externally contacting the insulated chip by removing selected portions of material of the electrically insulating layer on the pad(s) can be accomplished simultaneously with the procedure of forming an
  • the insulated chip and a corresponding package can be manufactured by a robust and efficient, manufacturing process
  • semiconductor chip may particularly denote a naked die, i.e. a non-packaged (for instance non-molded) chip made of a processed semiconductor, for instance a. singulated piece of a semiconductor wafer.
  • One or more integrated circuit elements such as a diode, a transistor, etc.; may be formed within the semiconductor chi .
  • rr.e term "pad” may particularly denote an electrically conductive contact: or terminal formed on a surface of the naked die which allows to electrically contact the one or more i n:eg r a eci c 1 rcu 1 r e 1.eme n 1s of the som 1 conda.cior chip,
  • a supply sicptal, a control signal or a data signal may be conducted from an electronic periphery into an interior of the package and into the semiconductor chip via the one or more pads.
  • a supply signal, a cone ro: signal or a data signal may he conducted from the semiconductor chip to the electronic periphery via the one or more pacis
  • the pads may be embodied as metallic islands on the die.
  • the term "electrically insulating layer” may particularly denote a thin, film or a coating of a dielectric material covering a surface of the semiconductor chip ufor example at least partially in direct contact with semiconductor material) and safely disabling any flow of electricity between an electronic periphery and the semiconductor chip through the electrically insulating layer.
  • the thickness of such a layer may be in a range between 1 pro, and 100 pro, in particular in a range between 5 pm and 50 pm. When the thickness falls significantly below? 1 pm, electrical insula ion and fluid tightness of the layer may become too low. It lne thickness significantly exceeds 100 urn, costs may become coo high, and limitations in terms of heat removal capability may occur.
  • the term "package" or module may particularly denote one or more semi concluc t or chips, opr. i orally comprising core or more:: other kind of electronic components in addition, embedded within an encapsulant such as a meld or a laminate.
  • an entire s rrounding surface of the semi conductor chip and the at least one D d is covered with the electrically insulating layer.
  • a surrounding surface of the semiconductor chip excluding only at least one surface portion around the at least one pad is covered with the electrically insulating layer. While sidewalls and a portion of the surface of the naked die may be completely protected against electricity in this embodiment, direct access to the chip pads is nevertheless enabled (for instance to couple' the pads with bond wires) ,
  • a substantially cuboid semiconductor chip is covered with the electrically insulating layer, and a sixth substantially rectangular surface of the semiconductor chip is free of the electrically insulating layer.
  • Such an insulated chip may be implemented advantageously in a chip encapsulating architecture based on an inverse cavity plating concept, tor Instance as described referring to Figure 15 to Figure 26.
  • the sixth rect ngular surface may be bonded on a mounting base such as a. Leadframe and/or may serve to provide for an elect ically conductive connection.
  • the electrically insulating layer is made of a polymer material, in particular parylene.
  • Other polymer materials which may be implemented are polyimide or polvaraid .
  • Paryiene which is a pr e fe r r ed marerfai in exemplary embodiments, denotes a variety of chemical vapor deposited pol ( -xylyiene ) polymers which may function as highly efficient moisture and dielectric barriers.
  • Xylyiene comprises two isomeric organic compounds with the formula CtHbCh ' : . Paryiene is particularly appropriate due to its combination of barrier properties and its capability to be processed. Paryiene may be enriched with one or more additives to precise] y adjust 'die desired materia] properties.
  • Polymer materials in particular paryiene, may combine an excellent electric isolation with a capability of reliably filling and flowing into even very narrow gaps during deposition, thereby ensuring also a sealing task concerning moisture.
  • su::h materials can be precisely ana rapidly removed by laser processing. It is possible to conformably deposit these material with homogeneous thickness from e gas phase.
  • the mentioned materials, in particular paryiene provide a pronounced protection against corrosion.
  • the electrically insulating layer is made of a material being removable by laser drilling to provide a defined and reproducible shape and. dimension.
  • via formation by laser patterning on the one hand and exposing one or more chip pads of the insulated chip on the other hand may be carried out by a single combined easer processing procedure, and hence very efficiently.
  • the semiconductor chip is a power semiconductor chip.
  • Such power semiconductor chips are specifically prone to failure in the event of creep currents or drsruptive discharge which may occur under high voltage or high current conditions.
  • Power semiconductor chips may be used for automotive applications.
  • Power semiconductor chips may comprise, as integrated circuit elements, power transistors and/or diodes.
  • the process of surrounding or coating comprises mounting the semiconductor chip on an auxiliary carrier, and depositing a first part of the electrically irsuiatina material on an exposed part of the surface o f the mounted semiconductor chip.
  • an auxiliary carrier may be a late or foil on. which one or a plurality of semiconductor chips to be coated may be arranged. After the coating procedure, the semi. conductor ehip(s) may be detached from the auxiliary carrier for further processing.
  • the surrounding ⁇ or coating) further ⁇ comprises mounting a surface portion of the semiconductor chip covered with the deposited electrically insulating material on a further auxiliary carrier, then removing the auxiliary carrier, and subsequently depositing a second part of the electrically insulating material on an exposed part of the surface of the mounted semiconductor chip which has been covered by the auxiliary carrier during depositing the first part of the electrically insulating material.
  • a remounting concept it is possible to detach the semiconductor chip(s) from the auxiliary carrier and to attach another (previously exposed) surface of the semiconductor chip is) onto the further auxiliary carrier before a subsequent coating procedure.
  • the manuf cturing method is car ied out simultaneously with a plurality of semiconductor chips.
  • a batch procedure allows for a very efficient processing
  • the e J octr ically insulating layer is deposited from a gas phase, in particular by Chemical Vapor Deposition (CVDj .
  • CVDj Chemical Vapor Deposition
  • This procedure allows to obtain a reliably uriinterr u ⁇ t ed homogeneoas 1 y ':.
  • r 1 c k elect r 1 ca 11 y i n su1 a t i nq layer.
  • PVD Physical Vapor Deposition
  • PECVDj Plasma Enhanced Physical Vapor Deposition
  • the package comprises at least one electrically conductive via.
  • Each via may extend through a respective common access hole extending through both the encapsulate and the electrically insulating layer.
  • a single via or other vertical interconnect element it is possible to electrically penetrate both encapsulant and electrical i y conductive layer for getting access to the one or more chop cads.
  • the encapsulant comp ises a laminate, in particular a printed circuit board laminate.
  • laminate structure may particularly denote an integral flat member formed by electrically conductive structures and/or electrically insulating structures which may oe connected to one another by applying a pressing force. The connection by pressing may be optionally accompanied by the supply of thermal energy. Lamination may hence be denoted as the technique of manufacturing a composite material in multiple layers.
  • a laminate can be permanently assembled by heat and/or pressure and/or welding and/or adhesives.
  • the encapsulant comprises a mold, in particular a plastic moid, tor instance, a correspondingly encapsulated chip may be provided by placing the insulated chip (if desired together with other components, such as a leadframe) between an upper mold die and a lower moid die and to inject liquid mold material therein. After solidification of the mold material, the package formed by the encapsulant with the insulated chip in between is completed.
  • a mold in particular a plastic moid, tor instance
  • a correspondingly encapsulated chip may be provided by placing the insulated chip (if desired together with other components, such as a leadframe) between an upper mold die and a lower moid die and to inject liquid mold material therein. After solidification of the mold material, the package formed by the encapsulant with the insulated chip in between is completed.
  • the encapsulant comprises a mounting base on which a bottom of "he insulated chip is mounted and comprises a cover covering a top of the insulated chip.
  • the mounting base may comprise an electrically conductive material (such as a metal sheet ⁇ and the cover may comprise a recessed or continuous electrically insulating material,
  • a corresponding package or module may oo denotes as BLADE package or module (compare Figure 12 or Pi pure 13 ; .
  • the cover comprises a lateral surrounding structure, in particular made of electrically conductive material, delimit ng a cavity in which the insulated chip is embedded, in particular vertical in flush with the insulated chip.
  • the lateral su rounding structure may be an annular body surrounding and accommodating the insulated. chip.
  • the lateral surrounding structure may be made of the same material as the mounting base and may be created after having mounted the insulated chip on the mounting base.
  • the cover comprises at least one top layer covering a top surface of the insulated chip.
  • encapsulation of the insulated chip, to which also the lateral surrounding structure contributes may be completed by covering the insulated chip and the lateral surrounding structure by one or more planar layers, for instance connectaoie by lamination.
  • the at least. one top layer additionally covers a top surface of the lateral surrounding structure.
  • the connection procedure may be accomplis ed by lamination ⁇ i.e. by applying heat and pressure) .
  • the at leas': one top layer comprises a lower electrically insulating top layer directly covering the top surface of the insulated chip and being penetrated by at least one vertical interconnect structure providing for an electric: connection with the at least one chip pad.
  • the lower electrically insulating top Layer may ensure chat the various chip pads remain electrically decoupled from one another.
  • vertical interconnect structures such as viae can be formed.
  • laser drilling for forming access holes as a basis for the vertical inte connect structures on the one hand and laser drilling fox exposing one or more chip pads of the insulated chip on the other hand may be carried out by a simple and single combined and simultaneous procedure.
  • the at least one top layer comprises an upper electrically conductive top layer directly covering the lower a er and being connected to the at. least one vertical interconnect structure.
  • the electrically conductive layer pfor instance a copper foil) may be directly connected with the one or more vertical interconnect structures.
  • a surface of the insulated chip being directly arranged on the mounting base is free of the electrically insulating layer and/or is electrically coupled to the mounting base. For instance, it may be connected and electro early coupled by soldering to the mounting base, for instance a leadframe.
  • the lateral surrounding structure is made of an electricall conductive material and is laterally 5 ⁇ r rounded by an electrically msul. a. tire annular se ucr ure, in particular an electrically insulating annular structure being in flush (i.e. vertically aligned) with the lateral surrounding structure.
  • the arrangement of insulated chip, latere: 3 y surroundina structure arid nounrirrs base may be arranged, in turn, in a cavity defined icy a central recess of the annular structure.
  • the package comprises a counter s'uucuue on a main surface of the mounring base opposing a farther main surface of the mounting base on which the lateral surrounding structure is arranged.
  • the counter structure and the laterally surrounding structure may b pi formed in a common procedure and/or from the same materia), for instance may be plated g a I varni ca 11 y on opposing main surfaces of the mounting base.
  • the provision of the counter structure provides for a more symmetric arrangement in the vertical direction, thereby suppressing bending and warpage of the package.
  • the package comprises at least one bottom layer constituting a main surface of the package opposing a further main surface of the package constituted by the 3t least one top layer.
  • Tire at least one bottom layer (tor instance an electrically insulating bottom layer and an electrically conductive bottom layer) may be connected to the package during the same lamination procedure in which the at least one top .Layer is connected.
  • the provision of the at least one bottom layer provides for a more symmetric arrangement in the vertical direction, thereby suppressing bending and warpage of the package.
  • the electrically insulating layer is arranged for electrically insulating the semiconductor chip from at least one further semiconductor chip of the package and/or electrically conductive traces of the package and/or electrically conductive contacts of the package. FCy taking this measure, it may be dispensable to ensure that the further semiconductor e)iip(s), the electrically conductive trace -s) and/or the contact !s) are itself reliably insulated from the insulated chip, because tors function is acoomypl I seed by trie electrically insulating layer.
  • the package further comprise: 7 ; a chip carrier, in particular a leadframe, carrying the insulated chip, and at least one bond guer electrically connecting the at least one chip pad with the chip carrier.
  • a chip carrier in particular a leadframe, carrying the insulated chip, and at least one bond guer electrically connecting the at least one chip pad with the chip carrier.
  • the package is configured as one of the group consisting of a current sensor (in particular a current sensor based on. magnetic sensing), a half bridge, a cascade circuit, a circuit constituted by a field effect transistor and a bipolar transistor being connected in parallel to one another, and a power semiconductor circuit.
  • a current sensor in particular a current sensor based on. magnetic sensing
  • a half bridge in particular a current sensor based on. magnetic sensing
  • a cascade circuit a circuit constituted by a field effect transistor and a bipolar transistor being connected in parallel to one another
  • a power semiconductor circuit for example, a power semiconductor circuit.
  • other high current and/or high voltage and/or high power applications are compatible with the architecture of an insulated chip according to an exemplary embodiment of the inven ion.
  • the method further comprises forming at least one common access hole extending through, both the encapsu ant and the electrically insulating layer in a single common procedure to thereby expose the at least one chip pad.
  • a single hole formation procedure is sufficient to obtain access to the chip pads of the semiconductor chip being insulated by the (even hermetically closed;- electrically insulating layer and a surrounding (for instance also electrically insulating) encapsu 1 a i: i on .
  • true access hole formation proceed re may simulta eously form a hole in the ;fcr instance hermetically sealed) electrically insulating layer and the encapsulant .
  • the forming of the at least one common access hole comprises at least one of the group consisting of laser ablation, plasma processing, and chemica 1 I y rocessing.
  • the method comprises mounting the insulated chip on a mounting base, in particular on a planar mounting base (rather than being inserted into a cavity during mounting) . This simplifies the mounting procedure, in particular in comparison to a scenario in which the insulated chip would have to be inserted into a recess or a cavity.
  • the method comprises, after the mounting, forming a lateral surrounding structure, in particular made of the same material as the mounting base, delimiting a cavity in which the already mounted insulated chip is embedded, in particular vertical in flush with the insulated chip.
  • surrounding the insulated chip may be formed only after the mounting procedure, i.e. by an additive rather than by a subtract ive procedure. This simplrfi.es processing and increases reliability of the manufactured package.
  • forming the lateral surrounding strueto.: re on the mounting base is accomplished by an additive procedure (for instance by material deposition), in
  • the mounting base is made of copper, for instance is a copper leadframe
  • galvanic deposition of material on this basis is enabled and is carried out for forming the laterally surrounding structure. This is a simple and very reliable procedure which does not harm the insulated chip. Its insulating layer protects the semiconductor chip in an. interior of the insulated chip c .;ring such a galvanic plating procedure from irne action with chemicals.
  • the method further comprises inserting the lateral surrccnding structure and che insulated chip on the mounting base into a laterally surrounding annular structure (which may be made of electrically insulating material;, in particular an annular structure being in flush wich the lateral surrounding structure and the insulated chip.
  • a laterally surrounding annular structure which may be made of electrically insulating material;, in particular an annular structure being in flush wich the lateral surrounding structure and the insulated chip.
  • the method further comprises
  • che method further comprises forming the at least one top layer with an electrically insulating too layer directly covering the top surface of the insulated chip, and forming at least one vertical interconnect
  • the insulating top layer rn. combination with the one or more vertical interconnect structures may hence fulfill two functions, i.e. encapsulating the insulated chip and defining one on more eleetric paths of signals
  • interconnect structure comprises forming, in. particular by laser drilling, at; least one common access hole extending through both the elec ric lly insulating nop layer and trie electrically insulating layer in a common procedure to thereby expose the at least one chip pad, and filling too at least one common access hole with electrically conductive materiel.
  • the method comprises manufacturing a plurality of packages at least partially in a batch procedure as a consecutive/a connected/an integral structure being subsequently singularized into the individual packages or preforms thereof.
  • the procedures of forming the insulated chip, of moun ing the insulated chip on rhe mounting base, and of forming the lateral ly surrounding structure may be performed efficiently for multiple packages in common or even on wafer level. After those procedures, the semifinished packages or preforms of packages may be
  • the individualized elements may be inserted into an integral structure comprising multiple annular surrounding structures, Subsequently, layer formation and lamination as well as access hole formation and material deposition for formation of the vertical interconnect structures may be again carried out as a batch.
  • the method further comprises filling, in particular at least partially gaivauicaily, the at least one common access hole with electrically conductive material, in particular copper.
  • the method further comprises forming at least one electrically conductive' layer structure on the encapsulant and electrically coupled to the electrically conductive material.
  • Such an electrically conductive layer may be attached by lamination or may be deposited by a deposition procedure (such as sputtering) .
  • the package comprises a mounting base on which both the insulated chip and the further semiconductor chip are mounted separately from one another ⁇ in particular juxtaposed to one another with a gap in between on the mounting base) .
  • insulated chip and further semiconductor chip may be connected to one another in a side-by-side archi ecture, for example electrically connected by one or more bond wires.
  • the insulated chip and the further semiconductor chip are mounted on one another (i.e. may be vertically stacked on top of each other) .
  • insulated chip and further semiconductor chip may be connected to one another in a chip-on-chip architecture, for example electrically connected via one or more bond wires.
  • the one or more electronic chips may be semiconductor chips, in particular dies.
  • the at least one electronic chip is configured as a power semiconductor chip, in particular comprising at least one of the group consisting of a diode, and a transistor, more particularly an insulated gate bipolar transistor.
  • the device is configured as a power module.
  • the one or more electronic chips may be used as semiconductor chips for power applications for instance in the automotive field,
  • at least one electronic chip may comprise a logic IC or an electronic chip for RF power applications.
  • the electronic chip(s) may be used as one or more sensors or actuators in microelectrontechanical systems (MiMO; , for example as pressure sensors or acceleration sens o r3.
  • MiMO microelectrontechanical systems
  • a semiconductor substrate preferably a silicon substrate
  • a silicon oxide or another insulator substrate may be provided.
  • I is also possible to implement a germanium substrate or a II I-V-semiconductor material.
  • exemplary embodiments may be implemented in GaN or SIC tecnnoiociy.
  • Figure 1 shows a cross-sectional view of an insulated chip being hermetically sealed, mechanically and. electrically, by a direct coating of semiconductor and metallic surface material of the chip with an electrically insulating layer according to an exemplary embodiment.
  • Figure 2 shows a cross-sectional view of an insulated chip with exposed pads, wherein all semiconductor surfaces of the chip are hermetically surrounded by an electrically insulating layer exposing only the pads according to an exeiop ; a r y ernbod imen t .
  • Figure 3 shows a cross-sectional view oi a semifinished pac kage with s emi conducto r chips mounted s iolo-by-s ide according to an exemplary embodiment before encapsula t i on .
  • Figure 4 shows a cross-sectional view of a s emi f i ni shed package with semi co nduc t or chips mounted in a chip-on-chip arnnbteceure according to another exemplary embodiment before
  • Figure 5 to Figure 3 show structures obtained during carrying out a method of manufacturing a plurality of insulated chips in a batch architecture according to another eae:a ⁇ 1a r y erobodiiten i .
  • Figure 10 shows a. semifinished package acce raiinp to an exemplary embodiment before exposing chip pads by removing material of an encapsulant and of a hermetically sealing e l ec t i ca l l y insulating layer in a common procedure.
  • Figure 11 shows the semifinished package of Figure 1.0 alter exposing chi pads by removing material of the encapsu ; ant. and of the electrically insulating layer in a common laser ablation procedure.
  • Figure 12 shows a cross-sectional view of a package according to an exemplary embodiment obtained by the manufacturing method according to.
  • Figure 13 shows a cross-sec a ions 1 view of a package providing a half bridge function according to an exemplary embodiment of the invention.
  • Figure 14 shows a cross-sectional view of a package according to yet another exemplary embodiment of the in ent. ion .
  • Figure 15 to Figure 26 show* structures obtained during carrying out a method of manufacturing a plurairty of packages in a batch architecture according to another exemp 1. a r y embodiment .
  • an isolated chip ⁇ for instance covered with a pa ry Lose layer or any other ap ropri t ⁇ dielect ic fairs/ may be implemented in a package or modmi ' V ⁇ such as a BLADE housing, i.e. laminated in a circuit board ⁇ .
  • the insulation layer and thereby rhe chip pads are opened only during opening of an upper passage layer ar ercapsuiaip (for instance by a laser procedure; .
  • the completed package then comprises a circunnorentiaily fully isolated or hermetically insulated chip, with the only exception of the contact pad(s) .
  • Such an architect re allows for a defined and reliable insulation of chip and chip surfaces. This also protects the package from unciesired creep currents and voltage induced degradation along the interface chip-encapsulation ⁇ for instance plastic encapsulation) , in particular in the scenario of delarnination at this interface (for instance under the influence of moisture) .
  • this can be achieved by a full surface coverage of the semiconductor chip by the electrically insulating layer ⁇ in. particular from paryleae) , wherein an obtained insulating chip may be embedded wrthin a package ⁇ such as an embedding i r: a printed circuit: coard or in a BLADE package; .
  • exposure of the contact cads of the chip to the encapsulant and the electrically insulating layer is accomplished in a single common procedure (for instance by laser ablation, m which the same laser beam peneirates firstdiy a part of she encapsoiant and Lheri the electrically insulating layer) .
  • the described architecture can be implemented in very different, package concepts, such as a BLADF. package iconpare Figure 11; to Figure 12), an embedded chip in a P.' , a chip embedded in a plastic encapsula ion, etc.
  • opening of a package up to the chip pads can be accomplished by processes su:h as laser ablation.
  • a parylene coated semiconductor chip can oe implemen ed in each standard package, for example in a s Ide-by-side configuration (see Figure 3) or in a stacked configuration (see Figure 4), with a voi e bond architecture (see Figure .14), with a clip a rch i rec sure , with a flip chap architecture, etc.
  • the described packaging technology is compatible with each package architecture in which at least one semiconductor chip shall be reliably isolated with regard to the e n ironment (such as neighbored chips and/or traces and/or contacts ) ,
  • an insulated, chip as described above may be implemented advantageously in a chip embedding concept based on an inverse cavity formation architecture.
  • die attach can be carried out according to an exemplary embodiment on a planar copper surface and before formation of the annular surrounding structure.
  • the latter is only formed after mounting of the insulated chip and then, delimits a chip accommodation cavity without inaccuracies. This is more simple in terms of processing and apparatus effort, and is more efficiency, safer and cheaper,
  • a semiconductor chip In order to prevent a semiconductor chip from electric, chemical and/or mechanical deterioration or damage and for passivatirrg and isolating the semiconductor chip from an electrolysis bath and other chemicals used, for forming the lateral surrounding structure, it can be covered for instance on five of six surfaces hereof with the dielectric and protecting insulating layer. For exam le, this can be accomplished nicer sawing and expanding on a sew foil, Preferably, the backside of the sendconduct or chip is protected by saw foil and will not be covered.
  • solderable o sinterable backside such as e multilayer arrangement with a silver structure
  • a reservoir of diffusion solder mate rial such as Au3n, SrcAg
  • a leadframe may be used as mounting base.
  • Such a leadframe may be untreated and may have a surface of low and homogeneous roughness depth (for instance may be rolled with a maximum roughness depth of 400 mri) and nay be free of disturbing oxides (for e am l anti-tarnish layer, for instance benzo r r ra sole ) ana organic co minants.
  • die attach can be carried out. After the die attach, the chip is still protected on five of six surfaces by the insulating layer.
  • the backside is electrically conductively connected fe the mounting base or leadframe by the die attach medium and is also protected.
  • material deposition in particular copper deposition
  • material deposition can be carried out until the chip is oi rcumferen t i a i 1 y completely embedded in the deposited material and remains only unencaosulated on its top.
  • the protecting insulating layer prevents advantageously any undesired direct contact between the surface /sidewa lis of the semiconductor chip on the one hand and a chemical (such as a copper electrolyte ⁇ used during the deposition procedure on the other hand. Consequently, an efficient: protection against mechanical and chemical damage is provided.
  • On the sidewalls it further functions as mechanical buffer between semiconductor material (such as silicon) and deposited copper. Since a gate pad and an emitter pad, for instance, are additionally isolated from one anther and protected by the protecting insulating layer, any electrosta ic discharge damage during and after copper deposition can be safely prevented ,
  • the mounting base can be further processed and patterned for completing the packaging procedure. This may involve placing the formed arrangement into an annular surrounding structure in particular in a way to obtain a structure with a planar top surface to provide a proper basis for a subsequent lamination of one or more l v rs on one c r bor h oppos i ng ca ⁇ n surfaces sf he arrangement.
  • she dielectric protection layer surrounding a major surfsee portion of the semiconductor chip may be configured so that a laser beam used for drilling access holes in one or more of the lamination layers tor laser via forrnac. ion can also loc ll remove part of the protecting ins l ting layer together with material of the laminate layer ,s) thereon.
  • a particularly appropriate material, for the mentioned purpose is parylene.
  • oarylene it is possible to use another dielectric material which can be properly deposited, sas a high disruptive strength and robustness against diffusion.
  • Advantages of the described embodiment are a robust processing during die attach and the oossiorlity to use well- known procedures for package formation, Furthermore, fine process is significantly more tolerant with regard to inaccuracies and tolerances of the plated copper layer thickness (the chip edges are protected by the protecting insulating layer) . Furthermore, the chip surface is protected during a roughing procedure of the mount ng base (such us a leadf ramie ) , which roughening procedure is advantageous for improving adhesion of the laminate. This allows the use of a thinner copper layer on the front side, which reduces costs and increases compactness.
  • i * is also possible to use cooper alloys or a different material [s c as nickel, iron, aluminum, etc.) for deposition.
  • order materials such as metallic sheets like coated molybdenum, laminates, etc. ⁇ , in particular as a basis for a subsequent plating procedure.
  • a protection layer is deposited on surfaces ⁇ for instance on five of six sides) ct an semiconductor chip for preventing the latter with regard to mechanical and in particular chemical damage.
  • the material of this protection layer can be configured to be pat ernable by a laser.
  • the protection layer may be used as a barrier and buffer around a chip in order t.o embed the latter after she mounting on a carrier circumferentialiy with a plated layer (for instance functioning similar as a quasi-plating resist) .
  • Such features may be implemented, in a procedure described below in detail referring to Figure 15 to Figure 26.
  • Figure 1 shows a cross-sectional view of an electrically hermetically sealed insulated ship 100 being hermetically surrounded by an electrically insulating layer 104 according to an. exemplary embodiment.
  • the insulated chip 100 comprises a. semiconductor chip 102 , for instance a power semiconductor chip comprising a transistor or a diode for a ha l f bridge.
  • the semiconductor chip 102 is a naked, unpackaged semiconductor chip consisting of a silicon body having an integrated circuit therein and naving chip pads 1 6.
  • the s mi conduc a r chip 1 02 aa a be direaaiy obtained from singuiating (for instance sawing) a processed semiconductor wafer.
  • An electrically insulating layer 104 embed L d as a ccwrf orm.ally deposited thin film of dielectric material sach as paryiene, -son 1 nuously and fully cir oam.ferentiai i.y coats the entire surrounding surface of the semiconductor chrp 102 with homogenous thickness and without interruption. In other words, an entire exterior surface of the semiconductor chip 102, including the pads 106, is covered with the electrically " insulating layer 104. Thus, a flow of electricity between an exterior and an interior of the insulated chip 100 is disabled by the dielectric shell or wall hermetical ly sealing the semiconda rror chip 101 with reward to an electronic periphery.
  • the insulated chrp 100 has an external surface which is continuously covered with a continuous uniform film of the electrically insulating layer lul.
  • the thru fri of rne electrically insulating polymer is deposited on the unpackaaod semiconductor chip 100 equipped with the pads 106 by Chemical Vapor Deposition (CV0P .
  • Figure 1 shows a semiconductor die completely covered with an isolation layer, preferably paryiene.
  • the insulated chip 100 can be embedded in an encapaulant, and an access hole can be formed through the encapsulant and the electrically insulating layer 104 in a common procedure ⁇ see Figure 11) to thereby open the lectrically insulating layer 104 selectively at and limited to the positions of the chip pads 106.
  • the insulated chip 100 shown in Figure 1 can be used in particular also for the following processing path:
  • the fully insulated, chip 100 according to Figure 1 can be mounted on a chip carrier (for instance by die bonding) .
  • Figure 2 sheae a cross -sect iona 1 view ot an insula ed chip 100 according to an exemplary embodiment with exposed pads 106,
  • the entire semiconductor surface of semiconductor chip 102 is hermetically covered by electricall insulating layer lOi. in other words, the entire exterior surface of the insulated chip 100 is formed by the electrically insulating layer 104, wherein the pads 106 form the only exception by also contributing to the exterior surface of the insulated c ip 100.
  • the difference between the insulated chip 100 according to Figure 0 ant care insulated chip 100 according to Fi ure 1 is that, according to Figure 0, access holes 200 are formed by laser ablation (see reference numeral 202) to remove material of the electrically insulating layer 104 selectively at the positions of the cnip pads 106, In other words, the electrically insulating layer 104 is interrupted only at the.
  • Figure 2 shows a semiconductor die covered with an isolation layer, but having contacts opened ⁇ for instance by laser ablation) so that the insulated chip 100 according to Figure 2 can be directly further processed, by wire bonding I see Figure 3 and Figure 4) .
  • the electric contact pads 106 of rhe insulated chip iaO have been opened (for instance by laser ablation, plasma oioressing, er chemically] so that he insulated chip 100 according to Figure 2 can be used as a basis for very different mounting procedures such as wir- bending (compare Figure 3, Figure i or Figure 14), flip chip processing, clip processing, etc.
  • the insulated chip 101 recording to Figure 2 can oe implemented in many different packaging architectures, such as EGA (Ball Grid Array) , Cod (Quad Fiat do Leads Package) , QF? (Quad Flat Package., Sol (Small Outline Transistor;, etc.
  • the rnsulateei chip lee tea form the basis of a single chip package or a mubttchdp package
  • Exemplary embodiments of the ian/ention may also be implemented in terms of ISOFACE technology (in particula to provide galvanic isolated high side switches and repat ntegrat d circuits) .
  • Figure 3 shows a cross-sectional view of a semifinished package with semiconductor chips 1C2, 300 mounted side-by- side according to an exemplary embodiment before encaps a 1 ati on .
  • the soma finished (since not yet encapsula ed; package shown in Figure 3 comprises the insulated chip IOC according to Figure 2, a further semiconductor chip 300 (in the shown embodiment naked die without electrically insulating layer 104) , and band wires 300 electrically connecting an exposed pad 10 o of the in s 1 .hi a fed ch 1p 100 ith a pa d 106 of t ite further semiconductor chip 102.
  • Figure 3 furthermore shows that further pads 106 of the insulated chip 100 and of the further send.conduct.or chip 300 car: oe connected by further bond wires 302 to an electronic environment (neb shown) .
  • the semifinished package according to Figure 3 additionally comprises a mounting base 304 (i.e. any substrate or chip carrier, for example a leaoframe or an organic substrate) on which both the insulated chip 100 and trie further semiconductor chip too a e mounted in a side-by- side arcnit.ectu.re with wircbond inte connection.
  • a mounting base 304 i.e. any substrate or chip carrier, for example a leaoframe or an organic substrate
  • the semifinished package can be encapsulated (for embedding insulated chip 100 and further semiconductor chip 300), for instance by lamir.at.ion cos shown in Figure 13) or by molding ;as shown in Figure 14) .
  • the electrically insulating layer 104 provides for a reliable electric decoupling between the insulated chip 100 and the r urt he r s raicond uc tor cin 1p 300.
  • Figure 4 shows a cross-sectional view of a semifinished package with semiconductor chips 102, 300 mounted in a chip- cn-cnop architecture according to another exemplary embodiment before encapsulation.
  • the embodiment of Figure 4 shows a configurate on in which the further semiconoiuct or chip 300 is mounted on the mounting base 304, and the insulated chip 100 is mounted, in turn, on the further semiconductor chip 102.
  • the electrically insulating layer 104 provides for a reliable electric decoupling between the directly connected arrangement of the insulated chip 100 and the further semiconductor chip 300 in the shown stacked die configuration.
  • the semifinished package can be encapsulated (for embedding insulated chip 100 and further semiconductor chip 300), for instance by lamination (as shown in Figure 13) or by molding ⁇ as shown in Figure 1.4) .
  • the (electricall insulating layer 104 pro ides for a reliable el ctric d oupling between the insulated chi 100 and he further semiconductor chip 300,
  • Figure 5 to Figure 9 show structures obtained during carrying our a method of manufacturing a plurality of insulated chips 100 in a batch rchitecture according to another exemplary embodiment.
  • the goal of the described me hod is to simultaneously manufacture a plurality of insulated ehrps 100 according to Figure 1.
  • a plurality of naked semiconductor chips 102 is mounted or placed on. an auxiliary carrier 500.
  • the semiconductor chrps 102 are mounted, after dicing from a semiconductor watery on the auxiliary carrier 000 which ⁇ : ⁇ . ⁇ be a dicing foil .
  • This deposition procedure can be accomplished by a CVD process by which electrically insulating material such as parylene is deposited from the gas phase on exposed, surfaces of the semiconductor chips 102 and of the auxiliary carrier 500.
  • the structure 62.0 is slipped or pivoted by ls0°, to thereby attach ⁇ according to Figure 6 upper) surfaces of the semiconductor chips 100 already covered with the electrically insuiatina material on a further auxiliary carrier 700.
  • This procedure can be denoted as a re-lamination.
  • surface portions of the semiconductor chips 102 covered with the previously deposited electrically insulating material are mounted on the further auxiliary carries 700.
  • a flipping of the dice is performed for re- laminar ion onto the further auxiliary carrier 700 (for instance a foil or any other carrier) in order to prepare the structure " '20 for subsequent hacks i do coating.
  • the auxi liary carrier too is removed from the seer ⁇ conductor chips 102, to thereb expose the 'according to Figure 7 upper) surface portions of the semiconductor chips 102 which have preciously been covered by the auxiliary carrier 500.
  • the further auxiliary carrier 200 is detached or removed from the insulated chips 100.
  • the described method is carried out simultaneously with the plurality of semiconductor chips 1 0 2 , thereby producing a large number of semiconductor chips : ' 02 in a quick and simple procedure carried ore: on wafer level after singularization (for instance sawing) .
  • FIG. 10 shows a semifinished pa-? kage a esiuotioig to as exemplary embodim nt. before expos ir.q chip pads . ' 06 (by removinq material of r. en.capsula.nt 1000 and of e l ectrically insulating layer 104 in a common procedure) .
  • cne insula tea chip 100 (or instance reecasfaotured according to Figure t to Figure 0) is encapsula t ed by an encapsuiaitt 1000.
  • the eocapsulant 1000 is a laminate composed of a mounting base 1002 (on which a bottom af the insulated chip 100 is mounted) and of a cover 1004 (covering a op: cf the insulated chip 100; , she mounting base 1000 can be made of an electrically conduce! ve material (for instance a copper sheet, for example having a thickness of about 200 gmb .
  • the cover 1004 can be made of an electrically insulating material (lar instance a cropreg foil tilth or without pure fcanned cavity tot acc.ommodar.ing the insulated chip 100) .
  • One insulated ship 100 may be mounted on the mounting base 1002, for instance by gluing or soldering,
  • the semiconductor chip 102 may have a (according to Figure 10 vertical.! thickness in a range between 30 gin ami 20.) pm, for instance 60 usu
  • the mounting base 1000, the insula t ed chip 100 and the cover 1001 can be connected to one another by lamination, i.e. by pressing them together supported by heat.
  • the insulated chip 100 can be embedded into a iaminat- ofcr instance m terms cf a FOB process or a BLADE process ; .
  • Figure 11 shows the semifinished package of Figure 10 after exposing chip pads 106 by removing material of encapsuiant 1.000 and of electrically insulating layer 104 in a common procedure.
  • common access holes 1100 are formed by laser ablation (see reference numeral 1110) to extend through both the encapsuiant 1000 and the electrically insulating layer 104.
  • the access holes 1100 are formed in a common procedure to thereby expose the chip pads 106.
  • opening of encapsulant 1000 and electrically insulating layer 104 is accomplished in the same process, here with she same laser bean.
  • Figure 12 shows a cross-sectional view of a package 1200 according to an exemplary embodiment obtained by the manufacturing method according to Figure 10 and figure 11.
  • the common access holes 1100 are filled 'for instance using a galvanic process) with electrically conductive material to thereby manufacture vias 1202 contacting the pads 100 in the access holes 1100.
  • a patterned electrically conductive layer 1204 (such as a patterned copper foil) is formed as a surface wiring on fin? ⁇ on the surface dielectric) encapsulant 1000 and electrically counted to the electrically conductive material forming the oias 1202. The, via tilling and formation of conductor fines compietes the m ufacturing procedure of the package 1200.
  • the electrically insulating layer 104 is arranged for electrically insulating the semiconductor chip 102 from one or more possible further semiconductor chips (not shown) of the package 1200, electrically conductive layer 1204, and one or more possible electrically conductive contacts (not shown) of the package 1200.
  • This ensures a. reliable electric decoupling of the semiconductor chip 102 from the electronic periphery and therefore an efficient protection against creep currents and disruptive discharge.
  • This is particularly advantageous when the package 1200 is configured for high current or high v .i ge applications such as a current censor application based on magnetic sensing, a hail bridge ap lication, etc.
  • the full-layer-encapsul ted insulated chip 10c can be adhered onto the electrically conductive mounting base 1002 (such as a lead frame or a printed circuit board) and can be laminated with the cover 1004 (such as printed circuit board material ⁇ .
  • the electrically conductive mounting base 1002 such as a lead frame or a printed circuit board
  • the cover 1004 such as printed circuit board material ⁇ .
  • contacts in form of the access holes 1110 are shot info the encapsalant 1000 to thereby expose the chip pads 106.
  • the access holes 1110 can be galvanicaily filled with electrically conductive material such as copper.
  • a highly advantageous effect of such an embodiment is that tnrs access hole formation procedure simultaneously removes material of the encapsulant 1000 ana the electrically insulating layer 104, in particular exclusively and exactly at the positions required for obtaining access to the chip pads 100.
  • the resulting package 1200 then comprises the fully embedded semiconductor chip 102 which, apart from its chip pads 106, is completely electrically insulated with regard to the envi ronment ,
  • the access hole formation as a basis for the upper chip metallization can be preferably carried out so that the laser automatically stops on the metallization (i.e. the chip pads 106) after forming the openings in the electrically insulating material of the electrically insulating layer 104 and the cover 1004.
  • copper as material for the chip pads 106 is h i gh 1 y approp ria te .
  • Figure 13 shows a cross-sectional view of a package 1200 according to another exemplary embodiment of the invention.
  • the package 1200 provides an electronic half bridge function.
  • the insulated chip 100 and a conventional naked semiconductor chip 300 are both embedded in the encapsulant 1000,
  • the insulated chip 100 may be glued to the mounting base 1002, whe rea s the semiconductor chip 300 may be assembled on the rn.ounti.ng base 1002 using an electrically conductive interconnect 1300,
  • the mounting base 1002 may for instance be a base substrate such as a metal foil or sheet.
  • the mounting base 1002 may also be a current carrying rail in the case of a current sensor based on magnetic field sensing.
  • a ground contact is denoted with reference numeral 1302 in Figure 13.
  • a detail 1350 of Figure 13 shows an enlarged view of the surrounding of the insulated chip 100.
  • a safe creepage distance, 1, is achieved, even if the cover 1004 delaminates from the electrically insulating layer 104.
  • a save isolation distance, d is defined by the thickness (for instance 10 grid of the electrically insulating layer 104.
  • a top surface ot the package 1200 according to Figure 13 can be mounted on a printed circuit board (PCBJ, for instance via solder balls (not shown) .
  • PCBJ printed circuit board
  • a possible current flow path during operation of the package 1200 according to Figure 13 is indicated with reference numeral 1390 and extends from the electrically conductive layer 1204 at the top surface, through one of the vias 1202, along the electrically conductive mounting base 1002, via the conductive interconnect 1300, through the further semiconductor chip 300, through another one of the vias 1202, and. back to another portion of the electrically conductive layer 1204 at the top surface.
  • the electrically conductive mounting base 1002 may contribute to the current flow and may simultaneously function as a heat sink for removing heat generated by the chips 100, 300 during operation of the package 1200.
  • Figure 14 shows a cross-sectional view of a package 1200 according to yet another exemplary embodiment of the invention.
  • the package J 200 shows an example of a ire bond arch ecture by which the insulated chip 100 according to Figure 0' is embedded in a mold compound as encapsulant 1,000,
  • the package 1200 further comprises a chip carreer 1400 embodied as a leadiraaie which carries the insula t ed chip 100.
  • a chip carreer 1400 embodied as a leadiraaie which carries the insula t ed chip 100.
  • One insulated chip 100 is mounted en the chip carrier 1400 by an adhesive material 1402. Bond wires 302 are provided for electrically connecting a. respective one of the chip pads 106 with a respective lead of the chip carrier 1400.
  • the package 1200 according to
  • Figure 14 has leads of the lead frame 1400 on the left-hand, side and on the right-hand side of the package 1200 which are in flesh with sidewalis of the encapsulant 1000.
  • Such a configuration can be im lemented in accordance with Q 100 ⁇ Quae Flat ho head) packaging technology.
  • the package 1200 according to Figure 14 has leads of the lead frame 1100 on the left-hand side and on the right-hand side of the package 1200 which laterally extend beyond sidewalis of the encapsulant 1000, thereby forming free terminals oi gull-wing shape shown as dotted lines according to Figure 14.
  • Such a. configuration can be implemented in accordance with 00 ⁇ Small Outline) or QFP packaging technology .
  • Figure 15 to Figure 26 show structures obtained durinq od.rryir;q out a method of man fac uring a plurality f packages 1200 in a baton architecture according to another exemplary embodiment oL the invention.
  • the structure sr.own in Figure 15 is a processed semiconductor wafer 1000 comprising a plurality ol semiconduc or chips 100 with integra ed circuit elements (such as SFETs or IGBTs, not shown) .
  • a processed semiconductor wafer 1000 comprising a plurality ol semiconduc or chips 100 with integra ed circuit elements (such as SFETs or IGBTs, not shown) .
  • the semiconductor wafer 1000 is thinned and sawn on a saw frame (see reference numeral 1600) .
  • the semiconductor wafer 150 comprises a plurality of semiconductor chips 100 arranged in rows and columns.
  • the semiconductor wafer 1500 as shown in Figure 10 is made subtest co a coating procedure for forming trie electrically insulating layer 3.0 ⁇ on all exposed surfaces of all semiconductor chips (,02. Thereby, a dielectric coated semiconductor wafer 1700 is obtained.
  • the sawn semiconductor wafer 1000 can be expanded during the coating procedure. This can bo accomplished by correspondingly bending the flexible foil ro increase the spacing between adjacent semiconductor chips 102 during the coating procedure. This may prevent undesired shading effects and may therefore reduce the risk of incompl e; coating of the five mentioned surfaces of the semiconductor chips 102 to be coated. Subsequently, the individual 1 formed insulating chips 00 e released from the fi.exi.ble foil and are i ureter processes; as shown in she following figures.
  • a. mounting base 1002 provided, such as a planar or rolled copper s hee ⁇ or a lead i raine ,
  • the insulated chip 100 is mounted directly on the planar mounting base 1002.
  • this is a very simple procedure, In other words, the mauntires base 1002 is advantageous i.y initially free of any cavities which are only formed, thereafter by an additive process (compare Figure 21) ,
  • This has she significant advantage that the remarkable effort for manufacturing cavities with high reliability by a subtraotrve piuscedare (in particular Involving lithography! can be cm.in ted.
  • Bonding the semiconductor chip 102 to the mounting base 1002 may be accomplished for example by soldering (for instance by soft soldering or Gold-Tin soldering) or by sintering .
  • the upper ana lower main surfaces of the mounting base 1.002 may be roughened in preparation of a subsequent galvanic deposition procedure (see ro uqh surfaces 2000, as shown in details 2010, 2020, More generally, the exposed surface of the mounting base 1002 can be preconditioned for subsequent plating.
  • a preconditioning may be the shown roughening procedure, or may additionally or alternatively involve cleaning of the surface ,
  • a lateral surrounding structure 2100 made of the same material (here copper) as the mounting base 1002 is formed.
  • a cavity is delimited i n which the insulated chip 100 is laterally embedded.
  • the lateral surrounding s t ruc t u re 2100 is vertical i n flush (i .e.
  • forming the lateral surrounding structure 2100 on the mounting base 1002 is accomplished by an additive procedure in form of galvanicaily plating. Simultaneously with the formation of the lateral surrounding structure 2100, the galvanic plating procedure also forms a counter structure 2102 on a main surface of the mounting base 1002 opposing a further main surface of the mo u n t i ng base 1002 on which the lateral surrounding structure 2100 is arranged.
  • a double-sided galvanic coating of the mounting base 1002 (here embodied as copper sheet) is carried, out (copper plating) .
  • a vertical thickness, d, of each of the structures 2100, 2.102 can be for example 150 um .
  • the structures 2100, 2102 can be formed by immersing the structure shown in. Figure 20 in a galvanic bath and by applying current.
  • p roced ur e s , t he e 1ect, ri ca.11 y i nsu1at i ng 1a ye r 10 o f pa ry1ene protects the semiconductor chip 102 with regard to the environment, from a mechanical and chemical point of view.
  • the silicon material of the send conductor chip 102 shall not c me into direct contact with tne galvanic chemistry as vac 11 an with copper m terial, because this might destroy he semiconductor chip 102, Then, the parylene material of the electrically insulating layer 104 also serves as a powerful passivation of the semiconductor chip 102 with regard to harsh conditions in the environment.
  • Figure 22 shows a three-dimension l view of an arrangeme t of multiple components, one of which being shown in Figure 21, connected via a bar and web structure 2200.
  • the manufacturing procedure can be carried out as a batch.
  • the arrangement of Figure 22 is siryularized into a plurality of semifinished packages 2300, for instance by punching.
  • the lateral surrounding structure 2100 and the insulated chip 100 en the mounting base 1002 are, i.e. a s mifinished package 2000 as sunown in Figure 20 2s, inserted info a late ally surrounding annular structure 2400 ⁇ for instance made of E ' fol material which may comprise cured resin and glass fibers) being vertically in flush with the lateral surrounding structure 210e and with the insulated chip 100.
  • the singalariced semifinished paceacnes 2300 are inserted into cavities of a frame s reet ere. With a thickness, 0, of for instance 1.2 mm, the structure according to Figure 24 is highly compact.
  • the annular structure 2400 may be a printed circuit board with punched, through holes in which the semifinished, packages .2300 may be inserted in a batch manufac uring procedure.
  • two top layers 25-00, 2502 are arranged as planar sheets or foils on a too surface of the insulated chip 100 and tho laterally scr round inc; structure 0100 and the Lateral su ounding annular structure 2400,
  • two oof torn layers 2504, 2506 are arranged as pJanar sheets or foils on a bottom surface of the counter structure 2102 and the lateral surrounding annular structure 2400,
  • the elements of the so obtained sandwich or layer: stack are ocnno otoo o one a no the r by 1 ami nat r on by app 1 y i ng mechani ca 1 pressure and thermal energy.
  • Layers 0500, 2504 are electrically insulating, whereas layers 2502, 2506 are electrically conductive (for instance are made of copper) .
  • the procedure described referring to Figure 25 results in an encapsul as i an of the semifinished package 2200 by lamina ion, layers 2a00, 2504 may be resin-rich piepreg layer, i.e. uncured resin with glass fibers therein. curing the lamination, part of the resin flows into lateral recesses 2450 (compare Figure 24 ⁇ between the semifinished package 2300 and the annular structure 2400 and therefore fills empty ga s .
  • vertical interconnect structures 2600 art formed in a top portion of the structure shown in Figure 25 vertically extending through the electrically insulating top layer 2500 and through the electricaLiy insulating layer 104 for providing an electric connection with the chip pads 106.
  • forming the vertieal interconnect structures 2600 comprises laser drilling common access holes ⁇ see reference numeral 1100 in Figure 11) extending through both the electrically insulating top layer 2500 and the electrically insulating layer 104 in a common procedure to thereby expose the chip pads 106.
  • the electrically insulating layer 104 is advantageously made of a material being removable by laser drilling, such as parylene.
  • the common access holes are filled with electrically conductive material such as copper.
  • Figure 26 shows that the semiconductor chip 102 is electrically contacted via correspondingly formed laser vias.
  • the package 1200 shown in Figure 26 according to an exemplary embodiment of the inven ion is obtained.
  • the package 1200 comprises the above described insulated chip 100 and an encapsulant 1000 encapsulating the insulated chip 100.
  • the package 1200 shown in Figure 26 is manufactured in a batch procedure with .multiple other packages 1200 (for instance when using a printed circuit board with punched through holes as annular structure 2400, wherein the semifinished packages 2300 are inserted in these through holes ⁇ , such a structure first needs to be singularized into the individual packages 1200, for instance by sawing.
  • a cover 1004 of the encapsulated 1000 comprises the lateral surrounding structure 2100 consisting of copper which delimits the cavity in which the insulated chip 100 is embedded vertical in flush with the insulated chip 100.
  • the cover 1004 also comprises the two described top layers 2500, 2502 covering the top surface of the insulated chip 100.
  • the two top layers 2500, 2502 additionally cover a top surface of the lateral surrounding structure 2100.
  • the two top layers 2500, 2502 comprise the lower electrically insulating top layer 2500 directly covering the top surface of the insulated chip 100 and being penetrated by the vertical interconnect structures 2600 providing for an electric connection with the chip pads 106.
  • the two top layers 2500, 2502 compri se upper electr ica 11 y cond.uct ive 1 a yer 2502 di rec11.y covering the lower layer 2500' and being connected to the vertical interconnect structures 2600,
  • the lateral surrounding structure 2100 is made of an electrically conductive material such as copper and is laterally surrounded by the electrically insulating annular structure 2400 being in flush with the lateral surrounding structure 2100.

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Geometry (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)

Abstract

An insulated chip (100) comprising a semiconductor chip (102) comprising at least one chip pad (106) and an electrically insulating layer (104) surrounding at least part of the semiconductor chip (102).

Description

Insulated die background Technical Field
Various embodiments relate generally to an insula, red chip, packages, and methods of manufacturing packages, Description of the related art
Packages may oe denoted as encapsulated electronic chips with electrical connects extending out of the encapsalant and being mounted to an electronic periphery, for instance on a. chip, carrier such as a printed circuit board.
In particular electronic power packages, for instance half bridge circuits or current. sensors, may comprise semiconductor chips which need to be mounted in an electrically insulated manner fin particular with regard to neighbored traces, other chips or other electric potentials in the environmen 5 · Conventionally, semiconductor chips are mounted on a mounting base via non-conductive glue body to provide an insulation of at least one metal pad on the semiconductor chip. Also a bulk encapsulant (tor instance a mold, or a laminate of a dielectric plastic material) may contribute to the electric insulation.
However, it is difficult to precisely adjust properties of such electrically insulating adhesive body (in particular in terms of dimensions, process stability, etc.) . Additionally, many conventionally used adhesive materials have insufficient electrically insulating properties, in particular when a. high dis uptive strength is required. Consequently, conventional packages may softer from the problem that undesired. creep currents can flow, under undesired circumstances such as delaminat ion , between an encapsulated electronic chip and another electrically conductive s ructure (such as another electronic chip, a trace, a via, etc.) of the package, which may deteriorate reliability of the package.
Sura ar y
There may be a need for a chip and a package with a chip which provide a high d sruptive strength and a reliable protection against creep currents. Additionally or alterna ively, there may be also a need for a chip and a package with a chip which are roanu facturable by a robust and efficient manufacturing process and provide a reliable protection of the chip daring processing.
According to an exemplary embodiment, an electrically insulated, chip is provided which comprises a semiconductor chip (for instance a naked, urepackaged die singulated direccly from a semiconductor wafer.) comprising at least one chip pad (for instance a metallic chip pad) and an electrically insulating layer surrounding sin particular covering, more particularly covering in direct contact with semiconductor material of the semiconductor chip) at least part (in particular at least 60%, more particularly at least 901, of an external surface) of the semiconduc or chip.
According to another exemplary embodiment, a method of manufacturing an insulated chip is provided, wherein the method comprises providing a semiconductor chip comprising at least one chip pad, and surrounding (in particular coating, more particularly conformally coating) at least part of the semiconductor chip (in particular including side surfaces of the semiconductor chip; with an electrically insulating layer . According to yet another exemplary embodiment, a packa e is provided which comprises an insulated chip having the above-mentioned features, and an encapsulant encapsulating at least part of the insulated chip (in particular covering at least part of the electrically insulating layer) .
According to yet another exemplary embodiment, a method of: manufacturing a package is provided, wherein the method comprises manufacturing an. insulated chip by a method having the above-mentioned features, and encapsulating at least part of the insulated chip by an encapsulant.
According to yet another exemplary embodiment, a packaqe is provided which comprises an insuiaoed chip having the above-mentioned features, a further semiconduc or chip (which may be configured as an insulated chip having the above- mentioned features, or as a packaged or non-packaged chip without electrically insulating layer), and at least one bond wire electrically connecting the insulated chip with the fu r the r s em i c onduc to r chip.
An exemplary embodiment has the advantage that a thin dielectric layer (rather than a bulk material) is applied onto the entire surface or at least onto a significant portion of the surface of the unpackaged semiconductor chip- to provide for a very compact and reliable dielectric isolation within an encapsulation. By providing a dielectric shell directly contacting or covering the exterior semiconductor surface of the semiconductor chip, there is a high freedom to select the material of the electrically insulating layer for the purpose of a reliable electric insulation for suppressing creep current and increasing disruptive strength. A procedure of conformaliy applying this electrically insulating layer is precisely controllable and is compatible with a batch processing on wafer level. Phis architecture of electrically isolating a naked die also allows to provide for a reliable isolation of sidewalls and/or an active chip side of the semiconductor ch p, thereby providing an efficient protection against undesired creep currents and voltage induced degradation along an interface 5 between semiconductor chip and encapsulation (in particular in the event of delamination at this interface) . Such parasitic phenomena, which are conventionally promoted by moisture, can be efficiently suppressed by the electrically insulating layer encasing the semiconductor chip,
10 Advantageously, a procedure of exposing one or more pads of the insulated chip for externally contacting the insulated chip by removing selected portions of material of the electrically insulating layer on the pad(s) can be accomplished simultaneously with the procedure of forming an
15 access opening in an encapsulant in which the isolated chip is encapsulated , Tills a 1.1 ows to rapidly manufacture the electric contacting structure of the package.
The insulated chip and a corresponding package can be manufactured by a robust and efficient, manufacturing process
20 and provide a reliable protection of the ch p during processing, in particular may protect the chip against damage by chemical and mechanical impact during the manufacturing process .
^ ~' icr off "'-y' f ύ r' of further exemplary embyod i nte n s
In the following, further exemplary embodiments of the insulated chip, the packages and the methods will be ex lained ,
30 In the context of the present application, the term
"semiconductor chip" may particularly denote a naked die, i.e. a non-packaged (for instance non-molded) chip made of a processed semiconductor, for instance a. singulated piece of a semiconductor wafer. One or more integrated circuit elements (such as a diode, a transistor, etc.; may be formed within the semiconductor chi .
In rhe context of the presert a plication, rr.e term "pad" may particularly denote an electrically conductive contact: or terminal formed on a surface of the naked die which allows to electrically contact the one or more i n:eg r a eci c 1 rcu 1 r e 1.eme n 1s of the som 1 conda.cior chip, For example, a supply sicptal, a control signal or a data signal may be conducted from an electronic periphery into an interior of the package and into the semiconductor chip via the one or more pads. In a similar way, a supply signal, a cone ro: signal or a data signal may he conducted from the semiconductor chip to the electronic periphery via the one or more pacis , The pads may be embodied as metallic islands on the die.
In the context of the present application, the term "electrically insulating layer" may particularly denote a thin, film or a coating of a dielectric material covering a surface of the semiconductor chip ufor example at least partially in direct contact with semiconductor material) and safely disabling any flow of electricity between an electronic periphery and the semiconductor chip through the electrically insulating layer. In particular, the thickness of such a layer may be in a range between 1 pro, and 100 pro, in particular in a range between 5 pm and 50 pm. When the thickness falls significantly below? 1 pm, electrical insula ion and fluid tightness of the layer may become too low. It lne thickness significantly exceeds 100 urn, costs may become coo high, and limitations in terms of heat removal capability may occur.
In the context of the present application, the term "package" or module may particularly denote one or more semi concluc t or chips, opr. i orally comprising core or more:: other kind of electronic components in addition, embedded within an encapsulant such as a meld or a laminate.
In an embodiment, an entire s rrounding surface of the semi conductor chip and the at least one D d is covered with the electrically insulating layer. By taking this measure, a hermetically closed insulating chip is obtained which is shielded again electricity through the c i rcu feren 1 ia i iy closed dielectric film. In particular, also sidewalls and the active surface of the naked die may be protected in this embodiment ,
In an embodiment, a surrounding surface of the semiconductor chip excluding only at least one surface portion around the at least one pad is covered with the electrically insulating layer. While sidewalls and a portion of the surface of the naked die may be completely protected against electricity in this embodiment, direct access to the chip pads is nevertheless enabled (for instance to couple' the pads with bond wires) ,
In an embodiment , five substantially rectangular
surfaces of a substantially cuboid semiconductor chip are covered with the electrically insulating layer, and a sixth substantially rectangular surface of the semiconductor chip is free of the electrically insulating layer. Such an insulated chip may be implemented advantageously in a chip encapsulating architecture based on an inverse cavity plating concept, tor Instance as described referring to Figure 15 to Figure 26. The sixth rect ngular surface may be bonded on a mounting base such as a. Leadframe and/or may serve to provide for an elect ically conductive connection.
In an embodiment, the electrically insulating layer is made of a polymer material, in particular parylene. Other polymer materials which may be implemented are polyimide or polvaraid . Paryiene, which is a pr e fe r r ed marerfai in exemplary embodiments, denotes a variety of chemical vapor deposited pol ( -xylyiene ) polymers which may function as highly efficient moisture and dielectric barriers. Xylyiene comprises two isomeric organic compounds with the formula CtHbCh ': . Paryiene is particularly appropriate due to its combination of barrier properties and its capability to be processed. Paryiene may be enriched with one or more additives to precise] y adjust 'die desired materia] properties. Polymer materials, in particular paryiene, may combine an excellent electric isolation with a capability of reliably filling and flowing into even very narrow gaps during deposition, thereby ensuring also a sealing task concerning moisture. Moreover, su::h materials can be precisely ana rapidly removed by laser processing. It is possible to conformably deposit these material with homogeneous thickness from e gas phase. Furthermore, the mentioned materials, in particular paryiene, provide a pronounced protection against corrosion.
In an .embodiment, the electrically insulating layer is made of a material being removable by laser drilling to provide a defined and reproducible shape and. dimension. By taking this measure, via formation by laser patterning on the one hand and exposing one or more chip pads of the insulated chip on the other hand may be carried out by a single combined easer processing procedure, and hence very efficiently.
In an embodiment, the semiconductor chip is a power semiconductor chip. Such power semiconductor chips are specifically prone to failure in the event of creep currents or drsruptive discharge which may occur under high voltage or high current conditions. Power semiconductor chips may be used for automotive applications. Power semiconductor chips may comprise, as integrated circuit elements, power transistors and/or diodes.
n an embodiment of the manufacturing method, the process of surrounding or coating comprises mounting the semiconductor chip on an auxiliary carrier, and depositing a first part of the electrically irsuiatina material on an exposed part of the surface of the mounted semiconductor chip. Such an auxiliary carrier may be a late or foil on. which one or a plurality of semiconductor chips to be coated may be arranged. After the coating procedure, the semi. conductor ehip(s) may be detached from the auxiliary carrier for further processing.
In an embodiment, the surrounding {or coating) further ■comprises mounting a surface portion of the semiconductor chip covered with the deposited electrically insulating material on a further auxiliary carrier, then removing the auxiliary carrier, and subsequently depositing a second part of the electrically insulating material on an exposed part of the surface of the mounted semiconductor chip which has been covered by the auxiliary carrier during depositing the first part of the electrically insulating material. In such a remounting concept, it is possible to detach the semiconductor chip(s) from the auxiliary carrier and to attach another (previously exposed) surface of the semiconductor chip is) onto the further auxiliary carrier before a subsequent coating procedure. By taking this measure, if is possible to fully circumferential ly deposit the layer of electrically insulating material on each and every surface portion of the semiconductor chip(s) .
In an embodiment, the manuf cturing method is car ied out simultaneously with a plurality of semiconductor chips. Such a batch procedure allows for a very efficient processing , In an embodiment, the e J octr ically insulating layer is deposited from a gas phase, in particular by Chemical Vapor Deposition (CVDj . This procedure allows to obtain a reliably uriinterr uρ t ed homogeneoas 1 y ':. r 1 c k elect r 1 ca 11 y i n su1 a t i nq layer. However, alternative deposition procedures are possible, such as Physical Vapor Deposition (PVD], and Plasma Enhanced Physical Vapor Deposition {PECVDj ,
In an embodiment, the package comprises at least one electrically conductive via. Each via may extend through a respective common access hole extending through both the encapsulate and the electrically insulating layer. Thus, by a single via or other vertical interconnect element, it is possible to electrically penetrate both encapsulant and electrical i y conductive layer for getting access to the one or more chop cads.
In an embodiment, the encapsulant comp ises a laminate, in particular a printed circuit board laminate. In the context of she present application, the term "laminate structure" may particularly denote an integral flat member formed by electrically conductive structures and/or electrically insulating structures which may oe connected to one another by applying a pressing force. The connection by pressing may be optionally accompanied by the supply of thermal energy. Lamination may hence be denoted as the technique of manufacturing a composite material in multiple layers. A laminate can be permanently assembled by heat and/or pressure and/or welding and/or adhesives.
In another embodiment, the encapsulant comprises a mold, in particular a plastic moid, tor instance, a correspondingly encapsulated chip may be provided by placing the insulated chip (if desired together with other components, such as a leadframe) between an upper mold die and a lower moid die and to inject liquid mold material therein. After solidification of the mold material, the package formed by the encapsulant with the insulated chip in between is completed.
In an embodiment, the encapsulant comprises a mounting base on which a bottom of "he insulated chip is mounted and comprises a cover covering a top of the insulated chip. In particular, the mounting base may comprise an electrically conductive material (such as a metal sheet} and the cover may comprise a recessed or continuous electrically insulating material, For instance, a corresponding package or module may oo denotes as BLADE package or module (compare Figure 12 or Pi pure 13 ; .
In an embodiment, the cover comprises a lateral surrounding structure, in particular made of electrically conductive material, delimit ng a cavity in which the insulated chip is embedded, in particular vertical in flush with the insulated chip. The lateral su rounding structure may be an annular body surrounding and accommodating the insulated. chip. For instance, the lateral surrounding structure may be made of the same material as the mounting base and may be created after having mounted the insulated chip on the mounting base.
In an embodiment , the cover comprises at least one top layer covering a top surface of the insulated chip. Thus, encapsulation of the insulated chip, to which also the lateral surrounding structure contributes, may be completed by covering the insulated chip and the lateral surrounding structure by one or more planar layers, for instance connectaoie by lamination.
In an embodiment, the at least. one top layer additionally covers a top surface of the lateral surrounding structure. When the one or more planar top layers are applied to the la teara 1 surrounding structure and the insulated chip having the same vertical, height, the connection procedure may be accomplis ed by lamination {i.e. by applying heat and pressure) .
∑ r: an embodiment, the at leas': one top layer comprises a lower electrically insulating top layer directly covering the top surface of the insulated chip and being penetrated by at least one vertical interconnect structure providing for an electric: connection with the at least one chip pad. By taking this measure, the lower electrically insulating top Layer may ensure chat the various chip pads remain electrically decoupled from one another. However, when forming one or more through holes extending through the lower electrically insulating cop layer and filling these through holes with electrically conductive material, vertical interconnect structures such as viae can be formed. Highly advantageously, laser drilling for forming access holes as a basis for the vertical inte connect structures on the one hand and laser drilling fox exposing one or more chip pads of the insulated chip on the other hand may be carried out by a simple and single combined and simultaneous procedure.
In an embodiment, the at least one top layer comprises an upper electrically conductive top layer directly covering the lower a er and being connected to the at. least one vertical interconnect structure. The electrically conductive layer pfor instance a copper foil) may be directly connected with the one or more vertical interconnect structures.
In an embodiment, a surface of the insulated chip being directly arranged on the mounting base is free of the electrically insulating layer and/or is electrically coupled to the mounting base. For instance, it may be connected and electro early coupled by soldering to the mounting base, for instance a leadframe.
In an. embodiment, the lateral surrounding structure is made of an electricall conductive material and is laterally 5ΐϊ r rounded by an electrically msul. a. tire annular se ucr ure, in particular an electrically insulating annular structure being in flush (i.e. vertically aligned) with the lateral surrounding structure. Thus, the arrangement of insulated chip, latere: 3 y surroundina structure arid nounrirrs base may be arranged, in turn, in a cavity defined icy a central recess of the annular structure.
In an emhooaiment, the package comprises a counter s'uucuue on a main surface of the mounring base opposing a farther main surface of the mounting base on which the lateral surrounding structure is arranged. For example, the counter structure and the laterally surrounding structure may bpi formed in a common procedure and/or from the same materia), for instance may be plated g a I varni ca 11 y on opposing main surfaces of the mounting base. The provision of the counter structure provides for a more symmetric arrangement in the vertical direction, thereby suppressing bending and warpage of the package.
In an embodiment, the package comprises at least one bottom layer constituting a main surface of the package opposing a further main surface of the package constituted by the 3t least one top layer. Tire at least one bottom layer (tor instance an electrically insulating bottom layer and an electrically conductive bottom layer) may be connected to the package during the same lamination procedure in which the at least one top .Layer is connected. The provision of the at feast one bottom layer provides for a more symmetric arrangement in the vertical direction, thereby suppressing bending and warpage of the package.
In an embodiment, the electrically insulating layer is arranged for electrically insulating the semiconductor chip from at least one further semiconductor chip of the package and/or electrically conductive traces of the package and/or electrically conductive contacts of the package. FCy taking this measure, it may be dispensable to ensure that the further semiconductor e)iip(s), the electrically conductive trace -s) and/or the contact !s) are itself reliably insulated from the insulated chip, because tors function is acoomypl I seed by trie electrically insulating layer.
In an embodiment, the package further comprise:7; a chip carrier, in particular a leadframe, carrying the insulated chip, and at least one bond voire electrically connecting the at least one chip pad with the chip carrier. Such an embodiment can be advantageously realized with an insulated chip in which the electrically insulating layer is interrupted solely at the chip pad portions because this simplifies attaching the bond wires thereto.
In an embodiment, the package is configured as one of the group consisting of a current sensor (in particular a current sensor based on. magnetic sensing), a half bridge, a cascade circuit, a circuit constituted by a field effect transistor and a bipolar transistor being connected in parallel to one another, and a power semiconductor circuit. However, also other high current and/or high voltage and/or high power applications are compatible with the architecture of an insulated chip according to an exemplary embodiment of the inven ion.
In an embodiment, the method further comprises forming at least one common access hole extending through, both the encapsu ant and the electrically insulating layer in a single common procedure to thereby expose the at least one chip pad. According to such a highly preferred embodiment, a single hole formation procedure is sufficient to obtain access to the chip pads of the semiconductor chip being insulated by the (even hermetically closed;- electrically insulating layer and a surrounding (for instance also electrically insulating) encapsu 1 a i: i on . In other sords, true access hole formation proced re may simulta eously form a hole in the ;fcr instance hermetically sealed) electrically insulating layer and the encapsulant . In particular, the forming of the at least one common access hole comprises at least one of the group consisting of laser ablation, plasma processing, and chemica 1 I y rocessing.
In an embodiment, the method comprises mounting the insulated chip on a mounting base, in particular on a planar mounting base (rather than being inserted into a cavity during mounting) . This simplifies the mounting procedure, in particular in comparison to a scenario in which the insulated chip would have to be inserted into a recess or a cavity.
In an embodiment, the method comprises, after the mounting, forming a lateral surrounding structure, in particular made of the same material as the mounting base, delimiting a cavity in which the already mounted insulated chip is embedded, in particular vertical in flush with the insulated chip. Thus, the cavity c i r cumferentialiy
surrounding the insulated chip may be formed only after the mounting procedure, i.e. by an additive rather than by a subtract ive procedure. This simplrfi.es processing and increases reliability of the manufactured package.
In an embodiment, forming the lateral surrounding strueto.: re on the mounting base is accomplished by an additive procedure (for instance by material deposition), in
particuiar by galvanrcaiiy plating. When the mounting base is made of copper, for instance is a copper leadframe, galvanic deposition of material on this basis is enabled and is carried out for forming the laterally surrounding structure. This is a simple and very reliable procedure which does not harm the insulated chip. Its insulating layer protects the semiconductor chip in an. interior of the insulated chip c .;ring such a galvanic plating procedure from irne action with chemicals.
In an embodiment, the method further comprises inserting the lateral surrccnding structure and che insulated chip on the mounting base into a laterally surrounding annular structure (which may be made of electrically insulating material;, in particular an annular structure being in flush wich the lateral surrounding structure and the insulated chip. When the mentioned components are all in flush with one another, i.e. ail at the same height level, subsequent- connection of one or more additional layers by lamination is Promot ed and s im 1 i f ied ,
In an embodiment, the method further comprises
connecting at least one top layer to a top surface of the insulated chip and the laterally surrounding structure (and preferably an annular surrounding structure} , in particular DV laminating. Such a lamination procedure can. be
accom lished by applying neat and pressure.
In an embodiment, che method, further comprises forming the at least one top layer with an electrically insulating too layer directly covering the top surface of the insulated chip, and forming at least one vertical interconnect
structure vertically extending through the electrically insulating top layer and through the elsasf. r ical 1 y insulating layer for providing an electric connection with the at reasf one chip pad. The insulating top layer rn. combination with the one or more vertical interconnect structures may hence fulfill two functions, i.e. encapsulating the insulated chip and defining one on more eleetric paths of signals
propagating between an. interior and an exterior of the package .
In an embodiment, forming at least, one vertical
interconnect structure comprises forming, in. particular by laser drilling, at; least one common access hole extending through both the elec ric lly insulating nop layer and trie electrically insulating layer in a common procedure to thereby expose the at least one chip pad, and filling too at least one common access hole with electrically conductive materiel. This has significant advantages: On the one hand, two procedures may be combined into one. On the other hand, any potential registration problems between individual access holes for exposing chip pads and for defining vias are completely omi tied .
In an embodiment, the method comprises manufacturing a plurality of packages at least partially in a batch procedure as a consecutive/a connected/an integral structure being subsequently singularized into the individual packages or preforms thereof. In particular, the procedures of forming the insulated chip, of moun ing the insulated chip on rhe mounting base, and of forming the lateral ly surrounding structure may be performed efficiently for multiple packages in common or even on wafer level. After those procedures, the semifinished packages or preforms of packages may be
singularized and may be then further processed. For further processing, the individualized elements may be inserted into an integral structure comprising multiple annular surrounding structures, Subsequently, layer formation and lamination as well as access hole formation and material deposition for formation of the vertical interconnect structures may be again carried out as a batch.
In an embodiment, the method further comprises filling, in particular at least partially gaivauicaily, the at least one common access hole with electrically conductive material, in particular copper. This combines a safe electric contactabi 11 ty of the insulated chip with a high protection against uncles ireci creep current or disruptive discharqe and allows for a simple and quick processing.
In an embodiment, the method further comprises forming at least one electrically conductive' layer structure on the encapsulant and electrically coupled to the electrically conductive material. Such an electrically conductive layer may be attached by lamination or may be deposited by a deposition procedure (such as sputtering) .
In an embodiment, the package comprises a mounting base on which both the insulated chip and the further semiconductor chip are mounted separately from one another {in particular juxtaposed to one another with a gap in between on the mounting base) . Hence, insulated chip and further semiconductor chip may be connected to one another in a side-by-side archi ecture, for example electrically connected by one or more bond wires.
In an embodiment, the insulated chip and the further semiconductor chip are mounted on one another (i.e. may be vertically stacked on top of each other) . Hence, insulated chip and further semiconductor chip may be connected to one another in a chip-on-chip architecture, for example electrically connected via one or more bond wires.
The one or more electronic chips may be semiconductor chips, in particular dies. In an embodiment, the at least one electronic chip is configured as a power semiconductor chip, in particular comprising at least one of the group consisting of a diode, and a transistor, more particularly an insulated gate bipolar transistor. In an embodiment, the device is configured as a power module. For instance, the one or more electronic chips may be used as semiconductor chips for power applications for instance in the automotive field, In an embodiment, at least one electronic chip may comprise a logic IC or an electronic chip for RF power applications. In one embodiment, the electronic chip(s) may be used as one or more sensors or actuators in microelectrontechanical systems (MiMO; , for example as pressure sensors or acceleration sens o r3.
As substrate or wafer for the electronic chips, a semiconductor substrate, preferably a silicon substrate, may be usee. Alternatively, a silicon oxide or another insulator substrate may be provided. I is also possible to implement a germanium substrate or a II I-V-semiconductor material. For instance, exemplary embodiments may be implemented in GaN or SIC tecnnoiociy.
The above and other objects, features and advantages will become apparent from the following description and the a 0pended c 1 a 1ma , taken 1 n conj unc t ion wi t h t he accompany ί ng drawings, in which like parts or elements are denoted by like refe ence numbers .
Brief description of t hsp cIrawings The accompanying drawings, which are included to provide a further understanding of exemplary embodiments and constitute a part of the specific tion, il lustrate exemplary embodiments .
In the drawings :
Figure 1 shows a cross-sectional view of an insulated chip being hermetically sealed, mechanically and. electrically, by a direct coating of semiconductor and metallic surface material of the chip with an electrically insulating layer according to an exemplary embodiment.
Figure 2 shows a cross-sectional view of an insulated chip with exposed pads, wherein all semiconductor surfaces of the chip are hermetically surrounded by an electrically insulating layer exposing only the pads according to an exeiop ; a r y ernbod imen t .
Figure 3 shows a cross-sectional view oi a semifinished pac kage with s emi conducto r chips mounted s iolo-by-s ide according to an exemplary embodiment before encapsula t i on .
Figure 4 shows a cross-sectional view of a s emi f i ni shed package with semi co nduc t or chips mounted in a chip-on-chip arnnbteceure according to another exemplary embodiment before
Figure imgf000020_0001
Figure 5 to Figure 3 show structures obtained during carrying out a method of manufacturing a plurality of insulated chips in a batch architecture according to another eae:aρ 1a r y erobodiiten i .
Figure 10 shows a. semifinished package acce raiinp to an exemplary embodiment before exposing chip pads by removing material of an encapsulant and of a hermetically sealing e l ec t i ca l l y insulating layer in a common procedure.
Figure 11 shows the semifinished package of Figure 1.0 alter exposing chi pads by removing material of the encapsu ; ant. and of the electrically insulating layer in a common laser ablation procedure.
Figure 12 shows a cross-sectional view of a package according to an exemplary embodiment obtained by the manufacturing method according to. Figure !O and Figure .11.
Figure 13 shows a cross-sec a ions 1 view of a package providing a half bridge function according to an exemplary embodiment of the invention.
Figure 14 shows a cross-sectional view of a package according to yet another exemplary embodiment of the in ent. ion .
Figure 15 to Figure 26 show* structures obtained during carrying out a method of manufacturing a plurairty of packages in a batch architecture according to another exemp 1. a r y embodiment .
Detail d d jscrijDtion
The illustration in the drawing is schematically and not co sea ie .
before exemplary embodiment s v/i!". no described in more detai J. re ferring t a he f i gures , sone gene ra 1 aooc i de rat ions will be s mmarized bases on which exemplary embodiments have been developed.
According to an exemplary embodiment, an isolated chip {for instance covered with a pa ry Lose layer or any other ap ropri t ■dielect ic fairs/ may be implemented in a package or modmi 'V {such as a BLADE housing, i.e. laminated in a circuit board} . In an embodiment, the insulation layer and thereby rhe chip pads are opened only during opening of an upper passage layer ar ercapsuiaip (for instance by a laser procedure; . The completed package then comprises a circunnorentiaily fully isolated or hermetically insulated chip, with the only exception of the contact pad(s) .
Such an architect re allows for a defined and reliable insulation of chip and chip surfaces. This also protects the package from unciesired creep currents and voltage induced degradation along the interface chip-encapsulation {for instance plastic encapsulation) , in particular in the scenario of delarnination at this interface (for instance under the influence of moisture) .
According to an exemplary embodiment of the invention, this can be achieved by a full surface coverage of the semiconductor chip by the electrically insulating layer {in. particular from paryleae) , wherein an obtained insulating chip may be embedded wrthin a package {such as an embedding i r: a printed circuit: coard or in a BLADE package; . Advantageously, exposure of the contact cads of the chip to the encapsulant and the electrically insulating layer is accomplished in a single common procedure (for instance by laser ablation, m which the same laser beam peneirates firstdiy a part of she encapsoiant and Lheri the electrically insulating layer) .
The described architecture can be implemented in very different, package concepts, such as a BLADF. package iconpare Figure 11; to Figure 12), an embedded chip in a P.' , a chip embedded in a plastic encapsula ion, etc. Advantageously, opening of a package up to the chip pads can be accomplished by processes su:h as laser ablation. A parylene coated semiconductor chip can oe implemen ed in each standard package, for example in a s Ide-by-side configuration (see Figure 3) or in a stacked configuration (see Figure 4), with a voi e bond architecture (see Figure .14), with a clip a rch i rec sure , with a flip chap architecture, etc.
Wish such a packaging technology, it is for example possible to realize half bridge circuits in power electronics in which an electric isolation between neighbored chips, signal pads between neighbored chips (for instance with clips or wire bonds) is accomplished, while providing for a defined electric connection.
With the described concept, it is also possible to realize current sensors on tore basis of magnetic sensors. For this purpose, an electric isolation between the sensor chip and the electrically conductive trace carrying a current to be measured is advantageous■■
More generally, the described packaging technology is compatible with each package architecture in which at least one semiconductor chip shall be reliably isolated with regard to the en ironment (such as neighbored chips and/or traces and/or contacts ) ,
According to another exemplary embodiment of the invention, an insulated, chip as described above may be implemented advantageously in a chip embedding concept based on an inverse cavity formation architecture.
Conventional approaches of mounting semiconductor chips on a mounting base provide an annular structure delimiting a cavity on the mounting base, and mount the semiconductor chip subsequently in a respective cavity. Such a cavity has the function to compensate the chip neigh" or chip volume in order to avoid glass fibers or the like to come into contact with the chip edeje during mounting which could cause reliability issues. However, accurate manufacture of the cavid:y and a precise mounting of the chip on the mounting base ana in the cavity are both cumbersome and involve re 11 abill t y i s s ue s in te rms o f d i e a 1 a ch qu a 1 ί t y .
In contrast to this and to overcome: the mentioned shortcomings, die attach can be carried out according to an exemplary embodiment on a planar copper surface and before formation of the annular surrounding structure. The latter is only formed after mounting of the insulated chip and then, delimits a chip accommodation cavity without inaccuracies. This is more simple in terms of processing and apparatus effort, and is more efficiency, safer and cheaper, A gist of an exemplary embodiment rs to carry out die attach first and. to perform copper deposition for cavity formation thereafter, A cor esponding embodiment is shown in Figure 15 to Figure 26.
In order to prevent a semiconductor chip from electric, chemical and/or mechanical deterioration or damage and for passivatirrg and isolating the semiconductor chip from an electrolysis bath and other chemicals used, for forming the lateral surrounding structure, it can be covered for instance on five of six surfaces hereof with the dielectric and protecting insulating layer. For exam le, this can be accomplished nicer sawing and expanding on a sew foil, Preferably, the backside of the sendconduct or chip is protected by saw foil and will not be covered. On the backside of the chip, it is possible to provide a further solderable o sinterable backside {such as e multilayer arrangement with a silver structure) or a reservoir of diffusion solder mate rial (such as Au3n, SrcAg) .
A leadframe may be used as mounting base. Such a leadframe may be untreated and may have a surface of low and homogeneous roughness depth (for instance may be rolled with a maximum roughness depth of 400 mri) and nay be free of disturbing oxides (for e am l anti-tarnish layer, for instance benzo r r ra sole ) ana organic co minants. On this surface, die attach can be carried out. After the die attach, the chip is still protected on five of six surfaces by the insulating layer. The backside is electrically conductively connected fe the mounting base or leadframe by the die attach medium and is also protected. Afterwards, material deposition (in particular copper deposition) can be carried out until the chip is oi rcumferen t i a i 1 y completely embedded in the deposited material and remains only unencaosulated on its top. The protecting insulating layer prevents advantageously any undesired direct contact between the surface /sidewa lis of the semiconductor chip on the one hand and a chemical (such as a copper electrolyte} used during the deposition procedure on the other hand. Consequently, an efficient: protection against mechanical and chemical damage is provided. On the sidewalls it further functions as mechanical buffer between semiconductor material (such as silicon) and deposited copper. Since a gate pad and an emitter pad, for instance, are additionally isolated from one anther and protected by the protecting insulating layer, any electrosta ic discharge damage during and after copper deposition can be safely prevented ,
After the plat irig of the (already chip carrying) platelike >ilcr exanip.lv.-: copper) mounting base for the formation, of the laterally surrounding structure, the mounting base can be further processed and patterned for completing the packaging procedure. This may involve placing the formed arrangement into an annular surrounding structure in particular in a way to obtain a structure with a planar top surface to provide a proper basis for a subsequent lamination of one or more l v rs on one c r bor h oppos i ng ca ί n surfaces sf he arrangement. Highly advantageously, she dielectric protection layer surrounding a major surfsee portion of the semiconductor chip may be configured so that a laser beam used for drilling access holes in one or more of the lamination layers tor laser via forrnac. ion can also loc ll remove part of the protecting ins l ting layer together with material of the laminate layer ,s) thereon. Thus, there is subs an ially no additional effort for exposing the chip pads ot the insulated chip. A particularly appropriate material, for the mentioned purpose is parylene. As an alternative to oarylene, it is possible to use another dielectric material which can be properly deposited, sas a high disruptive strength and robustness against diffusion.
Advantages of the described embodiment are a robust processing during die attach and the oossiorlity to use well- known procedures for package formation, Furthermore, fine process is significantly more tolerant with regard to inaccuracies and tolerances of the plated copper layer thickness (the chip edges are protected by the protecting insulating layer) . Furthermore, the chip surface is protected during a roughing procedure of the mount ng base (such us a leadf ramie ) , which roughening procedure is advantageous for improving adhesion of the laminate. This allows the use of a thinner copper layer on the front side, which reduces costs and increases compactness.
As an alternative to copper, i *: is also possible to use cooper alloys or a different material [s c as nickel, iron, aluminum, etc.) for deposition. Apart from the described copper plate as mounting base, it is also possible to use order materials (such as metallic sheets like coated molybdenum, laminates, etc.}, in particular as a basis for a subsequent plating procedure.
According to an exemplary embodiment of the invention, a protection layer is deposited on surfaces {for instance on five of six sides) ct an semiconductor chip for preventing the latter with regard to mechanical and in particular chemical damage. The material of this protection layer can be configured to be pat ernable by a laser. Advantageously, the protection layer may be used as a barrier and buffer around a chip in order t.o embed the latter after she mounting on a carrier circumferentialiy with a plated layer (for instance functioning similar as a quasi-plating resist) . Such features may be implemented, in a procedure described below in detail referring to Figure 15 to Figure 26.
Figure 1 shows a cross-sectional view of an electrically hermetically sealed insulated ship 100 being hermetically surrounded by an electrically insulating layer 104 according to an. exemplary embodiment.
The insulated chip 100 comprises a. semiconductor chip 102 , for instance a power semiconductor chip comprising a transistor or a diode for a ha l f bridge. The semiconductor chip 102 is a naked, unpackaged semiconductor chip consisting of a silicon body having an integrated circuit therein and naving chip pads 1 6. The s mi conduc a r chip 1 02 aa a be direaaiy obtained from singuiating (for instance sawing) a processed semiconductor wafer. An electrically insulating layer 104, embed L d as a ccwrf orm.ally deposited thin film of dielectric material sach as paryiene, -son 1 nuously and fully cir oam.ferentiai i.y coats the entire surrounding surface of the semiconductor chrp 102 with homogenous thickness and without interruption. In other words, an entire exterior surface of the semiconductor chip 102, including the pads 106, is covered with the electrically "insulating layer 104. Thus, a flow of electricity between an exterior and an interior of the insulated chip 100 is disabled by the dielectric shell or wall hermetical ly sealing the semiconda rror chip 101 with reward to an electronic periphery.
Hence, the insulated chrp 100 has an external surface which is continuously covered with a continuous uniform film of the electrically insulating layer lul. Preferably, the thru fri of rne electrically insulating polymer is deposited on the unpackaaod semiconductor chip 100 equipped with the pads 106 by Chemical Vapor Deposition (CV0P ., Hence, Figure 1 shows a semiconductor die completely covered with an isolation layer, preferably paryiene.
The insulated chip 100 can be embedded in an encapaulant, and an access hole can be formed through the encapsulant and the electrically insulating layer 104 in a common procedure {see Figure 11) to thereby open the lectrically insulating layer 104 selectively at and limited to the positions of the chip pads 106.
The insulated chip 100 shown in Figure 1 can be used in particular also for the following processing path: The fully insulated, chip 100 according to Figure 1 can be mounted on a chip carrier (for instance by die bonding) . Only directly before forming access contacts to the insulated chip .100 (tor ir.st.ance by wire bonding or clip bonding) ihe electric contact peas 106 of the insulated chip ] 00 ice opened by selectively removing material of the electrically insulating layer 104 covering the pads 106 (tor instance by laser ablation) .
Figure 2 sheae a cross -sect iona 1 view ot an insula ed chip 100 according to an exemplary embodiment with exposed pads 106, The entire semiconductor surface of semiconductor chip 102 is hermetically covered by electricall insulating layer lOi. in other words, the entire exterior surface of the insulated chip 100 is formed by the electrically insulating layer 104, wherein the pads 106 form the only exception by also contributing to the exterior surface of the insulated c ip 100.
Hence, the difference between the insulated chip 100 according to Figure 0 ant care insulated chip 100 according to Fi ure 1 is that, according to Figure 0, access holes 200 are formed by laser ablation (see reference numeral 202) to remove material of the electrically insulating layer 104 selectively at the positions of the cnip pads 106, In other words, the electrically insulating layer 104 is interrupted only at the. positions of the chip pads 100 while fully covering trie entire semiconductor surface of the soma., conductor chip 102, Thus, a surrounding surface of the semi conductor chip 1.02 excluding only the surface portions defined by the pads 106 is covered with the electrically insulating layer 104, Therefore, Figure 2 shows a semiconductor die covered with an isolation layer, but having contacts opened {for instance by laser ablation) so that the insulated chip 100 according to Figure 2 can be directly further processed, by wire bonding I see Figure 3 and Figure 4) . In the confi guru'., ion of Figure 3, the electric contact pads 106 of rhe insulated chip iaO have been opened (for instance by laser ablation, plasma oioressing, er chemically] so that he insulated chip 100 according to Figure 2 can be used as a basis for very different mounting procedures such as wir- bending (compare Figure 3, Figure i or Figure 14), flip chip processing, clip processing, etc. the insulated chip 101 recording to Figure 2 can oe implemented in many different packaging architectures, such as EGA (Ball Grid Array) , Cod (Quad Fiat do Leads Package) , QF? (Quad Flat Package., Sol (Small Outline Transistor;, etc. The rnsulateei chip lee tea form the basis of a single chip package or a mubttchdp package, Exemplary embodiments of the ian/ention may also be implemented in terms of ISOFACE technology (in particula to provide galvanic isolated high side switches and repat ntegrat d circuits) .
Figure 3 shows a cross-sectional view of a semifinished package with semiconductor chips 1C2, 300 mounted side-by- side according to an exemplary embodiment before encaps a 1 ati on .
The soma finished (since not yet encapsula ed; package shown in Figure 3 comprises the insulated chip IOC according to Figure 2, a further semiconductor chip 300 (in the shown embodiment naked die without electrically insulating layer 104) , and band wires 300 electrically connecting an exposed pad 10 o of the in s 1.hi a fed ch 1p 100 ith a pa d 106 of t ite further semiconductor chip 102. Figure 3 furthermore shows that further pads 106 of the insulated chip 100 and of the further send.conduct.or chip 300 car: oe connected by further bond wires 302 to an electronic environment (neb shown) .
The semifinished package according to Figure 3 additionally comprises a mounting base 304 (i.e. any substrate or chip carrier, for example a leaoframe or an organic substrate) on which both the insulated chip 100 and trie further semiconductor chip too a e mounted in a side-by- side arcnit.ectu.re with wircbond inte connection.
To obtain a package according to an exemplary embodiment based on the s mifinished package according to Figure 3, the semifinished package can be encapsulated (for embedding insulated chip 100 and further semiconductor chip 300), for instance by lamir.at.ion cos shown in Figure 13) or by molding ;as shown in Figure 14) . After encapsulation, the electrically insulating layer 104 provides for a reliable electric decoupling between the insulated chip 100 and the r urt he r s raicond uc tor cin 1p 300.
Figure 4 shows a cross-sectional view of a semifinished package with semiconductor chips 102, 300 mounted in a chip- cn-cnop architecture according to another exemplary embodiment before encapsulation.
In contrast to Figure 3, the embodiment of Figure 4 shows a configurate on in which the further semiconoiuct or chip 300 is mounted on the mounting base 304, and the insulated chip 100 is mounted, in turn, on the further semiconductor chip 102. The electrically insulating layer 104 provides for a reliable electric decoupling between the directly connected arrangement of the insulated chip 100 and the further semiconductor chip 300 in the shown stacked die configuration.
To obtain a package according to an exemplary embodiment foaseci on the semifinished package according to Figure 4, the semifinished package can be encapsulated (for embedding insulated chip 100 and further semiconductor chip 300), for instance by lamination (as shown in Figure 13) or by molding {as shown in Figure 1.4) . After encapsulation, the (electricall insulating layer 104 pro ides for a reliable el ctric d oupling between the insulated chi 100 and he further semiconductor chip 300,
Figure 5 to Figure 9 show structures obtained during carrying our a method of manufacturing a plurality of insulated chips 100 in a batch rchitecture according to another exemplary embodiment. The goal of the described me hod is to simultaneously manufacture a plurality of insulated ehrps 100 according to Figure 1.
In order ro obtain a structure 020 shown in Figure 5, a plurality of naked semiconductor chips 102 is mounted or placed on. an auxiliary carrier 500. Thus, the semiconductor chrps 102 are mounted, after dicing from a semiconductor watery on the auxiliary carrier 000 which ·:οί.η be a dicing foil .
In order Co obtain a structure 620 shown in Figure 6, a first pan. of the e I.cctr ically insulating material, which later forms part of the electrically insulating layer 104, is deposited on an exposed part of the surface of all mounted semiconductor chips 1.00 simultaneously. This deposition procedure can be accomplished by a CVD process by which electrically insulating material such as parylene is deposited from the gas phase on exposed, surfaces of the semiconductor chips 102 and of the auxiliary carrier 500.
In. order to obtain a structure 720 shown in Figure 7, the structure 62.0 is slipped or pivoted by ls0°, to thereby attach {according to Figure 6 upper) surfaces of the semiconductor chips 100 already covered with the electrically insuiatina material on a further auxiliary carrier 700. This procedure can be denoted as a re-lamination. In other word, surface portions of the semiconductor chips 102 covered with the previously deposited electrically insulating material are mounted on the further auxiliary carries 700. Thus, a flipping of the dice is performed for re- laminar ion onto the further auxiliary carrier 700 (for instance a foil or any other carrier) in order to prepare the structure "'20 for subsequent hacks i do coating. After oho descr b d att chment, the auxi liary carrier too is removed from the seer ί conductor chips 102, to thereb expose the 'according to Figure 7 upper) surface portions of the semiconductor chips 102 which have preciously been covered by the auxiliary carrier 500.
Tn order to oboe lit a structure 82 0 shown i n Figure 8 , a second part of too electrically nsulating material, later forming the electrically insulating Sayer 104, is deposited on a now exposed part of the surface of the mounted, semiconductor chips L 02 which has been covered by the auxiliary carrier oOo during deposit beg the firsr part of the elect ically insulating mate i l. hence, coot i eg of the backside of the semiconductor chips 102 is carried out, so that, finally the whole surface of the semiconductor chips 102 (including pads iOb5 is encapsulated with a layer type electrically insulating layer 1.04.
In order to obtain the batch of hermetically sealrngiy insulated chips 100 shewn in Figure 9, the further auxiliary carrier 200 is detached or removed from the insulated chips 100. Thus, the described method is carried out simultaneously with the plurality of semiconductor chips 1 0 2 , thereby producing a large number of semiconductor chips : ' 02 in a quick and simple procedure carried ore: on wafer level after singularization (for instance sawing) .
Modifications of the process flow described referring to Figure 5 to Figure 9 are of course possible. For instance, it is possible to start the deposition on the backside of the semiconductor chips 1 02 , or to carry out a part of the deposition (for instance on one surface and side surfaces) ithout re 1 ami na t ion . Figure 10 shows a semifinished pa-? kage a esiuotioig to as exemplary embodim nt. before expos ir.q chip pads .'06 (by removinq material of r. en.capsula.nt 1000 and of electrically insulating layer 104 in a common procedure) .
For manufacturing the semifinished package according to Figure 1 , cne insula tea chip 100 ( or instance reecasfaotured according to Figure t to Figure 0) is encapsulated by an encapsuiaitt 1000. In the shown eiabodimen t , the eocapsulant 1000 is a laminate composed of a mounting base 1002 (on which a bottom af the insulated chip 100 is mounted) and of a cover 1004 (covering a op: cf the insulated chip 100; , she mounting base 1000 can be made of an electrically conduce! ve material (for instance a copper sheet, for example having a thickness of about 200 gmb . The cover 1004 can be made of an electrically insulating material (lar instance a cropreg foil tilth or without pure fcanned cavity tot acc.ommodar.ing the insulated chip 100) . One insulated ship 100 may be mounted on the mounting base 1002, for instance by gluing or soldering, The semiconductor chip 102 may have a (according to Figure 10 vertical.! thickness in a range between 30 gin ami 20.) pm, for instance 60 usu The mounting base 1000, the insulated chip 100 and the cover 1001 can be connected to one another by lamination, i.e. by pressing them together supported by heat.
Therefore, the insulated chip 100 can be embedded into a iaminat- ofcr instance m terms cf a FOB process or a BLADE process ; .
Figure 11. shows the semifinished package of Figure 10 after exposing chip pads 106 by removing material of encapsuiant 1.000 and of electrically insulating layer 104 in a common procedure.
Thus, common access holes 1100 are formed by laser ablation (see reference numeral 1110) to extend through both the encapsuiant 1000 and the electrically insulating layer 104. In o i l i r words, the access holes 1100 are formed in a common procedure to thereby expose the chip pads 106, Highly advantageously, opening of encapsulant 1000 and electrically insulating layer 104 is accomplished in the same process, here with she same laser bean. This corr.bir.es a highly reliable electric insulation of she se iuuonciuotor chip lot with a simple and quick accessibility of the chip pads 106.
Figure 12 shows a cross-sectional view of a package 1200 according to an exemplary embodiment obtained by the manufacturing method according to Figure 10 and figure 11.
In order to obtain the package 1200 based on the semifinished package of figure 11, the common access holes 1100 are filled 'for instance using a galvanic process) with electrically conductive material to thereby manufacture vias 1202 contacting the pads 100 in the access holes 1100. Furthermore, a patterned electrically conductive layer 1204 (such as a patterned copper foil) is formed as a surface wiring on fin? {on the surface dielectric) encapsulant 1000 and electrically counted to the electrically conductive material forming the oias 1202. The, via tilling and formation of conductor fines compietes the m ufacturing procedure of the package 1200.
In the configuration according to Figure 12, the electrically insulating layer 104 is arranged for electrically insulating the semiconductor chip 102 from one or more possible further semiconductor chips (not shown) of the package 1200, electrically conductive layer 1204, and one or more possible electrically conductive contacts (not shown) of the package 1200. This ensures a. reliable electric decoupling of the semiconductor chip 102 from the electronic periphery and therefore an efficient protection against creep currents and disruptive discharge. This is particularly advantageous when the package 1200 is configured for high current or high v .i ge applications such as a current censor application based on magnetic sensing, a hail bridge ap lication, etc.
In terms of a BLADE process, the full-layer-encapsul ted insulated chip 10c can be adhered onto the electrically conductive mounting base 1002 (such as a lead frame or a printed circuit board) and can be laminated with the cover 1004 (such as printed circuit board material} . By laser processing, contacts in form of the access holes 1110 are shot info the encapsalant 1000 to thereby expose the chip pads 106. The access holes 1110 can be galvanicaily filled with electrically conductive material such as copper.
A highly advantageous effect of such an embodiment is that tnrs access hole formation procedure simultaneously removes material of the encapsulant 1000 ana the electrically insulating layer 104, in particular exclusively and exactly at the positions required for obtaining access to the chip pads 100. The resulting package 1200 then comprises the fully embedded semiconductor chip 102 which, apart from its chip pads 106, is completely electrically insulated with regard to the envi ronment ,
Further advantageously, the access hole formation as a basis for the upper chip metallization can be preferably carried out so that the laser automatically stops on the metallization (i.e. the chip pads 106) after forming the openings in the electrically insulating material of the electrically insulating layer 104 and the cover 1004. For this purpose, copper as material for the chip pads 106 is h i gh 1 y approp ria te .
Figure 13 shows a cross-sectional view of a package 1200 according to another exemplary embodiment of the invention.
The package 1200 provides an electronic half bridge function. In this embodiment, the insulated chip 100 and a conventional naked semiconductor chip 300 are both embedded in the encapsulant 1000, For example, the insulated chip 100 may be glued to the mounting base 1002, whe rea s the semiconductor chip 300 may be assembled on the rn.ounti.ng base 1002 using an electrically conductive interconnect 1300, The mounting base 1002 may for instance be a base substrate such as a metal foil or sheet. The mounting base 1002 may also be a current carrying rail in the case of a current sensor based on magnetic field sensing. A ground contact is denoted with reference numeral 1302 in Figure 13. A detail 1350 of Figure 13 shows an enlarged view of the surrounding of the insulated chip 100. As can be taken from detail 1350, a safe creepage distance, 1, is achieved, even if the cover 1004 delaminates from the electrically insulating layer 104. A save isolation distance, d, is defined by the thickness (for instance 10 grid of the electrically insulating layer 104.
A l t h ough not shown in che figures, a top surface ot the package 1200 according to Figure 13 can be mounted on a printed circuit board (PCBJ, for instance via solder balls (not shown) .
A possible current flow path during operation of the package 1200 according to Figure 13 is indicated with reference numeral 1390 and extends from the electrically conductive layer 1204 at the top surface, through one of the vias 1202, along the electrically conductive mounting base 1002, via the conductive interconnect 1300, through the further semiconductor chip 300, through another one of the vias 1202, and. back to another portion of the electrically conductive layer 1204 at the top surface. Thus, the electrically conductive mounting base 1002 may contribute to the current flow and may simultaneously function as a heat sink for removing heat generated by the chips 100, 300 during operation of the package 1200. Figure 14 shows a cross-sectional view of a package 1200 according to yet another exemplary embodiment of the invention. The package J 200 shows an example of a ire bond arch ecture by which the insulated chip 100 according to Figure 0' is embedded in a mold compound as encapsulant 1,000, According to Figure 14, the package 1200 further comprises a chip carreer 1400 embodied as a leadiraaie which carries the insulated chip 100. One insulated chip 100 is mounted en the chip carrier 1400 by an adhesive material 1402. Bond wires 302 are provided for electrically connecting a. respective one of the chip pads 106 with a respective lead of the chip carrier 1400.
line described arranqement Is then inserted beeween a lower mo d die and an upper mold die Ore': shown: . Liquid mold material is introduced into the chamber defined between the lower mold die and the upper mold die and is solidified. Consequently, encapsulant 1000 is obtained in the form of a moid compound encapsulating the insulated chip 100, the bond wire 002, and part of the chip carrier 1400.
In one configuration, the package 1200 according to
Figure 14 has leads of the lead frame 1400 on the left-hand, side and on the right-hand side of the package 1200 which are in flesh with sidewalis of the encapsulant 1000. Such a configuration can be im lemented in accordance with Q 100 {Quae Flat ho head) packaging technology.
In another configuration, the package 1200 according to Figure 14 has leads of the lead frame 1100 on the left-hand side and on the right-hand side of the package 1200 which laterally extend beyond sidewalis of the encapsulant 1000, thereby forming free terminals oi gull-wing shape shown as dotted lines according to Figure 14. Such a. configuration can be implemented in accordance with 00 {Small Outline) or QFP packaging technology . Figure 15 to Figure 26 show structures obtained durinq od.rryir;q out a method of man fac uring a plurality f packages 1200 in a baton architecture according to another exemplary embodiment oL the invention.
The structure sr.own in Figure 15 is a processed semiconductor wafer 1000 comprising a plurality ol semiconduc or chips 100 with integra ed circuit elements (such as SFETs or IGBTs, not shown) .
In order to obtain a structure shown in Figure 16, the semiconductor wafer 1000 is thinned and sawn on a saw frame (see reference numeral 1600) . As can be taker: from a detail 1610, the semiconductor wafer 150;) comprises a plurality of semiconductor chips 100 arranged in rows and columns.
In order to obtain a structure shown in Figure 17, the semiconductor wafer 1500 as shown in Figure 10 is made subtest co a coating procedure for forming trie electrically insulating layer 3.0Ί on all exposed surfaces of all semiconductor chips (,02. Thereby, a dielectric coated semiconductor wafer 1700 is obtained.
In order to enable coatina material to be deposited reliably on the entire upper main so; r face and the four vertical side surfaces of the sawn semiconductor chips 102 still being attached with their lower main surfaces on a flexible foil, the sawn semiconductor wafer 1000 can be expanded during the coating procedure. This can bo accomplished by correspondingly bending the flexible foil ro increase the spacing between adjacent semiconductor chips 102 during the coating procedure. This may prevent undesired shading effects and may therefore reduce the risk of incompl e; coating of the five mentioned surfaces of the semiconductor chips 102 to be coated. Subsequently, the individual 1 formed insulating chips 00 e released from the fi.exi.ble foil and are i ureter processes; as shown in she following figures.
In order to obtain a structure shown in Figure 18, a. mounting base 1002 provided, such as a planar or rolled copper s hee ι or a lead i raine ,
.In order to obr ain a structure shown in Figure 1.9, the insulated chip 100, as obtained according to Figure 17, is mounted directly on the planar mounting base 1002. In view of the pla rarity of the mounting base 1002, this is a very simple procedure, In other words, the mauntires base 1002 is advantageous i.y initially free of any cavities which are only formed, thereafter by an additive process (compare Figure 21) , This has she significant advantage that the remarkable effort for manufacturing cavities with high reliability by a subtraotrve piuscedare (in particular Involving lithography! can be cm.in ted.
Still referring so a Figure 19, five substantially rectangular surfaces of the substantially cuboid semiconductor chip 102 are fully covered with the electrically Insulating layer Ifi . Only a sixen substantially rectangular surface of the semiconductor chip 102, more specifically arranged as the bottom surface according to Figure 19, is free of the electrically insulating 'layer 1.04. In confucjst to this, it may be exposed or may bo covered with a saw frame foil or with an electricall conductive coupling structure .
Bonding the semiconductor chip 102 to the mounting base 1002 may be accomplished for example by soldering (for instance by soft soldering or Gold-Tin soldering) or by sintering .
In. order to obtain, a structure shown, in Figure 20, the upper ana lower main surfaces of the mounting base 1.002, preferably made of copper, may be roughened in preparation of a subsequent galvanic deposition procedure (see ro uqh surfaces 2000, as shown in details 2010, 2020, More generally, the exposed surface of the mounting base 1002 can be preconditioned for subsequent plating.. Such a preconditioning may be the shown roughening procedure, or may additionally or alternatively involve cleaning of the surface ,
In order to obtain a structure shown in Figure 21, only after completion of the mounting procedure, a lateral surrounding structure 2100 made of the same material (here copper) as the mounting base 1002 is formed. As a consequence of the presence of the already mounted insulated chip 100 on the moun t i ng base 1,002, a cavity is delimited i n which the insulated chip 100 is laterally embedded. As can be taken from Figure 21, the lateral surrounding s t ruc t u re 2100 is vertical i n flush (i .e. at the s ame h e i ght level and forming a common planar surface) with the i n s u l a t e d chip 100, Highly advantageously, forming the lateral surrounding structure 2100 on the mounting base 1002 is accomplished by an additive procedure in form of galvanicaily plating. Simultaneously with the formation of the lateral surrounding structure 2100, the galvanic plating procedure also forms a counter structure 2102 on a main surface of the mounting base 1002 opposing a further main surface of the mo u n t i ng base 1002 on which the lateral surrounding structure 2100 is arranged. Thus, a double-sided galvanic coating of the mounting base 1002 (here embodied as copper sheet) is carried, out (copper plating) . A vertical thickness, d, of each of the structures 2100, 2.102 can be for example 150 um . The structures 2100, 2102 can be formed by immersing the structure shown in. Figure 20 in a galvanic bath and by applying current. During this and other p roced ur e s , t he e 1ect, ri ca.11 y i nsu1at i ng 1a ye r 10 o f pa ry1ene protects the semiconductor chip 102 with regard to the environment, from a mechanical and chemical point of view. The silicon material of the send conductor chip 102 shall not c me into direct contact with tne galvanic chemistry as vac 11 an with copper m terial, because this might destroy he semiconductor chip 102, Then, the parylene material of the electrically insulating layer 104 also serves as a powerful passivation of the semiconductor chip 102 with regard to harsh conditions in the environment.
Figure 22, shows a three-dimension l view of an arrangeme t of multiple components, one of which being shown in Figure 21, connected via a bar and web structure 2200. Thus, the manufacturing procedure can be carried out as a batch. For s i regularising the individual components, it is sufficient 'on break the webs 2202, for example by punching.
In order to obtain a structure shown rn Figure 23, the arrangement of Figure 22 is siryularized into a plurality of semifinished packages 2300, for instance by punching.
In order to obtain a structure shown in Figure 24, the lateral surrounding structure 2100 and the insulated chip 100 en the mounting base 1002 are, i.e. a s mifinished package 2000 as sunown in Figure 20 2s, inserted info a late ally surrounding annular structure 2400 {for instance made of E'fol material which may comprise cured resin and glass fibers) being vertically in flush with the lateral surrounding structure 210e and with the insulated chip 100. In other words, the singalariced semifinished paceacnes 2300 are inserted into cavities of a frame s reet ere. With a thickness, 0, of for instance 1.2 mm, the structure according to Figure 24 is highly compact. The annular structure 2400 may be a printed circuit board with punched, through holes in which the semifinished, packages .2300 may be inserted in a batch manufac uring procedure. In order to obtain a structure shown in Figure 25 , two top layers 25-00, 2502 are arranged as planar sheets or foils on a too surface of the insulated chip 100 and tho laterally scr round inc; structure 0100 and the Lateral su ounding annular structure 2400, Correspondingly, two oof torn layers 2504, 2506 are arranged as pJanar sheets or foils on a bottom surface of the counter structure 2102 and the lateral surrounding annular structure 2400, For connection, the elements of the so obtained sandwich or layer: stack are ocnno otoo o one a no the r by 1 ami nat r on by app 1 y i ng mechani ca 1 pressure and thermal energy. Layers 0500, 2504 are electrically insulating, whereas layers 2502, 2506 are electrically conductive (for instance are made of copper) . The procedure described referring to Figure 25 results in an encapsul as i an of the semifinished package 2200 by lamina ion, layers 2a00, 2504 may be resin-rich piepreg layer, i.e. uncured resin with glass fibers therein. curing the lamination, part of the resin flows into lateral recesses 2450 (compare Figure 24} between the semifinished package 2300 and the annular structure 2400 and therefore fills empty ga s .
In or ier to obtain package 1200 shown in Figure 26 , vertical interconnect structures 2600 art formed in a top portion of the structure shown in Figure 25 vertically extending through the electrically insulating top layer 2500 and through the electricaLiy insulating layer 104 for providing an electric connection with the chip pads 106. More specifically, forming the vertieal interconnect structures 2600 comprises laser drilling common access holes {see reference numeral 1100 in Figure 11) extending through both the electrically insulating top layer 2500 and the electrically insulating layer 104 in a common procedure to thereby expose the chip pads 106. Thus, the electrically insulating layer 104 is advantageously made of a material being removable by laser drilling, such as parylene. Subsequently, the common access holes are filled with electrically conductive material such as copper. Figure 26 shows that the semiconductor chip 102 is electrically contacted via correspondingly formed laser vias.
As a result of the manufacturing procedure described referring to Figure 15 to Figure 26, the package 1200 shown in Figure 26 according to an exemplary embodiment of the inven ion is obtained. The package 1200 comprises the above described insulated chip 100 and an encapsulant 1000 encapsulating the insulated chip 100. When the package 1200 shown in Figure 26 is manufactured in a batch procedure with .multiple other packages 1200 (for instance when using a printed circuit board with punched through holes as annular structure 2400, wherein the semifinished packages 2300 are inserted in these through holes}, such a structure first needs to be singularized into the individual packages 1200, for instance by sawing.
A cover 1004 of the encapsulated 1000 comprises the lateral surrounding structure 2100 consisting of copper which delimits the cavity in which the insulated chip 100 is embedded vertical in flush with the insulated chip 100. The cover 1004 also comprises the two described top layers 2500, 2502 covering the top surface of the insulated chip 100. The two top layers 2500, 2502 additionally cover a top surface of the lateral surrounding structure 2100. The two top layers 2500, 2502 comprise the lower electrically insulating top layer 2500 directly covering the top surface of the insulated chip 100 and being penetrated by the vertical interconnect structures 2600 providing for an electric connection with the chip pads 106. Moreover, the two top layers 2500, 2502 compri se upper electr ica 11 y cond.uct ive 1 a yer 2502 di rec11.y covering the lower layer 2500' and being connected to the vertical interconnect structures 2600, The lateral surrounding structure 2100 is made of an electrically conductive material such as copper and is laterally surrounded by the electrically insulating annular structure 2400 being in flush with the lateral surrounding structure 2100.
it should be noted that the term "comprising" does not exclude other elements or features and the "a" or "an" does not exclude a plurality. Also elements described in association with different embodiments may be combined. It should also be noted that reference signs shall not be construed as limiting the scope of the claims. Moreover, the scope of the present application is not intended to be limited to the particular embodiments of the process, machine, manufacture, composition of matter, means, methods and steps described in the specification. Accordingly, the appended claims are intended to include within their scope such processes, machines, manufacture, compositions of matter, means, methods, or steps.

Claims

1, An Insulated chip (100), comprising:
• a semiconductor chip (.102) comprising at least one chip pad (106) ;
• an electrically insulating layer (104) surrounding at least part of the semiconductor chip (102) .
2, The chip (100) according to claim 1, wherein an entire surrounding surface of the semiconductor chip (102) and the at least one pad (106) is covered with the electrically insulating layer (104) ,
3, The chip (100) according to claim 1, wherein a surrounding surface of the semiconductor chip (102) excluding only at leas one surface portion around the at least one pad (106) is covered, with the electrically insulating layer (104) .
4, The chip (100) according to claim 1, wherein five side surfaces of the semiconductor chip (102) are covered with the electrically insulating layer (104), and a sixth side surface of the semiconductor chip (102) is free of the electrically insulating layer (104) . 5. The chip (1.00) according to any of claims 1 to 4, wherein the electrically insulating layer (104) is made of a polymer material, in particular parylene,
6. The chip (100) according to any of c la ims 1 to 5, wherein the electrically insulating layer (104) is made of a material being removable by laser drilling.
7, A method of manufacturing an. insulated chip (100), the '15
method comprising:
• providing a semiconductor chip (102) comprising at least one chip pad (106);
• surrounding at least part of the semiconductor chip
(102) with an electrically insulating layer (104) .
8, The method according to claim 1, wherein the surrounding compri ses :
• placing the semiconductor chip (102) on an auxiliary carrier ( 500 } , and;
• depositing a first part of electrically insulating
material of the electrically insulating layer (104) on an exposed surface of the semiconductor chip (102) placed on the auxiliary carrier (500) .
9, The method according to claim 8, wherein the surrounding further comprises:
• placing a surface portion of the semiconductor chip
(102) covered with the deposited electrically insulating material on a further auxiliary carrier (700);
• removing the auxiliary carrier (500); and
• depositing a second part of the electrically insulating material of the electrically insulating layer {104} on an exposed surface of the semiconductor chip (102) placed on the further auxiliary carrier (700), which surface had been covered, by the auxiliary carrier (500) during depositing the first part of the electrically insulating material,
10, The method according to any of claims 7 to 9, wherein the method is carried out simultaneously with a plurality of semiconductor chips (102) .
11. A package (1200), comprising:
• an insulated chip (100) according to any of claims 1 to 6;
• an encapsulant (1000) encapsulating at least part of the insulated chip (100) .
12. The package (1200) according to claim 11, comprising at least one electrically conductive vda (1202) electrically coupled to the at least one chip pad (106), wherein each of the at least one via (1202) extends through a respective common access hole (1100) extending through both the
encapsulant (1,000) and the electrically insulating layer (104 ) .
13. The package (1200) according to claim 11 or 12, wherein the encapsulant (1000) comprises a. laminate, in particular printed circuit board laminate.
14, The package (1200) according to claim 11 or 12, whe the encapsulant (1000) comprises a mold, in particular lastic mold.
15. The package (1200) according to any of claims 11 to 14, wherein the encapsulant (1000) comprises a mounting base (1002) on which a bottom of the insulated chip (100) is mounted and comprises a cover (1004) covering a top of the insulated chip (100) .
]6, The package (1200) according to claim 15, wherein the cover (1004) comprises a lateral surrounding structure
(2100) , in particular made at least partially of electrically conductive material, delimiting a cavity in which the insulated chip (100) is embedded, in particular vertical in flush with the insulated chip (100)
17, The package (1200) according to claim 15 or 16, wherein the cover (1004) comprises at. least one top layer {2500, 2502) covering a top surface of the insulated chip (100) ,
18, The package (1200) according to claims 16 arid 17, wherein the at least one top layer (2500, 2502) additionally covers a top surface of the lateral surrounding structure (2100) .
19, The package (1200} according to claim 17 or 18, wherein the at least one top layer (2500, 2502} comprises a lower electrically insulating top layer (2500) directly covering the top surface of the insulated chip (100) and being penetrated by at least one vertical interconnect structure
·: 26001 providing an electric connection with the at least one en ip pad (106) ,
20, The package (1200) according to claim 19, wherein the at least one top layer (2500, 2502) comprises an upper
electrically conductive layer (2500} directly covering the lower layer (2500) and being connected to the at least one vertical interconnect structure (2600) , 21, The package (1200) according to any of claims 15 to 20, wherein a surface of the insulated chip (100) being directly arranged on the mounting base (1002) is at least one of the group consisting of:
• free of the electrically insulating layer (104); and · electrically coupled to the mounting base (1002) ,
22, The package (1200) according to any of claims 16 to 21, wherein the lateral surrounding structure (2100) is laterally surrounded by an, in particular electrically insulating, annular structure (2400), in particular an annular structure (2400) being if; flush with the lateral surrounding structure (2100) .
23. The package (1200) according to any of claims 16 to 22, comprising a counter structure (2102) on a main surface of the mounting case (1002) opposing a further main surface of the mourn i no base (1002) on which the lateral su ounding structure ( 100) is arranged.
24. The package (1200) according to any of elarara 17 to 23, comprising at least one bottom layer (2504, 2506)
constituting a ma i n surface of the package (1200' opposing a further r.a ir, surface of the package (1200} constituted by the at least one top layer (2500, 2502) .
25. A method of manufacturing a package (1200), the method comprising :
« manufacturing an insulated chip (100) by a method
according so any of claims 7 to 10;
• encapsul ting at least part cf the insulated chip (100! by an encapsulant (1000; .
26. The method according to claim 25, wherein the method further comprises forming at least one common access hole (1100) extending through both the encapsulant (1000) and the electrically insinuating layer (104) in a common procedure to thereby expose the at least one chip pad (106; .
27. The method according to claim 26, wherein the method further comprises filling, in particular gal vanicaliy, the at least one common access ho i e (1100) with electrically conduc t ί ve materi l,
28, The method according to claim 26 or 27, wherein the forming of the at least one common access hole (1100) comprises at least one of the group consisting of laser ablation, plasma processing, and chemically processing.
29. The method according to any of claims 25 to 28, wherein the method comprises mounting the insulated chip (100) on a mounting base (1002), in particular on a planar mounting base (10021, more particularly on a mounting base (1002) being initially free of cavities at a mounting position of the insulated chip (100) . 00. The method according to claim 29, wherein the method comprises, after the mounting, forming a lateral surrounding structure (2100), in particular made of the same material as the mounting base (1002), delimiting a cavity in which the insulated chip (100) is embedded, in particular vertical in flush with the insulated chip {100) .
31. The method according to claim 30, wherein forming the lateral surrounding structure (2100) on the mounting base (1002) is accomplished by a material adding procedure, in particular by a galvanic plating procedure.
32. The method according to claim 30 or 31, wherein the method, further comprises inserting the lateral surrounding structure (2100) and the insulated chip (100) on the mounting base (1002) into a laterally surrounding annular structure { 2400 ) , in pa rt i cu .1 nnu1 a r st ructure (2400 ) be ing in flush with the lateral surrounding structure (2100) and the insu1a ted ch1p ( 100 } . 33, The method according to claim 31 or 32, wherein the method further comprises connecting at least one top layer (2500, 2502} to a top surface of the insulated chip (100 J an the laterally surrounding structure (2100), in particular by laminating ,
34, The marthod according to claim 33, wherein the method further comprises
• forming the at least one top layer (2500, 2502} with an electrically insulating top layer (2500) directly covering the top surface of the insulated chip (100); arid
• forming at least one vertical interconnect structure (2600) vertically extending through the electrically insulating top layer (2500) and through the electrical! insulating layer (104} for providing an electric connection with the at least one chip pad (106) .
35, The method according to claim 34, wherein forming at least one vertical interconnect structure (2600) comprises:
• forming, in particular by laser drilling, at least one common access hole (1100) extending through both the electrically insulating top layer (2500) and the electrically insulating layer (104) in a common procedure to thereby expose the at least one chip pad (106) ; and
• filling the at least one common access hole (1100) with electrically conductive material.
36, The method according to any of claims 25 to 35, whe ein the method comprises manufacturing a plurality of packages (1200) at least partially in a batch procedure as a
consecutive structure being subsequently singularized into 31
the individual packages (1200) ,
37, A package (1200), comprising:
• an insulated chip (100) according to any of claims 1 to 6;
• a fu rther semiconductor chip (300);
• at least one bond wire (302) electrically connecting the insulated chip (100} with the further send. conductor chip (102) ,
38, The package (1200) according to claim 37, comprising a mounting base (304) on which both the insulated chip (100) and the further semiconductor chip {102} are mounted
separately fron one another.
39, Tne pa ckag e (1200) according to claim 38, whe re in the insulated ch i p (100) and the further semiconductor chip (102) are mo un ted on one another.
PCT/EP2016/077915 2015-07-06 2016-11-16 Insulated die WO2017102230A1 (en)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
DE102015110853 2015-07-06
DE102015122294.9A DE102015122294B4 (en) 2015-07-06 2015-12-18 Isolated Die
DE102015122294.9 2015-12-18

Publications (1)

Publication Number Publication Date
WO2017102230A1 true WO2017102230A1 (en) 2017-06-22

Family

ID=58010495

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/EP2016/077915 WO2017102230A1 (en) 2015-07-06 2016-11-16 Insulated die

Country Status (3)

Country Link
CN (1) CN106571347A (en)
DE (2) DE102015122294B4 (en)
WO (1) WO2017102230A1 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN111869334A (en) * 2018-03-12 2020-10-30 朱马技术有限公司 Method for manufacturing printed circuit board using conductor element mold

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN113163572A (en) 2020-01-22 2021-07-23 奥特斯(中国)有限公司 Component carrier with components covered with an ultra-thin transition layer
CN114325252A (en) * 2021-11-18 2022-04-12 北京卫星制造厂有限公司 Insulation protection method

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2005048302A2 (en) * 2003-11-05 2005-05-26 California Institute Of Technology Method for integrating pre-fabricated chip structures into functional electronic systems

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6908784B1 (en) * 2002-03-06 2005-06-21 Micron Technology, Inc. Method for fabricating encapsulated semiconductor components
US7923823B2 (en) * 2007-01-23 2011-04-12 Infineon Technologies Ag Semiconductor device with parylene coating
US7687895B2 (en) * 2007-04-30 2010-03-30 Infineon Technologies Ag Workpiece with semiconductor chips and molding, semiconductor device and method for producing a workpiece with semiconductors chips
US8264085B2 (en) * 2008-05-05 2012-09-11 Infineon Technologies Ag Semiconductor device package interconnections
JP4787296B2 (en) * 2008-07-18 2011-10-05 Ｔｄｋ株式会社 Semiconductor built-in module and manufacturing method thereof
US8008781B2 (en) * 2008-12-02 2011-08-30 General Electric Company Apparatus and method for reducing pitch in an integrated circuit
JP2011258867A (en) * 2010-06-11 2011-12-22 Casio Comput Co Ltd Semiconductor device and method of manufacturing the same
TWI575684B (en) * 2011-06-13 2017-03-21 矽品精密工業股份有限公司 Chip-scale package structure
US9496195B2 (en) * 2012-10-02 2016-11-15 STATS ChipPAC Pte. Ltd. Semiconductor device and method of depositing encapsulant along sides and surface edge of semiconductor die in embedded WLCSP

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2005048302A2 (en) * 2003-11-05 2005-05-26 California Institute Of Technology Method for integrating pre-fabricated chip structures into functional electronic systems

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN111869334A (en) * 2018-03-12 2020-10-30 朱马技术有限公司 Method for manufacturing printed circuit board using conductor element mold
CN111869334B (en) * 2018-03-12 2024-04-30 朱马技术有限公司 Method for manufacturing printed circuit board using conductor element mold

Also Published As

Publication number Publication date
DE202015009284U1 (en) 2017-01-20
DE102015122294A1 (en) 2017-04-06
DE102015122294B4 (en) 2021-04-22
CN106571347A (en) 2017-04-19

Similar Documents

Publication Publication Date Title
US9978720B2 (en) Insulated die
US20220130682A1 (en) Stiffener package and method of fabricating stiffener package
CN107275294B (en) Thin chip stack package structure and manufacturing method thereof
KR101634067B1 (en) Semiconductor package and method of manufacturing the same
CN103515260B (en) Encapsulation and forming method thereof in encapsulation
US9847236B2 (en) Electrical interconnect structure for an embedded electronics package
US8597983B2 (en) Semiconductor device packaging having substrate with pre-encapsulation through via formation
US20120306031A1 (en) Semiconductor sensor device and method of packaging same
CN105895535A (en) Electronic Device Package Including Metal Blocks
JP2006523964A (en) At least partially packaged circuit device and method of forming the same
WO2005078796A1 (en) Electronic component and method for manufacturing the same
US10522433B2 (en) Laminate package of chip on carrier and in cavity
US11721634B2 (en) Conductive structure and wiring structure including the same
CN106328607A (en) Semiconductor device and method for manufacturing same
US10700035B2 (en) Stacked electronics package and method of manufacturing thereof
CN106672888B (en) Method and device for packaging integrated circuit tube core
WO2017102230A1 (en) Insulated die
JP2004342861A (en) Chip type electronic component, dummy wafer, methods of manufacturing them, and packaging structure of electronic component
KR20160029037A (en) An interconnect system comprising an interconnect having a plurality of metal cores at least partially surrounded by a dielectric layer
KR20170002830A (en) Electronic component module and manufacturing method threrof
KR20150025939A (en) Interposer and semiconductor package using the same, and method of manufacturing interposer
US8686569B2 (en) Die arrangement and method of forming a die arrangement
US11978693B2 (en) Semiconductor device package comprising side walls connected with contact pads of a semiconductor die
CN211792251U (en) Embedded copper structure for microelectronic package
US10861780B1 (en) Wiring structure and method for manufacturing the same

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 16810260

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 16810260

Country of ref document: EP

Kind code of ref document: A1