CN103489757A - Etching method for laminated insulating film - Google Patents
Etching method for laminated insulating film Download PDFInfo
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- CN103489757A CN103489757A CN201310486173.4A CN201310486173A CN103489757A CN 103489757 A CN103489757 A CN 103489757A CN 201310486173 A CN201310486173 A CN 201310486173A CN 103489757 A CN103489757 A CN 103489757A
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- 238000005530 etching Methods 0.000 title claims abstract description 101
- 238000000034 method Methods 0.000 title claims abstract description 53
- 238000003486 chemical etching Methods 0.000 claims abstract description 24
- 230000004888 barrier function Effects 0.000 claims description 21
- 238000009413 insulation Methods 0.000 claims description 19
- 229920002120 photoresistant polymer Polymers 0.000 claims description 17
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims description 12
- 239000007789 gas Substances 0.000 claims description 12
- 239000001301 oxygen Substances 0.000 claims description 12
- 229910052760 oxygen Inorganic materials 0.000 claims description 12
- YCKRFDGAMUMZLT-UHFFFAOYSA-N Fluorine atom Chemical compound [F] YCKRFDGAMUMZLT-UHFFFAOYSA-N 0.000 claims description 11
- 229910052731 fluorine Inorganic materials 0.000 claims description 11
- 239000011737 fluorine Substances 0.000 claims description 11
- 239000001307 helium Substances 0.000 claims description 10
- 229910052734 helium Inorganic materials 0.000 claims description 10
- SWQJXJOGLNCZEY-UHFFFAOYSA-N helium atom Chemical compound [He] SWQJXJOGLNCZEY-UHFFFAOYSA-N 0.000 claims description 10
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 22
- 229910052581 Si3N4 Inorganic materials 0.000 description 11
- 230000000694 effects Effects 0.000 description 11
- 235000012239 silicon dioxide Nutrition 0.000 description 11
- 239000000377 silicon dioxide Substances 0.000 description 11
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 11
- 238000002161 passivation Methods 0.000 description 10
- 239000002184 metal Substances 0.000 description 6
- 238000001312 dry etching Methods 0.000 description 5
- 239000012212 insulator Substances 0.000 description 5
- 239000000758 substrate Substances 0.000 description 4
- 238000004380 ashing Methods 0.000 description 3
- 238000010586 diagram Methods 0.000 description 3
- 238000005516 engineering process Methods 0.000 description 3
- 150000002500 ions Chemical class 0.000 description 3
- 230000015572 biosynthetic process Effects 0.000 description 2
- 229910044991 metal oxide Inorganic materials 0.000 description 2
- 150000004706 metal oxides Chemical class 0.000 description 2
- 238000012545 processing Methods 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 230000003321 amplification Effects 0.000 description 1
- 150000001768 cations Chemical class 0.000 description 1
- 238000010276 construction Methods 0.000 description 1
- 238000001816 cooling Methods 0.000 description 1
- 238000002474 experimental method Methods 0.000 description 1
- 239000012634 fragment Substances 0.000 description 1
- 238000002513 implantation Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000003199 nucleic acid amplification method Methods 0.000 description 1
- 238000001259 photo etching Methods 0.000 description 1
- 238000002360 preparation method Methods 0.000 description 1
- 238000011160 research Methods 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 238000005389 semiconductor device fabrication Methods 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 238000001179 sorption measurement Methods 0.000 description 1
- 230000003068 static effect Effects 0.000 description 1
- 230000003313 weakening effect Effects 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31144—Etching the insulating layers by chemical or physical means using masks
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31105—Etching inorganic layers
- H01L21/31111—Etching inorganic layers by chemical means
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31105—Etching inorganic layers
- H01L21/31111—Etching inorganic layers by chemical means
- H01L21/31116—Etching inorganic layers by chemical means by dry-etching
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- Chemical & Material Sciences (AREA)
- Microelectronics & Electronic Packaging (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Power Engineering (AREA)
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Abstract
The invention discloses an etching method for a laminated insulating film. The etching method comprises the following steps: forming a mask layer with an etching window on the surface of an outermost insulating layer; etching the etching window by taking plasma physical bombardment etching as a main means and taking chemical etching an auxiliary means and forming a via hole; and removing the mask layer and performing destaticizing treatment. When the etching method provided by the invention is used for etching the laminated insulating film, the plasma physical bombardment etching is taken as the main means, the chemical etching is taken as the auxiliary means, and the differences among transverse etching rates of all the insulating layers can be reduced by reducing the action of chemical etching, so that the transverse etching rates of all the insulating layers are similar, the problem of bottom cutting is further avoided, and the effectiveness of the via hole is ensured.
Description
Technical field
The present invention relates to the semiconductor device fabrication process technical field, more particularly, relate to a kind of lithographic method for the laminated insulation film.
Background technology
In the various semiconductor device operations of preparation, sometimes need to adopt dry etching to carry out etching to the laminated insulation film with multilayer dielectric layer, form via hole.While adopting dry etching, because the etch rate of different insulation films differs larger, via etch has been caused to very large puzzlement.
The via etch for preparing the laminated insulation film in metal oxide TFT structure (metal oxide TFT) of take is example, on the silicon substrate surface of TFT structure, is provided with gate insulator, is provided with passivation layer on gate insulator.Gate insulator is generally silicon nitride layer, and passivation layer is generally silicon dioxide layer.Adopt existing lithographic method to carry out etching while forming via hole to described passivation layer and gate insulator, silicon nitride etch speed is greater than the etch rate of silicon dioxide, therefore because the silicon nitride layer etching that is positioned at the silicon dioxide layer below is too fast, there will be the undercutting problem, cause via hole to lose efficacy.
Summary of the invention
For solving the problems of the technologies described above, the invention provides a kind of lithographic method for the laminated insulation film, avoided the generation of etching process undercutting problem, guaranteed the validity of via hole.
For achieving the above object, the invention provides following technical scheme:
A kind of lithographic method for the laminated insulation film, this lithographic method comprises:
Surface at the outermost layer insulating barrier forms the mask layer with etching window;
The plasma physics of take bombardment etching, as main, chemical etching carry out etching as auxiliary to described etching window, forms via hole;
Remove described mask layer, and gone Electrostatic Treatment.
Preferably, in above-mentioned lithographic method, described take plasma physics bombardment etching as main, chemical etching as auxiliary to described etching window carry out etching as:
Under default pressure and power, adopt fluorine base gas and helium to carry out etching to described etching window, form via hole;
Wherein, the fluorine base gas range of flow is 100sccm-150sccm, comprises endpoint value.
Preferably, in above-mentioned lithographic method, the range of flow of described helium is 250sccm-350sccm, comprises endpoint value.
Preferably, in above-mentioned lithographic method, pass into oxygen during to described etching window etching.
Preferably, in above-mentioned lithographic method, the flow-rate ratio of described helium and oxygen is greater than 4:1.
Preferably, in above-mentioned lithographic method, described pressure range is 3Pa-10Pa, comprises endpoint value.
Preferably, in above-mentioned lithographic method, the scope of described power is 1000W-1600W, comprises endpoint value.
Preferably, in above-mentioned lithographic method, described mask layer is photoresist layer.
Preferably, in above-mentioned lithographic method, described fluorine base gas is SF6.
From technique scheme, can find out, lithographic method provided by the present invention is when carrying out laminated insulation film etching, the plasma physics of take bombardment etching is as master, chemical etching as auxiliary, by reducing the chemical etching effect, to reduce the difference of each insulating barrier lateral etching speed, make the lateral etching speed of each insulating barrier close, thereby avoided generation undercutting problem, guaranteed the validity of via hole.
The accompanying drawing explanation
In order to be illustrated more clearly in the embodiment of the present invention or technical scheme of the prior art, below will the accompanying drawing of required use in embodiment or description of the Prior Art be briefly described, apparently, accompanying drawing in the following describes is only some embodiments of the present invention, for those of ordinary skills, under the prerequisite of not paying creative work, can also obtain according to these accompanying drawings other accompanying drawing.
Fig. 1 a-Fig. 1 c is the schematic flow sheet that a kind of film of the laminated insulation to the TFT structure carries out etching;
The schematic flow sheet of a kind of lithographic method that Fig. 2 provides for the embodiment of the present invention;
A kind of film of the laminated insulation to the TFT structure that Fig. 3 a-3c provides for the embodiment of the present invention carries out the schematic flow sheet of etching.
Embodiment
Just as described in the background section, adopt existing lithographic method to carry out etching while forming via hole to described passivation layer and gate insulator, silicon nitride etch speed is greater than the etch rate of silicon dioxide, therefore because the silicon nitride layer etching that is positioned at the silicon dioxide layer below is too fast, there will be the undercutting problem, cause via hole to lose efficacy.
The laminated insulation film of TFT structure is carried out to etching while forming via hole, and a kind of lithographic method is at first, as shown in Figure 1a, to form one deck photoresist layer 14 on the surface of silicon dioxide passivation layer 3, and form etching window on photoresist layer 14.
Then, as shown in Figure 1 b, setting under pressure and power, by the plasma gas formed by fluorine base gas, helium and oxygen, the etching window place is carried out to etching, form via hole.This etching process is that plasma physics bombardment etching and chemical etching carry out simultaneously, plasma physics bombardment etching and chemical etching master acting in conjunction impel vertical etching of insulating barrier, and another effect of plasma chemical etching is the lateral etching that impels insulating barrier.But, the etch rate of silicon nitride gate insulating barrier 12 is different from the etch rate of silicon dioxide passivation layer 13, transversely, the etch rate of silicon nitride gate insulating barrier 12 is greater than the etch rate of silicon dioxide passivation layer 13, because transversely silicon nitride etch is very fast, cause etching through hole generation undercutting problem, form invalid via hole.
As shown in Fig. 1 c, after removing photoresist layer 14, while in the via hole on substrate 11, forming metal electrode layer 15, due to the undercutting problem, can cause metal level 15 to occur across disconnected problem, can't realize the via hole overlap joint.
The inventor studies discovery, for dry etching, and can be by reducing the chemical etching effect, reduce each insulating barrier lateral etching speed difference, so that the lateral etching speed of each insulating barrier is close, thereby form effective and the good via hole of practicality, avoid the generation of undercutting problem.
Based on above-mentioned research, the invention provides a kind of lithographic method for the laminated insulation film, the method comprises:
Surface at the outermost layer insulating barrier forms the mask layer with etching window;
The plasma physics of take bombardment etching, as main, chemical etching carry out etching as auxiliary to described etching window, forms via hole;
Remove described mask layer, and gone Electrostatic Treatment.
Lithographic method provided by the present invention is when carrying out laminated insulation film etching, the plasma physics of take bombardment etching is as master, chemical etching as auxiliary, by reducing the chemical etching effect, to reduce the difference of each insulating barrier lateral etching speed, make the lateral etching speed of each insulating barrier close, thereby avoided generation undercutting problem, guaranteed the validity of via hole.
It should be noted that, the described lithographic method of the application is all to refer to dry etching, and whole technical process can be carried out in existing etching apparatus, and the present techniques scheme is not done and repeated etching apparatus.
It is more than the application's core concept, below in conjunction with the accompanying drawing in the embodiment of the present invention, the technical scheme in the embodiment of the present invention is clearly and completely described, obviously, described embodiment is only the present invention's part embodiment, rather than whole embodiment.Embodiment based in the present invention, those of ordinary skills, not making under the creative work prerequisite the every other embodiment obtained, belong to the scope of protection of the invention.
A lot of details have been set forth in the following description so that fully understand the present invention, but the present invention can also adopt other to be different from alternate manner described here and implement, those skilled in the art can be in the situation that do similar popularization without prejudice to intension of the present invention, so the present invention is not subject to the restriction of following public specific embodiment.
Secondly, the present invention is described in detail in conjunction with schematic diagram, when the embodiment of the present invention is described in detail in detail; for ease of explanation; the schematic diagram of indication device part structure can be disobeyed general ratio and be done local the amplification, and described schematic diagram is example, and it should not limit the scope of protection of the invention at this.The three-dimensional space that in actual fabrication, should comprise in addition, length, width and height.
Based on above-mentioned thought, the present embodiment provides a kind of lithographic method for the laminated insulation film, and with reference to figure 2, described lithographic method comprises:
Step S11: the surface at the outermost layer insulating barrier forms the mask layer with etching window.
With reference to figure 3, the laminated insulation film of TFT structure is comprised: be positioned at the silicon nitride gate insulating barrier 22 on substrate 21 and be positioned at the silicon dioxide passivation layer 23 on silicon nitride gate insulating barrier 22.When this laminated construction is carried out to etching formation via hole, at first, on silicon dioxide passivation layer 23 surfaces, form the mask layer 24 that one decks have etching window.Preferably, described mask layer can be the photoresist layer formed by photoetching process.
It should be noted that, the present embodiment is only to take the etching of laminated insulation film of TFT structure to describe as example, but the execution mode of described technical scheme is not limited to the laminated insulation film of TFT structure, applicable to the etching of any laminated insulation film.
Step S12: the plasma physics of take bombardment etching, as main, chemical etching carry out etching as auxiliary to described etching window, forms via hole.
As shown in Figure 3, under default pressure and power, adopt fluorine base gas and helium to carry out etching to described etching window, form via hole, wherein, the fluorine base gas range of flow is 100sccm-150sccm, comprises endpoint value.In this range of flow, a little less than chemical etching effect, transversely etch rate difference is less for each insulating barrier.
Now, adopt high power, low pressure and larger He/O2 flow-rate ratio further to increase plasma physics bombardment corrasion, weaken horizontal chemical etching effect, thereby further reduce the difference of each insulating barrier lateral etching speed, realize take plasma physics bombardment etching as main, chemical etching be auxiliary etching.
Owing to adopting high power, low pressure to carry out etching, the energy of plasma is larger, to have more ion participates in vertically, make the ion that participates in horizontal chemical etching further reduce, silicon nitride gate insulating barrier 22 is further little with the lateral etching speed difference of silicon dioxide passivation layer 23, so the angle of gradient of the via hole of etching is good, the validity of via hole is good.
In this enforcement, power bracket is 1000W-1600W, and pressure range is 3Pa-10Pa.The range of flow of helium is 250sccm-350sccm.The flow of fluorine base gas is 100sccm-150sccm.In the present embodiment, described fluorine base gas preferably adopts SF6.
Owing to the three-dimensional physical bombardment effect such as having strengthened, so, in the described technical scheme of the present embodiment, can be so that being positioned at the etching window of photoresist layer enlarges gradually, in order to make the via hole of etching there is the angle of gradient preferably by stronger physical bombardment corrasion.Can pass into oxygen in etching process, further adjust the change speed of etching window.The flow-rate ratio of helium and oxygen is greater than 4:1, too fast with the astern speed of the photoresist of avoiding the etching window place.
On the one hand by weakening the chemical etching effect, avoid the generation of undercutting problem in this step, guarantee the validity of via hole to be etched.
On the other hand, existing dry etching technology etching in the horizontal is mainly by the chemical etching effect, and in the application, the plasma physics etching of take bombardment is as main, chemical etching is auxiliary, control the angle of gradient of via hole to be etched by stronger plasma physics bombardment effect, guarantee the validity of via hole to be etched.
The present embodiment, the opening that is less than via hole to be etched of etching window is set, due to stronger plasma physics bombardment effect, the etching window of photoresist layer can enlarge gradually, and like this, the insulating barrier zone that is subject to vertically going up plasma physical bombardment etching is along with etching window enlarges gradually and enlarges, the insulating barrier zone be etched is asynchronous on etch period, make etching depth form gradient difference, thereby form the angle of gradient preferably, avoid the generation of undercutting problem.
Step S13: carry out the photoresist ashing processing and go Electrostatic Treatment.
After above-mentioned etching process completes, carry out the photoresist ashing processing to remove photoresist layer.In the present embodiment, described ashing is treated to: at power, be that 450W-650W, pressure are to pass into oxygen under the 10Pa-20Pa condition, the flow of oxygen is 250sccm-350sccm.
In step S12, because photoresist has been subject to larger Ions Bombardment, etching process completes, react cooling after, the photoresist surface has Implantation can adhere to the product generated in some etching processes, thereby causes photoresist to be difficult for removing.And the cation that oxygen generates can soften photoresist, also can, with described product in conjunction with making its volatilization, can remove fast photoresist layer.
By removing Electrostatic Treatment, remove the static between the loading platform of substrate and etching device, prevent the generation of the fragment problems that causes due to the electrostatic adsorption between the two.The described removal Electrostatic Treatment of the present embodiment is: at power, be that 150W-200W, pressure are to pass into oxygen under the 10Pa-20Pa condition, the flow of oxygen is 250sccm-350sccm.
Finally, with reference to figure 5, because the via hole generated has the angle of gradient added, while in via hole, generating metal level 25, avoid metal level 25 across disconnected, can't realize the problem of via hole overlap joint.
In addition, adopt the present embodiment lithographic method to do the etching experiment contrast with adopting general lithographic method, each parameter value is as shown in table 1:
Table 1
Wherein, " novel " corresponding each parameter value of the present embodiment technical scheme that adopts, each parameter value in " tradition " corresponding general lithographic method.
Experimental result shows, adopt the via hole of the described lithographic method formation of the present embodiment there is no the undercutting problem, and the angle of gradient of via hole is good.Known by foregoing description, the described lithographic method of the present embodiment is via hole effectively, has avoided the generation of undercutting problem, thereby, while in via hole, generating metal level 25, has avoided metal level 25 across problem disconnected, that can't realize the via hole overlap joint.
To the above-mentioned explanation of the disclosed embodiments, make professional and technical personnel in the field can realize or use the present invention.Multiple modification to these embodiment will be apparent for those skilled in the art, and General Principle as defined herein can be in the situation that do not break away from the spirit or scope of the present invention, realization in other embodiments.Therefore, the present invention will can not be restricted to these embodiment shown in this article, but will meet the widest scope consistent with principle disclosed herein and features of novelty.
Claims (9)
1. the lithographic method for the laminated insulation film, is characterized in that, comprising:
Surface at the outermost layer insulating barrier forms the mask layer with etching window;
The plasma physics of take bombardment etching, as main, chemical etching carry out etching as auxiliary to described etching window, forms via hole;
Remove described mask layer, and gone Electrostatic Treatment.
2. lithographic method according to claim 1, is characterized in that, described take plasma physics bombardment etching as main, chemical etching as auxiliary to described etching window carry out etching as:
Under default pressure and power, adopt fluorine base gas and helium to carry out etching to described etching window, form via hole;
Wherein, the fluorine base gas range of flow is 100sccm-150sccm, comprises endpoint value.
3. lithographic method according to claim 2, is characterized in that, the range of flow of described helium is 250sccm-350sccm, comprises endpoint value.
4. lithographic method according to claim 1, is characterized in that, passes into oxygen during to described etching window etching.
5. lithographic method according to claim 4, is characterized in that, the flow-rate ratio of described helium and oxygen is greater than 4:1.
6. lithographic method according to claim 1, is characterized in that, described pressure range is 3Pa-10Pa, comprises endpoint value.
7. lithographic method according to claim 1, is characterized in that, the scope of described power is 1000W-1600W, comprises endpoint value.
8. lithographic method according to claim 1, is characterized in that, described mask layer is photoresist layer.
9. lithographic method according to claim 1, is characterized in that, described fluorine base gas is SF6.
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Cited By (3)
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| CN106707649A (en) * | 2017-03-01 | 2017-05-24 | 合肥京东方光电科技有限公司 | Via holes' preparation method, array substrate and preparation method thereof |
| CN108346569A (en) * | 2018-01-24 | 2018-07-31 | 中芯集成电路（宁波）有限公司 | The production method of semiconductor devices |
| CN111696863A (en) * | 2019-03-15 | 2020-09-22 | 北京北方华创微电子装备有限公司 | Silicon medium material etching method |
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| WO2018157601A1 (en) * | 2017-03-01 | 2018-09-07 | 京东方科技集团股份有限公司 | Manufacturing method for via, manufacturing method for array substrate, and array substrate |
| CN106707649B (en) * | 2017-03-01 | 2019-09-03 | 合肥京东方光电科技有限公司 | The preparation method of via hole, the preparation method of array substrate and array substrate |
| US11054707B2 (en) | 2017-03-01 | 2021-07-06 | Boe Technology Group Co., Ltd. | Method of manufacturing via hole, method of manufacturing array substrate, and array substrate |
| CN108346569A (en) * | 2018-01-24 | 2018-07-31 | 中芯集成电路（宁波）有限公司 | The production method of semiconductor devices |
| CN108346569B (en) * | 2018-01-24 | 2020-10-02 | 中芯集成电路（宁波）有限公司 | Method for manufacturing semiconductor device |
| CN111696863A (en) * | 2019-03-15 | 2020-09-22 | 北京北方华创微电子装备有限公司 | Silicon medium material etching method |
| CN111696863B (en) * | 2019-03-15 | 2024-04-12 | 北京北方华创微电子装备有限公司 | Silicon dielectric material etching method |
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