TWI570804B - A method of forming a notch at the bottom of the hole during the etching process, and a method of forming the hole - Google Patents

A method of forming a notch at the bottom of the hole during the etching process, and a method of forming the hole Download PDF

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TWI570804B
TWI570804B TW103144914A TW103144914A TWI570804B TW I570804 B TWI570804 B TW I570804B TW 103144914 A TW103144914 A TW 103144914A TW 103144914 A TW103144914 A TW 103144914A TW I570804 B TWI570804 B TW I570804B
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etching
hole
etched
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etching process
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TW201608634A (en
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qiu-ping Huang
hong-chao Wang
Li-Jun Yan
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Description

抑制刻蝕過程中孔底部出現缺口的方法、孔的形成方法Method for suppressing the occurrence of a notch at the bottom of a hole during etching, and method for forming a hole

本發明關於一種半導體製造領域,特別係關於一種利用等離子在待蝕刻材料層內刻蝕以形成貫穿該材料層的通孔的方法,用來抑制在通孔的底部(即該材料層與下方絕緣層的交界面處)出現缺陷(notching)現象。The present invention relates to the field of semiconductor fabrication, and more particularly to a method for etching a via hole in a material layer to be etched to form a through hole through the material layer for suppressing the bottom of the via hole (ie, the material layer is insulated from the bottom) At the interface of the layer, a phenomenon of notching occurs.

利用異向等離子刻蝕的方法在材料層內形成通孔是半導體加工最常見的工藝之一。如圖1,在刻蝕矽(或其它材料)1時,由於下方絕緣層(如氧化矽)2的電性隔離作用,矽1上會累積大量電荷。由於電荷的影響,當刻蝕進行至矽1與絕緣層2的交界面處時,孔3的兩側會產生缺口(notching)4。The use of anisotropic plasma etching to form vias in a material layer is one of the most common processes for semiconductor processing. As shown in Fig. 1, when ruthenium (or other material) 1 is etched, a large amount of charge is accumulated on 矽1 due to the electrical isolation of the lower insulating layer (e.g., yttrium oxide) 2. Due to the influence of the electric charge, when etching proceeds to the interface between the crucible 1 and the insulating layer 2, notches 4 are formed on both sides of the hole 3.

在某些應用中,缺口是要竭力避免的,因為缺口的存在本身就已破壞了特徵(即孔)的形狀,進而惡化器件的性能。不僅如此,缺口也會對後續的處理工藝(如對孔的填充)帶來問題。In some applications, the gap is to be avoided because the presence of the gap itself has destroyed the shape of the feature (ie, the hole), thereby degrading the performance of the device. Not only that, but the gap also poses problems for subsequent processing processes, such as filling holes.

本發明的目的在於改善等離子刻蝕過程中孔底部出現的缺口(notching)現象。It is an object of the present invention to improve the notching phenomenon that occurs at the bottom of a hole during plasma etching.

根據本發明的一個方面,提供一種利用波希法刻蝕孔結構的方法,其包括: 執行主刻蝕工藝,以形成孔,所述主刻蝕工藝包括:(a)、等離子刻蝕步驟;(b)、鈍化步驟;(c)、交替重複上述等離子刻蝕步驟(a)與鈍化步驟(b); 執行過刻蝕工藝,以加深所述孔,所述過刻蝕工藝包括:(d)等離子刻蝕步驟;(e)鈍化步驟;(f)交替重複上述等離子刻蝕步驟(d)與鈍化步驟(e); 其中,所述過刻蝕工藝對應的等離子刻蝕步驟(d)中反應腔內的工作氣壓,小於所述主刻蝕工藝對應的等離子刻蝕步驟(a)中反應腔內的工作氣壓。According to an aspect of the invention, a method for etching a hole structure by a Bosch method is provided, comprising: performing a main etching process to form a hole, the main etching process comprising: (a) a plasma etching step; (b) a passivation step; (c) alternately repeating the plasma etching step (a) and the passivation step (b); performing an over-etching process to deepen the hole, the over-etching process comprising: (d a plasma etching step; (e) a passivation step; (f) alternately repeating the plasma etching step (d) and the passivation step (e); wherein the over etching process corresponds to the plasma etching step (d) The working gas pressure in the reaction chamber is smaller than the working gas pressure in the reaction chamber in the plasma etching step (a) corresponding to the main etching process.

根據本發明的另一個方面,提供一種孔結構的形成方法,其包括: 提供基底,所述基底包括待蝕刻材料層與粘附在所述待蝕刻材料層下表面的絕緣層; 異向等離子刻蝕所述待蝕刻材料層,以初步形成孔; 在相對較低的工作氣壓環境下,繼續異向等離子刻蝕,以加深所述孔;至少在所述加深所述孔的工藝結束時,所述絕緣層已能透過所述孔而暴露。According to another aspect of the present invention, a method of forming a hole structure is provided, comprising: providing a substrate comprising a layer of a material to be etched and an insulating layer adhered to a lower surface of the layer of material to be etched; Etching the layer of material to be etched to initially form a hole; continuing the anisotropic plasma etch to deepen the hole under a relatively low working pressure environment; at least at the end of the process of deepening the hole The insulating layer has been exposed through the holes.

根據本發明的又一個方面,提供一種降低或消除孔結構刻蝕過程中孔底部出現缺口缺陷的方法,包括: 在上批工藝製得的器件中,孔底部出現缺口缺陷或缺口缺陷超出允許範圍時,調低上次工藝中等離子刻蝕步驟的工作氣壓; 以該調整後的參數對下批工件進行等離子刻蝕。According to still another aspect of the present invention, there is provided a method for reducing or eliminating a notch defect at the bottom of a hole during etching of a hole structure, comprising: in a device obtained by the above batch process, a notch defect or a notch defect at the bottom of the hole is out of an allowable range At the same time, the working gas pressure of the previous process medium ion etching step is lowered; the next batch of workpieces is plasma etched with the adjusted parameters.

目前的研究理論通常認為,等離子刻蝕中,孔底部缺口(notching)的產生與矽(或其它材料)上電荷的累積直接相關,因而,抑製缺口現象的思路通常是中和矽表面累積的電荷,或直接減少離子傳遞給矽的電荷量,具體的措施包括降低射頻的頻率(lower frequency)、施加脈衝(pulsed generator)於射頻電源、降低空占比(duty cycle,也可稱之為工作週期)等。Current research theories generally suggest that in plasma etching, the occurrence of notching at the bottom of the hole is directly related to the accumulation of charge on the ruthenium (or other material). Therefore, the idea of suppressing the notch phenomenon is usually the charge accumulated on the surface of the neutralized ruthenium. Or directly reduce the amount of charge delivered to the helium. Specific measures include lowering the radio frequency, applying a pulsed generator to the RF power source, and reducing the duty cycle. )Wait.

在研究消除缺口現象這一課題時,本發明人發現了一個新的可影響缺口的因素:等離子刻蝕的氣壓。在其它參數不變時,採用越低的工作氣壓,缺口現象的改善越明顯。In investigating the problem of eliminating the gap phenomenon, the inventors have discovered a new factor that can affect the gap: the plasma pressure of the plasma etching. When the other parameters are constant, the lower the working pressure, the more obvious the improvement of the notch phenomenon.

在等離子刻蝕中,刻蝕所形成的底部的表面是不平坦,為弧形,刻蝕步驟中的氣壓越高,弧形越大,反之越小。如圖2,刻蝕剛進行至下方絕緣層2時,孔3’底部中央區域的矽1已被消耗殆盡,而邊緣區域的矽1仍有殘留,並且越靠近邊緣殘留越多,也就是說刻蝕底面產生了高度差H。邊緣區域殘留的矽1材料大體呈臺階狀。In plasma etching, the surface of the bottom formed by etching is not flat and curved, and the higher the gas pressure in the etching step, the larger the arc shape, and vice versa. As shown in FIG. 2, when the etching is performed to the lower insulating layer 2, the 矽1 in the central portion of the bottom of the hole 3' has been exhausted, and the 矽1 of the edge region remains, and the closer to the edge remains, that is, It is said that the etched bottom surface produces a height difference H. The 矽1 material remaining in the edge region is generally stepped.

繼續刻蝕以清除殘留的矽1,如圖3,發明人發現,在這個過程中,伴隨著殘留矽的消除,其對應高度的孔側壁處也會出現損傷D(對於該損傷D產生的原因,發明人的理解是,伴隨著下方絕緣層的暴露面積越來越大,實際被刻蝕的矽1的面積逐漸在縮小,而起刻蝕作用的粒子數目卻維持不變,這使得矽1的刻蝕相當於被增強,進而導致出現損傷)。隨著刻蝕的進行,這些損傷D就會發展為最終的缺口。最終形成的缺口的高度基本等於上述的底面高度差H。The etching is continued to remove the residual 矽1. As shown in Fig. 3, the inventors have found that in this process, along with the elimination of residual ruthenium, damage D occurs at the sidewall of the corresponding height hole (for the cause of the damage D) The inventor's understanding is that as the exposed area of the underlying insulating layer becomes larger and larger, the area of the actually etched 矽1 is gradually reduced, and the number of particles that are etched remains unchanged, which makes 矽1 The etching is equivalent to being enhanced, resulting in damage). As the etch progresses, these damages D develop into the final gap. The height of the finally formed notch is substantially equal to the above-described bottom surface height difference H.

不同參數條件的多次試驗也都驗證了缺口與底面高度差(特別是剛刻蝕至下方絕緣層時刻蝕底面的高度差,如圖2所示的情景)之間的上述關係。Multiple tests of different parameter conditions have also verified the above relationship between the gap height of the notch and the bottom surface (especially the height difference of the etched bottom surface just after etching to the lower insulating layer, as shown in Figure 2).

鑒於上述發現,發明人提出,通過減小等離子刻蝕階段的工作氣壓,改善刻蝕底面的平坦度(高度差),減弱甚至是避免前面所述的刻蝕被增強現象,從而抑制或消除孔底部的缺口現象。具體實施時,既可以自始至終以較低的工作氣壓完成孔的刻蝕,也可以先以較高的工作氣壓刻蝕孔的大部分深度,待刻蝕至下方絕緣層或接近下方絕緣層時,再以較低的工作氣壓完成後續刻蝕。不管以上述的何種方式,都可抑制甚至消除缺口現象。In view of the above findings, the inventors propose to improve the flatness (height difference) of the etched bottom surface by reducing the working gas pressure in the plasma etching stage, thereby reducing or even avoiding the etching enhancement described above, thereby suppressing or eliminating the hole. The gap at the bottom. In the specific implementation, the hole etching may be completed at a lower working pressure from beginning to end, or the majority of the depth of the hole may be etched first at a higher working pressure, to be etched to the lower insulating layer or close to the lower insulating layer. Subsequent etching is then performed at a lower working pressure. Regardless of the above, the gap phenomenon can be suppressed or even eliminated.

以下結合附圖,對等離子刻蝕中如何具體實施本發明的方法以抑制通孔底部缺口現象進行說明。需強調的是,這裡僅是示例型的闡述,不排除有其它利用本發明的實施方式。Hereinafter, how to specifically implement the method of the present invention in plasma etching to suppress the notch phenomenon at the bottom of the via hole will be described with reference to the accompanying drawings. It is emphasized that the description herein is merely exemplary and that other embodiments that utilize the invention are not excluded.

依據本發明原理而實施的一種可抑制缺口產生的等離子刻蝕通孔工藝,如圖4所示,主要包括兩個刻蝕階段:主刻蝕階段與過刻蝕階段。其中,先執行的主刻蝕階段用於形成通孔的主要輪廓及深度,後執行的過刻蝕階段則在相對較低的氣壓環境中完成剩餘部分的刻蝕從而形成完整的通孔結構。下面結合待加工的半導體元件,詳細介紹該工藝的各步驟的實施情形及要達到的效果。A plasma etched via process capable of suppressing the occurrence of a notch according to the principles of the present invention, as shown in FIG. 4, mainly includes two etching stages: a main etching stage and an over etching stage. The first etch phase is performed to form the main outline and depth of the via hole, and the over-etching stage is performed to etch the remaining portion in a relatively low pressure environment to form a complete via structure. The implementation of each step of the process and the effects to be achieved will be described in detail below in connection with the semiconductor component to be processed.

提供基底。所述基底至少包括位於表面的待蝕刻材料層,以及粘附在待蝕刻材料層下表面的絕緣層。其中,絕緣層的材質與待蝕刻材料層不同,在後續的刻蝕工藝中較難(相對於待刻蝕材料層而言)被腐蝕,適合作為刻蝕停止層。絕緣層的下方還可以有其它材料層。A substrate is provided. The substrate includes at least a layer of material to be etched on the surface, and an insulating layer adhered to the lower surface of the layer of material to be etched. The material of the insulating layer is different from the material layer to be etched, and is difficult to be etched in the subsequent etching process (relative to the material layer to be etched), and is suitable as an etch stop layer. There may also be other layers of material beneath the insulating layer.

在本實施例中,該基底為SOI基板,如圖5所示。其頂層矽10為待蝕刻材料層;埋氧化層20為絕緣層及停止層,可防止對頂層矽10的刻蝕工藝損傷底層矽30。但是本發明並不局限於此,以其它方式提供待蝕刻材料層和停止層,也均在本發明的保護範圍之內。In this embodiment, the substrate is an SOI substrate, as shown in FIG. The top layer 矽10 is a material layer to be etched; the buried oxide layer 20 is an insulating layer and a stop layer, which can prevent the underlying germanium 30 from being damaged by the etching process of the top layer 矽10. However, the present invention is not limited thereto, and it is also within the scope of the present invention to provide the material layer to be etched and the stop layer in other ways.

不僅如此,待蝕刻材料層的材質並不局限於矽,其它任何適合在其內刻蝕通孔的材料,如鍺、氧化矽等,亦均可行。其下方絕緣層材質的選擇可根據待蝕刻材料層進行調整。另外,在進行刻蝕前,基底內(準確的說是待蝕刻材料層內)可已形成有其它結構,如淺溝槽隔離結構(圖中未示出)等。Moreover, the material of the material layer to be etched is not limited to germanium, and any other material suitable for etching through holes therein, such as germanium, antimony oxide, etc., can also be used. The material of the underlying insulating layer can be adjusted according to the layer of material to be etched. In addition, other structures, such as shallow trench isolation structures (not shown), etc., may already be formed in the substrate (accurately within the layer of material to be etched) prior to etching.

如圖6,在頂層矽10上方形成掩膜P,比如光刻膠。所述掩膜P遮蓋頂層矽10的部分區域;頂層矽10未被遮蓋的區域即是將被刻蝕而形成通孔的區域。As shown in FIG. 6, a mask P, such as a photoresist, is formed over the top layer 矽10. The mask P covers a partial area of the top layer 10; the uncovered area of the top layer 10 is the area where the through holes are to be etched.

將基底放置於一等離子刻蝕裝置內,執行主刻蝕工藝,透過掩膜P異向等離子刻蝕頂層矽10至一定深度,初步形成孔。形成的器件如圖7所示,其中,標號12所指為初步形成的孔。在圖7中,孔12的中央區域被刻蝕得較快,邊緣區域被刻蝕得相對較慢,使得中央區域至邊緣區域的連接處形成逐步抬升的階梯。The substrate is placed in a plasma etching apparatus, and a main etching process is performed to etch the top layer 10 to a certain depth through the mask P anisotropic plasma to form a hole. The device formed is as shown in Fig. 7, wherein reference numeral 12 denotes a preliminary formed hole. In Figure 7, the central region of the aperture 12 is etched faster and the edge region is etched relatively slowly such that the junction of the central region to the edge region forms a step-up step.

而後,調整該刻蝕裝置的反應腔內的氣壓,在較低的氣壓環境中,執行過刻蝕工藝,徹底清除上述孔12(參圖7)底部的矽材料,形成最終的通孔。上述過刻蝕工藝同樣為異向等離子刻蝕工藝。該步結束後形成的器件如圖8所示,其中,標號14所指為最終形成的通孔。由於過刻蝕步驟採用了較低的工作氣壓,保證了孔底部刻蝕的平坦度,從而消除了主刻蝕工藝階段所形成的階梯(或者說高度差),因而避免了孔底部兩側缺口(notching)的產生。Then, the gas pressure in the reaction chamber of the etching device is adjusted, and in a lower pressure environment, an etching process is performed to completely remove the germanium material at the bottom of the hole 12 (refer to FIG. 7) to form a final through hole. The above overetching process is also an anisotropic plasma etching process. The device formed after the end of this step is as shown in Fig. 8, wherein reference numeral 14 is referred to as the finally formed through hole. Since the over-etching step uses a lower working pressure, the flatness of the etching at the bottom of the hole is ensured, thereby eliminating the step (or height difference) formed in the main etching process, thereby avoiding the gap on both sides of the bottom of the hole. (notching) is produced.

在等離子刻蝕工藝中,反應腔內氣壓的設定會直接影響到刻蝕速率。在其它參數條件不變的情況下,氣壓越高,刻蝕速率越快;氣壓越低,刻蝕速率越慢,但相應的,刻蝕所形成表面的平坦度越高。在上述主刻蝕階段中,採用較高的氣壓完成通孔主要部分的刻蝕,基本保證了刻蝕效率;而收尾階段(即過刻蝕階段)採取的低氣壓只完成很淺深度的刻蝕,因而其在避免或抑制缺口產生的同時,不會明顯降低整個刻蝕的效率。In the plasma etching process, the setting of the gas pressure in the reaction chamber directly affects the etching rate. Under the condition that other parameters are unchanged, the higher the gas pressure, the faster the etching rate; the lower the gas pressure, the slower the etching rate, but correspondingly, the flatness of the surface formed by etching is higher. In the above main etching stage, the etching of the main part of the through hole is completed by using a higher air pressure, and the etching efficiency is basically ensured; and the low air pressure taken in the finishing stage (ie, the over etching stage) only completes the shallow depth. The etch, so it does not significantly reduce the efficiency of the entire etch while avoiding or suppressing the generation of the gap.

為保證異向刻蝕中側壁能保持較高的垂直度,不管是主刻蝕階段還是過刻蝕階段,同時通入的氣體較佳地都既包括刻蝕氣體,也包括鈍化氣體,其中,刻蝕氣體解離所形成的離子與待蝕刻材料反應生成的物質易自基底上分離,以實現刻蝕的目的;鈍化氣體解離所形成的離子與待蝕刻材料反應生成聚合物,並保留在側壁上,以實現對側壁的臨時保護。具體的刻蝕氣體與鈍化氣體的選擇及兩者之間比例的調節,以及刻蝕中各種參數的設定,都可根據待蝕刻的材料以及實際需求作選擇和調整。In order to ensure that the sidewalls of the anisotropic etching can maintain a high verticality, whether in the main etching stage or the over-etching stage, the gas to be introduced preferably includes both an etching gas and a passivation gas, wherein The ions formed by the dissociation of the etching gas and the material formed by the reaction of the material to be etched are easily separated from the substrate to achieve the purpose of etching; the ions formed by the dissociation of the passivation gas react with the material to be etched to form a polymer, and remain on the sidewall. To achieve temporary protection of the side walls. The choice of the specific etching gas and passivation gas and the adjustment of the ratio between the two, as well as the setting of various parameters in the etching, can be selected and adjusted according to the material to be etched and the actual needs.

作為一個更佳的替換方式,上述主刻蝕工藝、過刻蝕工藝均可採用波希法(Bosch process),以在獲得較高的側壁垂直度(highly vertical sidewalls)的同時,保證刻蝕的速率。也就是說,不管是主刻蝕還是過刻蝕,都可利用兩個交替循環的刻蝕步驟及鈍化步驟來實現。其中,在刻蝕步驟中,由反應氣體解離出的等離子的至少一部分沿幾乎豎直的方向轟擊基底;在鈍化步驟中,通入的鈍化氣體在暴露的基底表面(包括側壁、底部)生成一層聚合物。在後續的刻蝕步驟中,底部的聚合物會被垂直方向的粒子轟擊開,其下方的基底被暴露進而被刻蝕,而側壁的聚合物卻極少被轟擊,因而得以留存並起到對側壁的臨時保護作用。As a better alternative, the above-mentioned main etching process and over-etching process can all adopt the Bosch process to ensure high etching of the vertical sidewalls while ensuring etching. rate. That is to say, whether it is a main etch or an over etch, it can be realized by two alternating cycles of etching and passivation steps. Wherein, in the etching step, at least a portion of the plasma dissociated by the reactive gas bombards the substrate in an almost vertical direction; in the passivation step, the passivating gas is introduced to form a layer on the exposed substrate surface (including the sidewall, the bottom) polymer. In the subsequent etching step, the polymer at the bottom is bombarded by particles in the vertical direction, the underlying substrate is exposed and etched, and the polymer on the sidewall is rarely bombarded, thereby remaining and playing against the sidewall. Temporary protection.

當主刻蝕、過刻蝕採用波希法時,或者主刻蝕、過刻蝕中的至少一個在包含基本刻蝕步驟的同時還包含其它非刻蝕步驟時,本發明所說的“在較低的氣壓環境下刻蝕”要求的僅是實際刻蝕步驟在較低氣壓環境下進行,而不要求其它非刻蝕步驟(如鈍化步驟)也得是在該較低氣壓環境中進行。When the main etching or over etching adopts the Bosch method, or at least one of the main etching and the over etching includes other non-etching steps while including the basic etching step, the present invention Etching in a lower gas pressure environment requires only that the actual etching step be performed in a lower pressure environment, without requiring other non-etching steps (such as passivation steps) to be performed in this lower pressure environment.

當待蝕刻材料為矽時,通常將過刻蝕階段的氣壓設定為40mTorr或以下時,可基本消除孔底部缺口的產生,即便偶有缺口留存,其尺寸也已被限制在幾乎不對器件造成影響的程度。這裡需說明一點,由於氣壓並非可影響缺口產生的唯一要素,因而在調整氣壓的同時,保證其它參數(如Duty Cycle等)不在最差狀態也很重要。但是,即便由於實際需求或其它原因使得其它影響要素處於較差狀態而無法優化,依本發明調低刻蝕階段反應腔內的工作氣壓依然可以改善缺口現象。When the material to be etched is tantalum, when the gas pressure in the over-etching stage is usually set to 40 mTorr or less, the generation of the notch at the bottom of the hole can be substantially eliminated, and even if the gap is left, the size is limited to almost no influence on the device. Degree. It should be noted here that since air pressure is not the only factor that can affect the generation of the gap, it is also important to adjust the air pressure while ensuring that other parameters (such as Duty Cycle, etc.) are not in the worst state. However, even if the other influencing factors are in a poor state due to actual demand or other reasons and cannot be optimized, according to the present invention, the working pressure in the reaction chamber in the etching stage can be lowered to improve the notch phenomenon.

主刻蝕階段的刻蝕速率較快,因而通常可被利用來完成整個通孔的大部分深度。通常可在刻蝕最快的區域剛刻蝕至下方的停止層時,即馬上停止所述主刻蝕階段。在具體實施時,可根據實際需求選擇何時終止主刻蝕階段、開始過刻蝕階段。可遵循的原則是,主刻蝕階段終止的越早,殘留給過刻蝕階段刻蝕的待蝕刻材料層的深度越大,抑制缺口產生的效果越好;相對的,主刻蝕階段終止的越晚,整個刻蝕過程的刻蝕效率越高,但缺口產生的幾率越大、所產生的缺口缺陷越嚴重。在實際操作中,經驗證確實行之有效的一種做法是:檢查上個批次的產品,測量它們缺口產生的深度;在加工下個批次的相同產品時,將主刻蝕階段設定為到達這個深度前或到達這個深度時終止。舉例來講,假如上個批次加工獲得的多個產品,缺口大多是在距停止層還有X微米(或納米)開始出現,那麼,為了抑制缺口的產生,下個批次加工時,可以將主刻蝕工藝設定為距停止層還有X微米(或納米)或更多時終止,並代之以工作氣壓較小的過刻蝕工藝。The etch rate in the main etch phase is faster and can therefore typically be utilized to complete most of the depth of the entire via. The main etching phase can be stopped immediately when the etched region is just etched to the underlying stop layer. In the specific implementation, it may be selected according to actual needs when the main etching phase is terminated and the over-etching phase is started. The principle that can be followed is that the earlier the main etching phase is terminated, the greater the depth of the layer of material to be etched which is etched in the over-etching phase, and the better the effect of suppressing the notch is generated; in contrast, the main etching phase is terminated. The later, the higher the etching efficiency of the entire etching process, but the greater the probability of the gap, the more serious the gap defects are. In practice, one that has been proven to be effective is to check the last batch of products and measure the depth of their gaps; when processing the same batch of the next batch, set the main etch phase to arrive. This depth is terminated before or when this depth is reached. For example, if multiple products obtained by the above batch processing, the gaps are mostly started at X microns (or nanometers) from the stop layer, then, in order to suppress the generation of the gap, the next batch can be processed. The main etch process is set to terminate at X microns (or nanometers) or more from the stop layer and replaced with an over etch process with a lower working pressure.

在通孔(尤其是深孔)刻蝕時,缺口總是產生在通孔的底部,通常在超過某個深度,如整個孔深的六分之五深度後,才會出現,因而,為簡便計,可將主刻蝕工藝設定為刻蝕到整個孔深的六分之五結束。理論上,將主刻蝕工藝設定為刻蝕至整個孔深的三分之二到二十分至十九終止,都是可行的。假如太早結束主刻蝕,一方面不能進一步改善缺口現象(舉例而言,假如,稍晚結束主刻蝕的工藝X1已可完全避免缺口現象,比之更早結束主刻蝕的工藝X2自然無法在改善缺口現象方面比X1有更好表現),另一方面又降低了刻蝕效率;而太晚結束主刻蝕的話,可能導致後續進行的過刻蝕無意義,無法有效的改善缺口現象。When a through hole (especially a deep hole) is etched, the notch is always generated at the bottom of the through hole, and usually occurs after a certain depth, such as a depth of five-fifths of the depth of the entire hole, so that it is simple. The main etch process can be set to etch to the end of five-fifths of the entire hole depth. In theory, it is feasible to set the main etch process to etch to two-thirds to twenty-seven to nineteenth of the entire hole depth. If the main etch is terminated too early, on the one hand, the gap phenomenon cannot be further improved (for example, if the process X1 of the main etch is finished later, the gap phenomenon can be completely avoided, and the process of the main etch is terminated earlier than X2 naturally. It can't improve the notch phenomenon better than X1. On the other hand, it reduces the etching efficiency. If the main etching ends too late, it may cause subsequent over-etching to be meaningless and can not effectively improve the gap phenomenon. .

對於反應腔內設置有刻蝕終點監測裝置的等離子刻蝕設備,其可利用上述終點監測裝置監測整個刻蝕過程,並在刻蝕進行至停止層時,立刻終止主刻蝕工藝、開始過刻蝕工藝。For the plasma etching device provided with the etching end point monitoring device in the reaction chamber, the end point monitoring device can be used to monitor the entire etching process, and when the etching proceeds to the stop layer, the main etching process is immediately terminated and the etching is started. Etching process.

當刻蝕採用波希法時,選擇提高過刻蝕階段鈍化步驟的工作氣壓(這裡的提高是相對主刻蝕階段的鈍化步驟而言的)也可改善缺口現象。這是因為,鈍化步驟氣壓的提高可改善保護層(即聚合物)沉積的量(厚度),而位於側壁的保護層厚度的提高能更有效阻止缺口或損傷在側壁的出現。在具體實施時,可以將過刻蝕階段鈍化步驟的工作氣壓設置在70 mTorr或以上。當然,根據需要可選擇設置其它的氣壓參數。此亦不能視為對本發明的限制。When the etching is performed by the Bosch method, it is also possible to improve the notch phenomenon by increasing the working gas pressure in the passivation step of the over-etching stage (the improvement here is relative to the passivation step of the main etching stage). This is because the increase in the pressure of the passivation step improves the amount (thickness) of the deposition of the protective layer (i.e., the polymer), and the increase in the thickness of the protective layer on the side walls is more effective in preventing the occurrence of notches or damage in the sidewalls. In a specific implementation, the working pressure of the passivation step of the over-etching step can be set to 70 mTorr or more. Of course, other air pressure parameters can be selected as needed. This is also not to be construed as limiting the invention.

圖9是依據本發明原理而實施的另一種可抑制缺口產生的等離子刻蝕通孔工藝的流程示意圖。該工藝主要包括以下步驟:9 is a flow diagram of another plasma etched via process that inhibits the generation of a gap in accordance with the principles of the present invention. The process mainly includes the following steps:

步驟(1)、將第N批待加工品放置於等離子反應腔內。Step (1), placing the Nth batch of the to-be-processed product in a plasma reaction chamber.

該待加工品可以是如前面實施方式中所給出的、類似於圖5所示的基底,其至少包括位於表面以便加工的待蝕刻材料層,以及位於待蝕刻材料層下方的絕緣層。The article to be processed may be a substrate similar to that shown in FIG. 5 as given in the previous embodiment, comprising at least a layer of material to be etched on the surface for processing, and an insulating layer underlying the layer of material to be etched.

步驟(2)、依已設定好的參數執行等離子刻蝕,在待加工品內形成通孔。Step (2), performing plasma etching according to the set parameters, forming a through hole in the product to be processed.

該等離子刻蝕可以是如前面實施例中所給出的兩階段刻蝕法(即,分為主刻蝕階段與過刻蝕階段),或更多階段刻蝕法,也可以是單階段刻蝕法(即,自始至終以不變的參數完成對整個通孔的刻蝕)。不僅如此,該等離子刻蝕的每一階段(如有兩個或更多階段的話)可以採用波希法或不採用波希法,如前面實施方式中所描述。The plasma etching may be a two-stage etching method as shown in the previous embodiment (ie, a main etching step and an over etching step), or a more-stage etching method, or a single-stage etching method. Etching (ie, etching the entire via through the constant parameters from start to finish). Moreover, each stage of the plasma etch (if there are two or more stages) may or may not employ a Bosch method, as described in the previous embodiments.

步驟(3)、將加工完成的待加工品移出反應腔,檢測所形成通孔的底部有無出現缺口(notching),缺口尺寸有無超出允許範圍。Step (3), removing the processed product to be processed out of the reaction chamber, and detecting whether there is a notching at the bottom of the formed through hole, and whether the size of the gap exceeds the allowable range.

若未發現缺口,或缺口尺寸在允許範圍內,則維持之前的刻蝕參數,對相同待加工品的以後批次(如第N+1批次)繼續適用;If no gap is found, or the gap size is within the allowable range, the previous etching parameters are maintained, and the subsequent batches of the same product to be processed (such as the N+1 batch) continue to be applied;

若缺口尺寸超出允許範圍,則調整之前採用的刻蝕參數,以便在對後面批次(如第N+1批)加工時(在缺口缺陷方面)可取得更理想的效果。並且,調整參數而對下批次進行加工時,也可繼續對其成品的缺口繼續檢測,若其缺口仍達不到要求,可進一步優化其參數。If the notch size is outside the allowable range, the previously used etching parameters are adjusted so that a better effect can be obtained in the subsequent batches (such as the N+1 batch) (in terms of notch defects). Moreover, when the parameters are adjusted and the next batch is processed, the gap of the finished product can be continuously detected. If the gap still fails to meet the requirements, the parameters can be further optimized.

前面所說的為優化缺口缺陷而進行的參數調整,至少包括調低反應腔內部氣壓。當然,也可同時輔之以業內所熟知的可取得改善效果的其它參數調整,如降低射頻的頻率、降低空占比等。The parameter adjustment described above for optimizing the notch defect includes at least reducing the internal pressure of the reaction chamber. Of course, it can also be supplemented by other parameter adjustments well known in the industry that can achieve improvement effects, such as reducing the frequency of the radio frequency and reducing the space-to-occupancy ratio.

不僅如此,跟前面實施方式中所已論述過的相似,這裡的調低氣壓既可以是調低整個刻蝕階段的工作氣壓,也可以是只調低刻蝕階段後段(其大致對應於前面所討論過的過刻蝕階段)的工作氣壓。Moreover, similar to that discussed in the previous embodiments, the lowering of the air pressure here may be to lower the working air pressure of the entire etching stage, or to only lower the back stage of the etching stage (which roughly corresponds to the front side). The working pressure of the over-etching phase discussed.

儘管本發明的內容已經通過上述優選實施例作了詳細介紹,但應當認識到上述的描述不應被認為是對本發明的限制。在本領域技術人員閱讀了上述內容後,對於本發明的多種修改和替代都將是顯而易見的。因此,本發明的保護範圍應由所附的請求項來限定。Although the present invention has been described in detail by the preferred embodiments thereof, it should be understood that the foregoing description should not be construed as limiting. Various modifications and alterations of the present invention will be apparent to those skilled in the art. Accordingly, the scope of the invention should be defined by the appended claims.

1‧‧‧矽
2‧‧‧絕緣層
3‧‧‧孔
3’‧‧‧孔
4‧‧‧缺口
10‧‧‧頂層矽
12‧‧‧孔
14‧‧‧通孔
20‧‧‧埋氧化層
30‧‧‧底層矽
D‧‧‧損傷
H‧‧‧高度差
P‧‧‧掩膜
1‧‧‧矽
2‧‧‧Insulation
3‧‧‧ hole
3'‧‧‧ hole
4‧‧‧ gap
10‧‧‧ top layer
12‧‧‧ hole
14‧‧‧through hole
20‧‧‧ buried oxide layer
30‧‧‧Underground
D‧‧‧Injury
H‧‧‧ height difference
P‧‧ mask

通過閱讀參照以下附圖對非限制性實施例所作的詳細描述,本發明的其它特徵、目的和優點將會變得更明顯: 圖1是刻蝕矽通孔時,在矽與下方絕緣層介面處產生缺口的示意圖; 圖2是剛刻蝕至下方絕緣層時,刻蝕所形成的底面的不平整狀況的示意圖; 圖3是繼續刻蝕圖2所示器件而導致缺口產生的示意圖; 圖2與圖3結合在一起反映出了缺口產生位置與刻蝕底面不平整狀況之間的對應關係; 圖4是根據本發明一個具體實施例的用於刻蝕通孔結構的工藝的流程示意圖; 圖5至圖8是執行本發明一個具體實施例的刻蝕工藝的各步驟而形成的半導體元件的結構示意圖; 圖9是根據本發明另一個具體實施例的用於刻蝕通孔結構的工藝的流程示意圖。Other features, objects, and advantages of the present invention will become more apparent from the detailed description of the accompanying drawings. FIG. 2 is a schematic view showing the unevenness of the bottom surface formed by etching when the etching is performed to the lower insulating layer; FIG. 3 is a schematic view showing the generation of the gap caused by continuing etching the device shown in FIG. 2; 2 is combined with FIG. 3 to reflect the correspondence between the position where the gap is generated and the unevenness of the etched bottom surface; FIG. 4 is a schematic flow chart of a process for etching the through-hole structure according to an embodiment of the present invention; 5 to 8 are schematic views showing the structure of a semiconductor device formed by performing the steps of an etching process according to an embodiment of the present invention; and FIG. 9 is a process for etching a via structure according to another embodiment of the present invention. Schematic diagram of the process.

Claims (7)

一種利用波希法刻蝕孔結構的方法,包括:執行主刻蝕工藝,以形成孔,所述主刻蝕工藝包括:(a)、等離子刻蝕步驟;(b)、鈍化步驟;(c)、交替重複上述等離子刻蝕步驟(a)與鈍化步驟(b)直至一主刻蝕停止點;執行過刻蝕工藝,自該主刻蝕停止點加深所述孔,以形成最終通孔,所述過刻蝕工藝包括:(d)等離子刻蝕步驟;(e)鈍化步驟;(f)交替重複上述等離子刻蝕步驟(d)與鈍化步驟(e);其中,所述過刻蝕工藝對應的等離子刻蝕步驟(d)中反應腔內的工作氣壓,小於所述主刻蝕工藝對應的等離子刻蝕步驟(a)中反應腔內的工作氣壓。 A method for etching a hole structure by using a Bosch method, comprising: performing a main etching process to form a hole, the main etching process comprising: (a), a plasma etching step; (b), a passivation step; Repeating the above-described plasma etching step (a) and the passivation step (b) up to a main etching stop point; performing an over-etching process to deepen the hole from the main etching stop point to form a final via hole, The over-etching process includes: (d) a plasma etching step; (e) a passivation step; (f) alternately repeating the plasma etching step (d) and the passivation step (e); wherein the over-etching process The working gas pressure in the reaction chamber in the corresponding plasma etching step (d) is smaller than the working gas pressure in the reaction chamber in the plasma etching step (a) corresponding to the main etching process. 如請求項1所述的方法,其中,所述過刻蝕工藝對應的等離子刻蝕步驟(d)中反應腔內的工作氣壓不大於40mTorr。 The method of claim 1, wherein the working pressure in the reaction chamber in the plasma etching step (d) corresponding to the over-etching process is not more than 40 mTorr. 如請求項1所述的方法,其中,所述過刻蝕工藝對應的鈍化步驟(e)中反應腔內的工作氣壓,大於所述主刻蝕工藝對應的鈍化步驟(b)。 The method of claim 1, wherein the working gas pressure in the reaction chamber in the passivation step (e) corresponding to the over-etching process is greater than the passivation step (b) corresponding to the main etching process. 如請求項1所述的方法,其中,待蝕刻材料層的下方粘附一層不同材質的絕緣層,所述主刻蝕工藝在刻蝕最快的區域剛接觸所述絕緣層立刻停止,或未接觸到所述絕緣層停止。 The method of claim 1, wherein an insulating layer of a different material is adhered under the layer of the material to be etched, and the main etching process is immediately stopped in contact with the insulating layer in the region where the etching is fastest, or Contact with the insulating layer stops. 一種孔結構的形成方法,用以抑製或避免在孔的底部出現缺口,包括:提供基底,所述基底包括待蝕刻材料層與粘附在所述待蝕刻材料層下表面的絕緣層;異向等離子刻蝕所述待蝕刻材料層,以初步形成孔;在相對較低的工作氣壓環境下,繼續異向等離子刻蝕,以加深所述孔;至少在所述加深所述孔的工藝結束時,所述絕緣層已能透過所述孔而暴露。 A method for forming a hole structure for suppressing or avoiding the occurrence of a notch at the bottom of the hole, comprising: providing a substrate comprising a layer of material to be etched and an insulating layer adhered to a lower surface of the layer of material to be etched; Plasma etching the layer of material to be etched to initially form a hole; in a relatively low working pressure environment, continuing an anisotropic plasma etch to deepen the hole; at least at the end of the process of deepening the hole The insulating layer is already exposed through the aperture. 如請求項5所述的形成方法,其中,用於初步形成孔的所述刻蝕步驟,以及用於加深孔的所述刻蝕步驟,均採用的是波希法。 The forming method according to claim 5, wherein the etching step for preliminary forming the holes and the etching step for deepening the holes are all performed by a Bosch method. 如請求項5所述的形成方法,其中,所述待蝕刻材料層與所述絕緣層為SOI基板的頂層矽與埋氧化層。 The method of forming according to claim 5, wherein the material layer to be etched and the insulating layer are top layer germanium and buried oxide layers of the SOI substrate.
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TW201025437A (en) * 2008-08-08 2010-07-01 Ibm Through wafer via and method of making same
TW201344787A (en) * 2012-02-29 2013-11-01 Oxford Instr Nanotechnology Tools Ltd Methods and apparatus for depositing and/or etching material on a substrate

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