CN101051610A - Method for producing semiconductor device - Google Patents
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- CN101051610A CN101051610A CN 200610025422 CN200610025422A CN101051610A CN 101051610 A CN101051610 A CN 101051610A CN 200610025422 CN200610025422 CN 200610025422 CN 200610025422 A CN200610025422 A CN 200610025422A CN 101051610 A CN101051610 A CN 101051610A
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Abstract
When etching ONO laminated construction of SONOS parts, the method uses mixed gas of carbon tetrafluoride (CF4) and fluoroform (CHF3) as main etching gas instead of mixed gas of HBr and C2F6, and uses CHF3 as over etching gas instead of mixed gas of CH2F2/SF6. Using mixed gas of CF4 and CHF3 accomplishes main etching and over etching step for one time so as to simplify etching technique. Based on good etching selectivity and suitable etching speed, the method controls and buffers effect for etching ONO laminated construction by plasma of etching gas. In procedure for etching wafer thin oxidizing layer of grid electrode, the method is capable of controlling etching depth accurately, stopping etching at oxidation surface at low layer of ONO. Moreover, the method eliminates concave phenomena at sidewall and root part of polysilicon gate caused by transversal etching.
Description
Technical field
The present invention relates to semiconductor integrated circuit manufacturing technology field, the manufacture method of particularly a kind of semiconductor SONOS (silicon-oxide-nitirde-oxide-silicon silicon-oxide-nitride-silicon-oxide-silicon) device grids structure.
Background technology
Along with the develop rapidly of semiconductor fabrication, semiconductor device is in order to reach arithmetic speed faster, bigger memory data output and more function, and semiconductor wafer develops towards higher component density, high integration direction.SONOS (silicon-oxide-nitirde-oxide-silicon silicon-oxide-nitride--oxide-silicon) device receives publicity with its good scaled characteristic day by day as low-voltage high density non-volatility semiconductor flush memory device of new generation.Core texture is oxide layer-nitride layer-oxide layer (oxide-nitirde-oxide ONO) laminated construction that forms between polysilicon gate and surface of silicon in the SONOS device, each layer thickness of ONO has only about 10nm, and it is shorter that length becomes, and charge carrier is stored in the nitration case.Adopt the ONO layer of thinner thickness, can strengthen the coupling of gate electrode and channel carrier, make the arithmetic speed of device faster.
Application number is the grid structure manufacture method that 200310102359.1 Chinese patent application has been introduced a kind of field-effect transistor.The manufacturing process of semiconductor storage unit at first is to form field oxide isolator on silicon substrate, for example silicon oxide film and silicon nitride film, patterned insulation layer also forms opening by photoetching and etching technics on insulating barrier, opening has and defines the corresponding shape in active region isolation district.By utilizing silicon nitride film as mask, the etch silicon substrate utilizes the insulating barrier of chemical vapor deposition methods such as (CVD) deposition as silicon oxide film, so that this insulating barrier is imbedded or embedded in the STI isolated groove then to be formed with the STI isolated groove between the source region.The unnecessary dielectric film that utilizes chemical and mechanical grinding method (CMP) will be deposited on the silicon nitride film is removed.In ensuing processing step, remove silicon nitride film, and carry out necessary ion and inject as mask.Afterwards, on the surface of active area, form ONO layer and polysilicon layer.Fig. 1 is the generalized section of SONOS device ONO laminated construction.As shown in Figure 1, the ONO laminated construction at first forms the layer thickness grid oxic horizon (oxide) 110 of (about about 60 ) as thin as a wafer on active area 100 surfaces of substrate, form the nitration case (nitirde) 120 of a layer thickness thinner (about about 50 ) subsequently on grid oxic horizon 110 surfaces, form layer of oxide layer (oxide) 130 again on this nitration case surface then, about about 100 of thickness.On oxide layer 130, utilize technology deposit polysilicon gates 140 such as CVD then.Utilize silicon oxynitride (SiON) 150 as mask, with polysilicon layer 140 patternings, utilize anisotropic dry etch process then, adopt brominated Br and chlorine Cl by photoetching process
2Etching gas etch polysilicon grid 140 and grid oxic horizon (ONO), to form insulated gate electrode.Can form gate electrode by pattern with high precisionization with utmost point short gate length.Be injected in the district of gate electrode both sides with after forming the expansion area at ion, the dielectric film of deposition as silicon oxide film also carries out anisotropic etching with the formation side wall spacers.By utilizing gate electrode and side wall spacers as mask, carry out ion and inject to form source/drain region high impurity concentration or dark and the LDD (low doped drain region) that prevents short-channel effect, annealing then forms source electrode and drain electrode to activate the foreign ion that injects.
Common using plasma dry etch process in the etching of ONO lamination, traditional dry plasma etch technology is to feed etching gas in reative cell, the mist of hydrogen bromide HBr/ perfluoroethane C2F6 and difluoromethane CH2F2/ sulphur hexafluoride SF6 for example, under certain temperature and pressure, utilize high frequency power source to provide high frequency voltage with certain power, in the plasma span mist being excited becomes plasmoid.At excited state, the grid oxic horizon of energetic plasma fluorine bombardment wafer surface, etching oxidation layer and nitration case also are translated into volatile ingredient and are discharged by vacuum system.Fig. 2 causes the generalized section of defective for traditional ONO etching technics.As shown in Figure 2, in the manufacture process of SONOS device, oxide layer 130 and nitration case 120 need be etched away and keep thickness grid oxic horizon 110 as thin as a wafer, and require the ONO lamination that the pin of sticking up or depression can not be arranged, can not any damage be arranged to exposed polysilicon gate simultaneously.And in traditional etching technics,, cause grid oxic horizon 110 to be etched away or the ONO lamination has and significantly sticks up the pin problem because mist etching selection to silicon nitride and silica in etching process of hydrogen bromide HBr/C2F6 is not high.The simultaneously high etching rate of SF6 and relatively poor anisotropic etching selectivity often cause the sidewall of polysilicon gate 140 and root to be caused the defective, the especially root that cave in by lateral etching, depression is not only arranged but also have the problem of sticking up pin.To traditional technology node, 0.13um device for example, the about 70-200 of thickness of grid oxide layer, depression can not influence the performance of device for the cmos device of 0.13um.Yet for the process node of 65nm and even 45nm, the thickness of grid oxic horizon has only about 60 , and it is etched away and the lateral recesses of polysilicon gate root will make device performance reduce inevitably, and the degree of depth of LDD will be difficult to control.
Summary of the invention
Therefore, the object of the present invention is to provide a kind of manufacture method of semiconductor gate electrode structure, in plasma etching industrial, by adopting carbon tetrafluoride (CF
4) and fluoroform (CHF
3) mist the ONO lamination is carried out etching, grid oxic horizon in the prior art is etched and the problem of polysilicon gate root lateral recesses to solve.
For achieving the above object, the manufacture method of a kind of semiconductor device provided by the invention comprises:
A provides semi-conductive substrate, forms dielectric stack on substrate;
B forms polysilicon layer on described first dielectric layer;
C uses the described polysilicon layer of first gas etching to form polysilicon gate;
D uses the described dielectric stack of second gas etching.
Described dielectric stack is oxide-nitride thing-oxide (ONO) lamination.
Described second gas is carbon tetrafluoride (CF
4) and fluoroform (CHF
3) the plasma of mist.
In the described mist, fluoroform (CHF
3) proportion is 5%～20%.
Described first gas is hydrogen bromide HBr, bromine gas Br
2, chlorine Cl
2, oxygen O
2, helium He
2, nitrogen N
2, the plasma of one of them gas at least in argon Ar and the neon Ne gas.
Described etching process of steps d and the described etching process of step c are carried out in identical or different reative cell.
Described reative cell internal pressure is 50-100mT.
The radio-frequency power supply power output is 100-300W in the described reative cell.
Described etch period 10-20 second.
Described polysilicon gate is metal gate electrode very.
Described metal gate electrode comprises a kind of in following at least: titanium Ti,, tantalum Ta, tungsten W, titanium nitride TiN, tantalum nitride TaN and tungsten nitride WN.
Compared with prior art, the present invention has the following advantages:
The manufacture method of grid structure of the present invention adopts carbon tetrafluoride (CF when the ONO laminated construction of etching SONOS device
4) and fluoroform (CHF
3) mist as main etching gas, replace the mist of hydrogen bromide HBr and C2F6; Adopt fluoroform (CHF
3) as over etching gas, replace the CH2F2/SF6 mist.Adopt carbon tetrafluoride (CF
4) and fluoroform (CHF
3) mist once finish the step of main etching and over etching, simplified etching technics.Because good etching selection of above-mentioned etching gas and suitable etch rate, make the plasma of etching gas to the corrasion of ONO laminated construction controlled and buffering.In that grid oxic horizon is as thin as a wafer carried out in the process of etching, can accurately control the degree of depth of etching, make etching ideally stop at the lower floor oxide layer surface of ONO.And can eliminate the depressed phenomenon that produces at the polysilicon gate root fully.Grid electrode of semiconductor structure making process of the present invention is very effective for accurately controlling ONO lamination etching at 90nm, 65nm even 45nm and following process node.
Description of drawings
Fig. 1 is a SONOS device ONO laminated construction schematic diagram;
Fig. 2 causes the schematic diagram of defective for the traditional etching technics ONO laminated construction of explanation;
Fig. 3 and Fig. 4 are the SONOS device ONO laminated construction schematic diagram of explanation method, semi-conductor device manufacturing method of the present invention;
Fig. 5 is the flow chart of method, semi-conductor device manufacturing method of the present invention.
Embodiment
For above-mentioned purpose of the present invention, feature and advantage can be become apparent more, the specific embodiment of the present invention is described in detail below in conjunction with accompanying drawing.
The present invention has disclosed a kind of manufacture method of semiconductor gate electrode structure.Etching for the ONO laminated construction of 65nm and following SONOS device has very high precision.This method can be used for making low-voltage high density non-volatility semiconductor flush memory device of future generation.
Fig. 3 and Fig. 4 are the SONOS device ONO laminated construction schematic diagram of explanation grid electrode of semiconductor structure making process of the present invention.SONOS (silicon-oxide-nitirde-oxide-silicon silicon-oxide-nitride--oxide-silicon) device is as the non-volatile large-capacity semiconductor memory device of a new generation, and its core texture is the ONO laminated construction that forms between polysilicon gate 140 and Semiconductor substrate 100.As shown in Figure 3, the structure sheaf of the field-effect transistor of at first on substrate, growing, the active area that the method for utilizing ion to inject behind the transistor arrangement layer of having grown forms wherein comprises source region and lightly doped drain (LDD) in the active area, be used to prevent short channel effect.The zone of substrate 100 correspondences is an active region.One deck grid oxic horizon (oxide) 110 that the forming process of described ONO laminated construction at first forms on substrate 100 surfaces, oxide layer 110 adopts silicon dioxide (SiO usually
2), silicon oxynitride material or its combinations such as (SiON).Grid oxic horizon 110 adopts earth silicon material in the present embodiment, and thickness is about 60 .It should be noted that in different embodiment, grid oxic horizon 110 can adopt different materials, adopt different thickness.The growing method of gate dielectric layer 110 can be any conventional vacuum coating technology, such as atomic deposition (ALD), physical vapor deposition (PVD), chemical vapor deposition (CVD), plasma-enhanced chemical vapor deposition (PECVD) or the like.Then, at one deck nitration case (nitirde) 120 that grid oxic horizon 110 surfaces form, nitration case 120 is a silicon nitride in the present embodiment, and its thickness is thinner, is about about 50 ; Then, in the layer of oxide layer (oxide) 130 that silicon nitride 120 surfaces form, oxide layer 130 adopts silicon dioxide (SiO usually
2), silicon oxynitride material or its combinations such as (SiON).Oxide layer 130 adopts earth silicon material thickness to be about 100 in the present embodiment.After forming the ONO structure, utilize HDP-CVD technology deposit polysilicon layers such as (high-density plasma chemical vapor depositions).Generally, polysilicon layer adopts doped polycrystalline silicon materials, thickness 500-6000 .Polysilicon layer can comprise a kind of metal (such as titanium Ti, tantalum Ta, tungsten w etc.) and metallic compound (such as titanium nitride TiN, tantalum nitride TaN, tungsten nitride WN etc.) at least.In ensuing processing step, utilize silicon oxynitride (SiON) 150 as mask, by photoetching process with polysilicon layer patternization.Then, the using plasma anisotropic dry etch process is to form insulated polygate electrodes 140.The duration of technology is according to etch period, the specific reflection wavelength of plasma, and laser interference, and other technology is controlled.Be the etch polysilicon layer, adopt brominated Br and chlorine Cl
2Mist as etching gas.Mist can comprise such as chlorine Cl
2, oxygen O
2, nitrogen N
2, helium He and oxygen O
2Mist, perhaps helium-oxygen He-O
2, and inert gas or its mist (such as hydrogen Ar, neon Ne, helium He or the like), or its combination.During etching, the directivity of etching can realize by control cathode (substrate just) substrate bias power.Can control etch period by the control substrate bias power.In the present embodiment, feed etchant gas flow 50-400sccm in the reative cell, underlayer temperature is controlled between 20 ℃ and 90 ℃, and chamber pressure is 4-80mTorr, plasma source power output 1000W.In above-mentioned technology was crossed, etching formed the polysilicon gate 140 that is limited by mask 150, and made the surface of etching stopping at ONO structure upper strata silica 130 by the control etch period.
In ensuing processing step, the ONO laminated construction is carried out etching.The ONO laminated construction comprises one deck silicon oxide layer 110 that forms on substrate 100, middle silicon nitride layer 120 and top one deck silicon oxide layer 130.As previously mentioned, in the process of in the past using plasma dry etching ONO lamination, normally in reative cell, feed etching gas, in living etch step, adopt the mist of HBr/C2F6 as etching gas, in the over etching step, adopt the CH2F2/SF6 mist as etching gas, under certain temperature and pressure, in the plasma span mist being excited becomes plasmoid the ONO structure is carried out etching.Because mist etching selection to silicon nitride and silica in etching process of HBr/C2F6 is not high, cause grid oxic horizon 110 to be etched away or the ONO lamination has and significantly sticks up the pin problem.The simultaneously high etching rate of SF6 and relatively poor anisotropic etching selectivity often cause the sidewall of polysilicon gate 140 and root to be caused the defective, the especially root that cave in by lateral etching, depression is not only arranged but also have the problem of sticking up pin.The manufacture method of semiconductor device of the present invention adopts carbon tetrafluoride (CF
4) and fluoroform (CHF
3) mist as main etching gas, replace the mist of hydrogen bromide HBr and C2F6; Adopt fluoroform (CHF
3) as over etching gas, replace the CH2F2/SF6 mist.The manufacture method of semiconductor device of the present invention adopts carbon tetrafluoride (CF
4) and fluoroform (CHF
3) mist, top oxide layer 130 and the nitration case 120 of ONO are once finished main etching and over etching process.Etching gas during etching also comprises oxygen O
2, nitrogen N
2, helium He and oxygen O
2Mist, perhaps helium one oxygen He-O
2, and inert gas or its mist (such as hydrogen Ar, neon Ne, helium He or the like), or its combination.Carbon tetrafluoride (CF
4) and fluoroform (CHF
3) mist in, CHF
3The ratio that accounts for mist is 5%～20%.Plasma radiofrequency output power of power supply 100-300W, underlayer temperature are controlled between 20 ℃ and 80 ℃, and the reative cell internal pressure is controlled at 50-100mTorr.The upper strata silica 130 of ONO laminated construction and the etch period of intermediate layer silicon nitride layer 120 are controlled between 10～20S.Like this, because good directivity of plasma etching and the good etching selection of etching gas, the etching process of the upper strata silica 130 of ONO laminated construction and intermediate layer silicon nitride layer 120 is ideally stopped at the surface of ONO lower floor silica 110, and can not cause the phenomenon of lateral etching to the root of polysilicon gate 140, as shown in Figure 4.
Fig. 5 is the flow chart of method, semi-conductor device manufacturing method of the present invention.As shown in Figure 5, the manufacture method of semiconductor device provided by the invention comprises:
A provides semi-conductive substrate, forms dielectric stack on substrate;
B forms polysilicon layer on described first dielectric layer;
C uses the described polysilicon layer of first gas etching to form polysilicon gate;
D uses the described dielectric stack of second gas etching.
Wherein dielectric stack is oxide-nitride thing-oxide (ONO) lamination, and second gas in the steps d is carbon tetrafluoride (CF
4) and fluoroform (CHF
3) the plasma of mist.In mist, fluoroform (CHF
3) proportion is 5%～20%.First gas among the step c is hydrogen bromide HBr, bromine gas Br
2, chlorine Cl
2, oxygen O
2, helium He
2, nitrogen N
2, the plasma of one of them gas at least in argon Ar and the neon Ne gas.Described etching process of steps d and the described etching process of step c are carried out in identical or different reative cell, and the reative cell internal pressure is 50-100mT, and the radio-frequency power supply power output is 100-300W in the reative cell, etch period 10-20 second.Described polysilicon gate is metal gate electrode very, and metal gate electrode comprises a kind of in following at least: titanium Ti,, tantalum Ta, tungsten W, titanium nitride TiN, tantalum nitride TaN and tungsten nitride WN.
Though the present invention discloses as above with preferred embodiment, the present invention is defined in this.Any those skilled in the art without departing from the spirit and scope of the present invention, all can do various changes and modification, so protection scope of the present invention should be as the criterion with claim institute restricted portion.
Claims (11)
1, a kind of manufacture method of semiconductor device comprises:
A provides semi-conductive substrate, forms dielectric stack on substrate;
B forms polysilicon layer on described first dielectric layer;
C uses the described polysilicon layer of first gas etching to form polysilicon gate;
D uses the described dielectric stack of second gas etching.
2, the method for claim 1 is characterized in that: described dielectric stack is oxide-nitride thing-oxide (ONO) lamination.
3, the method for claim 1 is characterized in that: described second gas is carbon tetrafluoride (CF
4) and fluoroform (CHF
3) the plasma of mist.
4, method as claimed in claim 3 is characterized in that: in the described mist, and fluoroform (CHF
3) proportion is 5%～20%.
5, the method for claim 1 is characterized in that: described first gas is hydrogen bromide HBr, bromine gas Br
2, chlorine Cl
2, oxygen O
2, helium He
2, nitrogen N
2, the plasma of one of them gas at least in argon Ar and the neon Ne gas.
6, as claim 1,3 or 4 described methods, it is characterized in that: described etching process of steps d and the described etching process of step c are carried out in identical or different reative cell.
7, method as claimed in claim 6 is characterized in that: described reative cell internal pressure is 50-100mT.
8, method as claimed in claim 6 is characterized in that: the radio-frequency power supply power output is 100-300W in the described reative cell.
9, method as claimed in claim 6 is characterized in that: described etch period 10-20 second.
10, the method for claim 1 is characterized in that: described polysilicon gate is metal gate electrode very.
11, method as claimed in claim 10 is characterized in that: described metal gate electrode comprises a kind of in following at least: titanium Ti,, tantalum Ta, tungsten W, titanium nitride TiN, tantalum nitride TaN and tungsten nitride WN.
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|---|---|---|---|
| CNB200610025422XA CN100428416C (en) | 2006-04-03 | 2006-04-03 | Method for producing semiconductor device |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB200610025422XA CN100428416C (en) | 2006-04-03 | 2006-04-03 | Method for producing semiconductor device |
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|---|---|
| CN101051610A true CN101051610A (en) | 2007-10-10 |
| CN100428416C CN100428416C (en) | 2008-10-22 |
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| CNB200610025422XA Expired - Fee Related CN100428416C (en) | 2006-04-03 | 2006-04-03 | Method for producing semiconductor device |
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| CN102915911A (en) * | 2012-09-24 | 2013-02-06 | 中国电子科技集团公司第五十五研究所 | Etching method for improving bottom of silicon carbide table board |
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| CN102386122A (en) * | 2011-11-02 | 2012-03-21 | 上海宏力半导体制造有限公司 | Method for forming isolated trench by adopting hard mask |
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| CN109983563A (en) * | 2016-10-19 | 2019-07-05 | 朗姆研究公司 | Silica silicon nitride stack ion-assisted etching |
| CN110649152A (en) * | 2019-09-27 | 2020-01-03 | 江苏鲁汶仪器有限公司 | Etching method of niobium-based superconducting device |
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| CN113140505B (en) * | 2021-03-18 | 2023-08-11 | 上海华力集成电路制造有限公司 | Method for manufacturing through hole |
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| CN100428416C (en) | 2008-10-22 |
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