CN103474401A - Support plate structure and chip packaging structure and manufacturing method thereof - Google Patents
Support plate structure and chip packaging structure and manufacturing method thereof Download PDFInfo
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- CN103474401A CN103474401A CN2012101851045A CN201210185104A CN103474401A CN 103474401 A CN103474401 A CN 103474401A CN 2012101851045 A CN2012101851045 A CN 2012101851045A CN 201210185104 A CN201210185104 A CN 201210185104A CN 103474401 A CN103474401 A CN 103474401A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/11—Manufacturing methods
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
Abstract
The invention discloses a support plate structure and a chip packaging structure and a manufacturing method thereof. The support plate structure comprises a composite substrate, first and second dielectric layers, first and second via holes, first and second imbedded line layers. The composite substrate comprises first and second substrates. The first substrate has a first surface and a second surface. The second substrate has a third surface and a fourth surface. The second surface is connected with the fourth surface. The first dielectric layer and the second dielectric layer are respectively arranged on the first surface and the third surface. The first and second via holes are respectively arranged in the first and second dielectric layers. The first embedded line layer is disposed in the first dielectric layer and is connected to the first via hole. The second embedded line layer is mounted in the second dielectric layer and is connected to the second via hole.
Description
Technical field
The present invention relates to a kind of carrying board structure and chip-packaging structure and preparation method thereof
Background technology
Along with science and technology is maked rapid progress, integrated circuit (integrated circuits, IC) element has been widely used in the middle of our daily life.Generally speaking, the production of integrated circuit mainly is divided into three phases: the encapsulation of the manufacture of silicon wafer, the making of integrated circuit and integrated circuit.For the encapsulation of integrated circuit, wafer-class encapsulation (wafer level package, WLP) technology is considered to the encapsulation technology of growing up the most rapidly from now on.
In general wafer-class encapsulation manufacture craft, chip is installed on carrying board structure, then is covered with packing colloid.Afterwards, then the carrying board structure that will be equiped with chip be installed on printed substrate.Above-mentioned encapsulating carrier plate generally includes substrate and is positioned at the line layer of the upper and lower both sides of substrate (line layer of upside is in order to be electrically connected to chip, and the line layer of downside is in order to be electrically connected to wiring board).These line layers all are disposed on the surface of substrate, and the flatness that therefore makes encapsulating carrier plate is poor and be unfavorable for follow-up manufacture craft.In addition, because two sides up and down of substrate all must the configuration line layer, so carrying board structure still must have certain thickness and can't meet the demand of element slimming now.
Summary of the invention
The object of the present invention is to provide a kind of carrying board structure, it has thinner thickness.
Another purpose of the present invention is to provide a kind of manufacture method of carrying board structure, and it has better simply manufacturing process steps.
Another object of the present invention is to provide a kind of chip-packaging structure, and it has thinner thickness.
Still a further object of the present invention is to provide a kind of manufacture method of chip-packaging structure, and it has better simply manufacturing process steps.
For reaching above-mentioned purpose; the present invention proposes a kind of carrying board structure, and it comprises composite base plate, the first dielectric layer, the first via, the second dielectric layer, the second via, the first embedded type circuit layer, the second embedded type circuit layer, the first protective layer and the second protective layer.Composite base plate comprises first substrate and second substrate, and wherein first substrate has each other relative first surface and second surface, and second substrate has the 3rd surface and the 4th surface respect to one another, and second surface and the 4th surface engagement.The first dielectric layer is disposed on first surface, and has the first via.It is upper that the second dielectric layer is disposed at the 3rd surface, and have the second via.The first embedded type circuit layer is disposed in the first dielectric layer, and is connected with the first via, wherein the flush of the surface of the first embedded type circuit layer and the first dielectric layer.The second embedded type circuit layer is disposed in the second dielectric layer, and is connected with the second via, wherein the flush of the surface of the second embedded type circuit layer and the second dielectric layer.The first protective layer is disposed on the first dielectric layer, and exposes part the first embedded type circuit layer.The second protective layer is disposed on the second dielectric layer, and exposes part the second embedded type circuit layer.
According to the described carrying board structure of the embodiment of the present invention, also comprise the first barrier layer and the second barrier layer.The first barrier layer is disposed between first substrate and the first dielectric layer.The second barrier layer is disposed between second substrate and the second dielectric layer.
According to the described carrying board structure of the embodiment of the present invention, also comprise first surface processing layer and second surface processing layer.The first surface processing layer is disposed on the first embedded type circuit layer that the first protective layer exposes.The second surface processing layer is disposed on the second embedded type circuit layer that the second protective layer exposes.
According to the described carrying board structure of the embodiment of the present invention, also comprise layer reinforced structure, this layer reinforced structure comprises the stacking metal carbonyl conducting layer that is arranged at least one dielectric layer on the first embedded type circuit layer and/or the second embedded type circuit layer and corresponding this dielectric layer, and wherein metal carbonyl conducting layer is imbedded in this dielectric layer.
The another manufacture method that proposes a kind of carrying board structure of the present invention, the method is that composite base plate first is provided.Composite base plate comprises first substrate and second substrate, and wherein first substrate has each other relative first surface and second surface, and second substrate has the 3rd surface and the 4th surface respect to one another, and second surface and the 4th surface engagement.Then, form the first dielectric layer and the first via that is arranged in the first dielectric layer on first surface, and in the 3rd upper formation in surface the second dielectric layer and the second via that is arranged in the second dielectric layer.Afterwards, form the first embedded type circuit layer in the first dielectric layer, and form the second embedded type circuit layer in the second dielectric layer, wherein ㄧ embedded type circuit layer is connected with the first via, and the flush of the surface of the first embedded type circuit layer and the first dielectric layer, the second embedded type circuit layer is connected with the second via, and the flush of the surface of the second embedded type circuit layer and the second dielectric layer.After forming the first embedded type circuit layer, form the first protective layer on the first dielectric layer, the first protective layer exposes part the first embedded type circuit layer.After forming the second embedded type circuit layer, form the second protective layer on the second dielectric layer, the second protective layer exposes part the second embedded type circuit layer.
Manufacture method according to the described carrying board structure of the embodiment of the present invention, before forming the first dielectric layer and the first via, can also on first surface, form the first barrier layer, and before forming the second dielectric layer and the second via, can also be in the 3rd upper formation in surface the second barrier layer.
Manufacture method according to the described carrying board structure of the embodiment of the present invention; after forming the first protective layer; form the first surface processing layer on the first embedded type circuit layer that can also expose in the first protective layer; and, after forming the second protective layer, form the second surface processing layer on the second embedded type circuit layer that can expose in the second protective layer.
Manufacture method according to the described carrying board structure of the embodiment of the present invention, the formation method of the first above-mentioned dielectric layer, the first via, the second dielectric layer and the second via is for example prior to forming the first conductive layer on first surface, and in the 3rd upper formation in surface the second conductive layer.Then, patterning the first conductive layer is to form the first via, and patterning the second conductive layer is to form the second via.Afterwards, pressing the first dielectric layer on first surface, and in the 3rd upper pressing the second dielectric layer in surface.
Manufacture method according to the described carrying board structure of the embodiment of the present invention, the first above-mentioned embedded type circuit layer and the formation method of the second embedded type circuit layer are for example prior to forming the first channel patterns in the first dielectric layer, and form the second channel patterns in the second dielectric layer, wherein the first channel patterns exposes part the first via, and the second channel patterns exposes part the second via.Afterwards, form the 3rd conductive layer in the first channel patterns, and form the 4th conductive layer in the second channel patterns.
The present invention proposes again a kind of chip-packaging structure, and it comprises substrate, dielectric layer, via, embedded type circuit layer, protective layer, surface-treated layer, chip and packing colloid.Dielectric layer is disposed on substrate.Via is disposed in dielectric layer.The embedded type circuit layer is disposed in dielectric layer, and is connected with via, wherein the flush of the surface of embedded type circuit layer and dielectric layer.Protective layer is disposed on dielectric layer, and exposes part embedded type circuit layer.Surface-treated layer is disposed on the embedded type circuit layer that protective layer exposes.Chip configuration, on protective layer, and is electrically connected to surface-treated layer.Packing colloid covers chip, protective layer and surface-treated layer.
According to the described chip-packaging structure of the embodiment of the present invention, also comprise barrier layer, it is disposed between substrate and dielectric layer.
According to the described chip-packaging structure of the embodiment of the present invention, above-mentioned chip for example is disposed on protective layer in the mode of routing joint (wire bond), and is electrically connected to surface-treated layer by routing (bonding wire).
According to the described chip-packaging structure of the embodiment of the present invention, above-mentioned chip for example is disposed on protective layer in the mode of flip-chip bonded (flip chip), and is electrically connected to surface-treated layer by projection (bump).
Based on above-mentioned, the line layer in carrying board structure of the present invention is the embedded line layer, and therefore carrying board structure of the present invention can have more smooth surface, and is conducive to follow-up manufacture craft.In addition, the present invention carries out identical manufacture craft in two sides of composite base plate, and then the first substrate in composite base plate is separated to form two times to carrying board structure with second substrate, therefore can effectively improve productive rate simultaneously, and because manufacturing process steps is simple, thereby reduce production costs.
For above-mentioned feature and advantage of the present invention can be become apparent, special embodiment below, and coordinate appended accompanying drawing to be described in detail below.
The accompanying drawing explanation
The making flow process cutaway view that Figure 1A to Fig. 1 H is the chip-packaging structure that illustrates of the embodiment of the present invention;
The generalized section that Fig. 2 is the chip-packaging structure that illustrates of another embodiment of the present invention.
The main element symbol description
10: composite base plate
20a, 20b: inferior carrying board structure
22: chip
24: routing
26: packing colloid
28: soldered ball
29: projection
30: chip-packaging structure
100: first substrate
100a: first surface
100b: second surface
102: the first barrier layers
103: the first conductive layers
104: the first vias
106: the first dielectric layers
108: the first channel patterns
110: the first embedded type circuit layers
112: the first protective layers
114: the first surface processing layer
200: second substrate
200a: the 3rd surface
200b: the 4th surface
202: the second barrier layers
203: the second conductive layers
204: the second vias
206: the second dielectric layers
208: the second channel patterns
210: the second embedded type circuit layers
212: the second protective layers
214: the second surface processing layer
Embodiment
The making flow process cutaway view that Figure 1A to Fig. 1 H is the chip-packaging structure that illustrates according to the embodiment of the present invention.At first, please refer to Figure 1A, composite base plate 10 is provided.Composite base plate 10 comprises first substrate 100 and second substrate 200.First substrate 100 has each other relative first surface 100a and second surface 100b.The material of first substrate 100 is for example metal or plastic cement.Second substrate 200 has the 3rd surperficial 200a respect to one another and the 4th surperficial 200b.The material of second substrate 200 is for example metal or plastic cement.In the present embodiment, the second surface 100b of first substrate 100 engages with the 4th surperficial 200b of second substrate 200 and forms composite base plate 10.
In addition, can also optionally form barrier layer on composite base plate 10.In the present embodiment, in upper first barrier layer 102 that forms of first surface 100a, and in upper second barrier layer 202 that forms of the 3rd surperficial 200a.The material of the first barrier layer 102 is for example metal or polymer.The material of the second barrier layer 202 is for example metal or polymer.Above-mentioned metal is for example aluminium or nickel.
Then, please refer to Figure 1B, form the first conductive layer 103 on the first barrier layer 102, and form the second conductive layer 203 on the second barrier layer 202.The material of the first conductive layer 103 and the second conductive layer 203 is for example copper, and it is in order to form follow-up conductive through hole.In the present embodiment, the first conductive layer 103 and the second conductive layer 203 are for example that mode by pressing is formed at respectively on the first barrier layer 102 and the second barrier layer 202.
Then, please refer to Fig. 1 C, by the first conductive layer 103 patternings to form the first via 104, and by the second conductive layer 203 patternings to form the second via 204.By the method for the first conductive layer 103 and the second conductive layer 203 patternings, be for example prior on the first conductive layer 103 and the second conductive layer 203, forming respectively patterning photoresist layer.Then, take patterning photoresist layer carries out etching process as cover curtain.Afterwards, remove patterning photoresist layer.
Then, pressing the first dielectric layer 106 on the first barrier layer 102, and on the second barrier layer 202 pressing the second dielectric layer 206.Then, form the first channel patterns 108 in the first dielectric layer 106, and form the second channel patterns 208 in the second dielectric layer 206.The first channel patterns 108 exposes part the first via 104.The second channel patterns 208 exposes part the second via 204.
In the present embodiment, the first channel patterns 108 and the second channel patterns 208 expose respectively the end face of the first via 104 and the second via 204, but the present invention is not limited to this.In another embodiment, the first via 104 and the second via 204 are except end face is exposed, and its partial sidewall also can be exposed.In addition, in the present embodiment, the first channel patterns 108 has the degree of depth of homogeneous, and the second channel patterns 208 has the degree of depth of homogeneous, but the present invention is not limited to this.In another embodiment, also visual actual demand and there is separately the degree of depth of non-homogeneous of the first channel patterns 108 and the second channel patterns 208.
Then, please refer to Fig. 1 E, form conductive layer to form the first embedded type circuit layer 110 in the first channel patterns 108, and form conductive layer to form the second embedded type circuit layer 210 in the second channel patterns 208.Above-mentioned conductive layer is for example the copper layer, and its formation method is for example galvanoplastic.Formed ㄧ embedded type circuit layer 110 is connected with the first via 104, and the second embedded type circuit layer 210 is connected 204 with the second via.In addition, the flush of the surface of the first embedded type circuit layer 110 and the first dielectric layer 106, and the flush of the surface of the second embedded type circuit layer 210 and the second dielectric layer 206.Then, form the first protective layer 112 on the first dielectric layer 106, and form the second protective layer 212 on the second dielectric layer 106.The first protective layer 112 exposes part the first embedded type circuit layer 110, and the second protective layer 212 exposes part the second embedded type circuit layer 210.Then; form first surface processing layer 114 on the first embedded type circuit layer 110 exposed in the first protective layer 112; and form second surface processing layer 214 on the second embedded type circuit layer 210 exposed in the second protective layer 212, to make carrying board structure of the present invention.First surface processing layer 114 is for example the gold layer with second surface processing layer 214.First surface processing layer 114/ second surface processing layer 214 can be used as the zone be connected with the chip of follow-up installing, so that chip can be electrically connected to the first embedded type circuit layer 110/ second embedded type circuit layer 210.
Subsequently, please refer to Fig. 1 F, separate first substrate 100 and second substrate, to form time carrying board structure 20a and 20b.In inferior carrying board structure 20a and 20b, owing to only thering is one deck line layer (the first embedded type circuit layer 110/ second embedded type circuit layer 210), because this carrying board structure 20a and 20b can have thinner thickness.Inferior carrying board structure 20a has in fact identical structure with 20b, and therefore following is that example explains follow-up manufacturing process steps by the following carrying board structure 20a.Any manufacturing process steps of carrying out for inferior carrying board structure 20a is applied to time carrying board structure 20b equally.
Then, please refer to Fig. 1 G, in the upper installing chip 22 of inferior carrying board structure 20a.Chip 22 is installed in the first protective layer 112, and is electrically connected to first surface processing layer 114.In the present embodiment, the mode that chip 22 engages with routing is installed on the first protective layer 112, and is electrically connected to first surface processing layer 114 by routing 24.Then, form the packing colloid 26 that covers chip 22, routing 24, the first protective layer 112 and first surface processing layer 114, to make chip-packaging structure 30.
Afterwards, please refer to Fig. 1 H, remove the first barrier layer 102 and first substrate 100, to expose the first dielectric layer 106 and the first conductive through hole 104.Special one carry be, in the present embodiment, owing between first substrate 100 and the first dielectric layer 106, having the first barrier layer 102, and the material of the first barrier layer 102 is metal or polymer, therefore can easily from the first dielectric layer 106, remove the first barrier layer 102 and first substrate 100.Then, form soldered ball 28 on the first conductive through hole 104.
In the present embodiment, the mode that chip 22 engages with routing is installed on the first protective layer 112, but the present invention is not limited to this.In another embodiment, chip 22 also can utilize the mode of flip-chip bonded to be installed on the first protective layer 112, as shown in Figure 2.In Fig. 2, chip 22 is installed on the first protective layer 112 in the mode of flip-chip bonded, and is electrically connected to first surface processing layer 114 by projection 29.
Special one carry be, in the embodiment do not illustrated at other, can also utilize the stacking setting of the mode metal carbonyl conducting layer of one dielectric layer and corresponding this dielectric layer at least that increases layer on the first embedded type circuit layer 110 and/or the second embedded type circuit layer 120, wherein this metal carbonyl conducting layer is embedded in this dielectric layer.
In sum, because the line layer in carrying board structure is the embedded line layer, so carrying board structure can have more smooth surface, and is conducive to follow-up manufacture craft.
In addition, the present invention carries out identical manufacture craft in two sides of composite base plate simultaneously, and then the first substrate in composite base plate is separated to form two time carrying board structures with second substrate, therefore can effectively improve productive rate, and because the manufacturing process steps of inferior carrying board structure is simple, thereby can shorten the manufacture craft time, and then reduce production costs.
Although in conjunction with above embodiment, disclosed the present invention; yet it is not in order to limit the present invention; be familiar with this operator in technical field under any; without departing from the spirit and scope of the present invention; can do a little change and retouching, thus protection scope of the present invention should with enclose claim was defined is as the criterion.
Claims (13)
1. a carrying board structure comprises:
Composite base plate, comprise first substrate and second substrate, and wherein this first substrate has each other relative first surface and second surface, and this second substrate has the 3rd surface and the 4th surface respect to one another, and this second surface and the 4th surface engagement;
The first dielectric layer, be disposed on this first surface, and have the first via;
The second dielectric layer, be disposed at the 3rd surface upper, and have the second via;
The first embedded type circuit layer, be disposed in this first dielectric layer, and be connected with this first via, wherein the flush of the surface of this first embedded type circuit layer and this first dielectric layer;
The second embedded type circuit layer, be disposed in this second dielectric layer, and be connected with this second via, wherein the flush of the surface of this second embedded type circuit layer and this second dielectric layer;
The first protective layer, be disposed on this first dielectric layer, and expose this first embedded type circuit layer of part; And
The second protective layer, be disposed on this second dielectric layer, and expose this second embedded type circuit layer of part.
2. carrying board structure as claimed in claim 1 also comprises:
The first barrier layer, be disposed between this first substrate and this first dielectric layer; And
The second barrier layer, be disposed between this second substrate and this second dielectric layer.
3. carrying board structure as claimed in claim 1 also comprises:
The first surface processing layer, be disposed on this first embedded type circuit layer that this first protective layer exposes; And
The second surface processing layer, be disposed on this second embedded type circuit layer that this second protective layer exposes.
4. carrying board structure as claimed in claim 1, also comprise layer reinforced structure, this layer reinforced structure comprises stacking at least one dielectric layer on this first embedded type circuit layer and/or this second embedded type circuit layer and the metal carbonyl conducting layer to should dielectric layer of being arranged at, and wherein this metal carbonyl conducting layer is imbedded in this dielectric layer.
5. the manufacture method of a carrying board structure comprises:
One composite base plate is provided, this composite base plate comprises first substrate and second substrate, wherein this first substrate has each other relative first surface and second surface, and this second substrate has the 3rd surface and the 4th surface respect to one another, and this second surface and the 4th surface engagement;
Form the first dielectric layer and the first via that is arranged in this first dielectric layer on this first surface, and in the 3rd upper formation in surface the second dielectric layer and the second via that is arranged in this second dielectric layer;
Form the first embedded type circuit layer in this first dielectric layer, and form the second embedded type circuit layer in this second dielectric layer, wherein this first embedded type circuit layer is connected with this first via, and the surface of this first embedded type circuit layer and the flush of this first dielectric layer, this the second embedded type circuit layer is connected with this second via, and the flush of the surface of this second embedded type circuit layer and this second dielectric layer;
After forming this first embedded type circuit layer, form the first protective layer on this first dielectric layer, this first protective layer exposes this first embedded type circuit layer of part; And
After forming this second embedded type circuit layer, form the second protective layer on this second dielectric layer, this second protective layer exposes this second embedded type circuit layer of part.
6. the manufacture method of carrying board structure as claimed in claim 5 also comprises:
Before forming this first dielectric layer and this first via, form the first barrier layer on this first surface; And
Before forming this second dielectric layer and this second via, form the second barrier layer on the 3rd surface.
7. the manufacture method of carrying board structure as claimed in claim 5 also comprises:
After forming this first protective layer, form the first surface processing layer on this first embedded type circuit layer exposed at this first protective layer; And
After forming this second protective layer, form the second surface processing layer on this second embedded type circuit layer exposed at this second protective layer.
8. the manufacture method of carrying board structure as claimed in claim 5, wherein the formation method of this first dielectric layer, this first via, this second dielectric layer and this second via comprises:
Form one first conductive layer on this first surface, and form the second conductive layer on the 3rd surface;
This first conductive layer of patterning is to form this first via, and this second conductive layer of patterning is to form this second via; And
This first dielectric layer of pressing on this first surface, and on the 3rd surface this second dielectric layer of pressing.
9. as the manufacture method of claim 5 or 7 described carrying board structures, wherein the formation method of this first embedded type circuit layer and this second embedded type circuit layer comprises:
Form the first channel patterns in this first dielectric layer, and form the second channel patterns in this second dielectric layer, wherein this first channel patterns exposes this first via of part, and this second channel patterns exposes this second via of part; And
Form the 3rd conductive layer in this first channel patterns, and form the 4th conductive layer in this second channel patterns.
10. a chip-packaging structure comprises:
Substrate;
Dielectric layer, be disposed on this substrate;
Via, be disposed in this dielectric layer;
The embedded type circuit layer, be disposed in this dielectric layer, and be connected with this via, wherein the flush of the surface of this embedded type circuit layer and this dielectric layer;
Protective layer, be disposed on this dielectric layer, and expose this embedded type circuit layer of part;
Surface-treated layer, be disposed on this embedded type circuit layer that this protective layer exposes;
Chip, be disposed on this protective layer, and be electrically connected to this surface-treated layer; And
Packing colloid, cover this chip, this protective layer and this surface-treated layer.
11. chip-packaging structure as claimed in claim 10, also comprise barrier layer, is disposed between this substrate and this dielectric layer.
12. chip-packaging structure as claimed in claim 10, the mode that wherein this chip engages with routing is disposed on this protective layer, and is electrically connected to this surface-treated layer by a routing.
13. chip-packaging structure as claimed in claim 10, wherein this chip is disposed on this protective layer in the mode of flip-chip bonded, and is electrically connected to this surface-treated layer by a projection.
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| CN201210185104.5A CN103474401B (en) | 2012-06-06 | 2012-06-06 | Carrying board structure and chip-packaging structure and preparation method thereof |
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Citations (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100196242B1 (en) * | 1989-04-05 | 1999-06-15 | 클라우스 포스, 게오르그 뮐러 | Method of making a hybrid semiconductor structure and the semiconductor structure thereof |
| US20080029894A1 (en) * | 2006-08-07 | 2008-02-07 | Phoenix Precision Technology Corporation | Flip-chip package substrate and a method for fabricating the same |
| CN101150075A (en) * | 2007-10-31 | 2008-03-26 | 日月光半导体制造股份有限公司 | Carrier and its making method |
| CN101393903A (en) * | 2007-09-18 | 2009-03-25 | 全懋精密科技股份有限公司 | Bearing board construction embedded with chip and fabrication method thereof |
| US20090169837A1 (en) * | 2007-12-26 | 2009-07-02 | Samsung Electro-Mechanics Co., Ltd. | Package substrate and manufacturing method thereof |
| CN102054814A (en) * | 2009-11-06 | 2011-05-11 | 欣兴电子股份有限公司 | Non-core layer package substrate and manufacturing method thereof |
| CN102065647A (en) * | 2009-11-17 | 2011-05-18 | 皓亮企业有限公司 | Method for manufacturing thick-film ceramic composite substrate |
| CN102376675A (en) * | 2010-08-04 | 2012-03-14 | 欣兴电子股份有限公司 | Packaging structure with embedded semiconductor element and manufacturing method thereof |
| CN102464294A (en) * | 2010-11-16 | 2012-05-23 | 矽品精密工业股份有限公司 | Packaging structure with micro electro mechanical element, and manufacturing method for packaging structure |
-
2012
- 2012-06-06 CN CN201210185104.5A patent/CN103474401B/en active Active
Patent Citations (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100196242B1 (en) * | 1989-04-05 | 1999-06-15 | 클라우스 포스, 게오르그 뮐러 | Method of making a hybrid semiconductor structure and the semiconductor structure thereof |
| US20080029894A1 (en) * | 2006-08-07 | 2008-02-07 | Phoenix Precision Technology Corporation | Flip-chip package substrate and a method for fabricating the same |
| CN101393903A (en) * | 2007-09-18 | 2009-03-25 | 全懋精密科技股份有限公司 | Bearing board construction embedded with chip and fabrication method thereof |
| CN101150075A (en) * | 2007-10-31 | 2008-03-26 | 日月光半导体制造股份有限公司 | Carrier and its making method |
| US20090169837A1 (en) * | 2007-12-26 | 2009-07-02 | Samsung Electro-Mechanics Co., Ltd. | Package substrate and manufacturing method thereof |
| CN102054814A (en) * | 2009-11-06 | 2011-05-11 | 欣兴电子股份有限公司 | Non-core layer package substrate and manufacturing method thereof |
| CN102065647A (en) * | 2009-11-17 | 2011-05-18 | 皓亮企业有限公司 | Method for manufacturing thick-film ceramic composite substrate |
| CN102376675A (en) * | 2010-08-04 | 2012-03-14 | 欣兴电子股份有限公司 | Packaging structure with embedded semiconductor element and manufacturing method thereof |
| CN102464294A (en) * | 2010-11-16 | 2012-05-23 | 矽品精密工业股份有限公司 | Packaging structure with micro electro mechanical element, and manufacturing method for packaging structure |
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