CN101150075A - Carrier and its making method - Google Patents
Carrier and its making method Download PDFInfo
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- CN101150075A CN101150075A CN200710168076.5A CN200710168076A CN101150075A CN 101150075 A CN101150075 A CN 101150075A CN 200710168076 A CN200710168076 A CN 200710168076A CN 101150075 A CN101150075 A CN 101150075A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/49105—Connecting at different heights
- H01L2224/49109—Connecting at different heights outside the semiconductor or solid-state body
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
Abstract
This invention relates to a manufacturing method for loaders, which first of all provides a first base board to form a circuit layer with several connection points on a surface of the board, then forms an anti-solder layer on the circuit layer to expose the conection points and after that joints a second base board with an aperture to the surface of the first board to constitute a loader, and the aperture should expose the anti-solder layer and the connection points of the first board, in which, space of circuit configuration can be increased and a chip in the aperture can be connected to the points directly to reduce the thickness of the package structure since the connection points are set in the aperture.
Description
Technical field
The invention relates to a kind of carrier, particularly a kind of carrier that increases the line configuring space.
Background technology
As shown in Figure 1, existing chip encapsulation construction 100 with appearance bug hole mainly comprises a carrier 110, one first chip 120, one second chip 130 and an adhesive body 140, this carrier 110 is made up of a substrate 111 and a fin 112 usually, this substrate 111 has a upper surface 113, an a lower surface 114 and an opening 115, this lower surface 114 that this fin 112 is pasted to this substrate 111 make this opening 115 of this substrate 111 form can ccontaining chip the appearance bug hole, this upper surface 113 of this substrate 111 is formed with several first contacts 116, several second contacts 117 and several balls pad 118, one back side 122 of this first chip 120 is attached at a surface 119 of this fin 112, this second chip 130 is attached at an active surface 121 of this first chip 120, several first bonding wires 150 electrically connect several first weld pads 123 of this first chip 120 and those first contacts 116 of this substrate 111, several second bonding wires 160 electrically connect several second weld pads 131 of this second chip 130 and those second contacts 117 of this substrate 111, this adhesive body 140 is formed at this upper surface 113 of this substrate to seal those first bonding wires 150 and those second bonding wires 160, and several soldered balls (not shown) are arranged at those ball pads 118 with the external circuits plate.Because this chip encapsulation construction 100 is the packaging structure of multicore sheet, therefore the setting of the configuration of circuit and chip is complicated, and because those first contacts 116 and those second contacts 117 all are formed at the same surface of this substrate 111, therefore those first bonding wires 150 need accurately control with the height of those second bonding wires 160, avoid those first bonding wires 150 and those second bonding wires 160 to contact with each other and cause short circuit, therefore the height of this adhesive body 140 can be higher, makes that the thickness of this chip encapsulation construction 100 is thicker.
Summary of the invention
Main purpose of the present invention is to provide a kind of and can reduces the thickness of chip encapsulation construction and simplify processing procedure and the carrier manufacture method of lifting manufacturing yield of products.
Another object of the present invention is to provide a kind of carrier that can reduce chip encapsulation construction thickness.
According to a kind of carrier manufacture method of the present invention, at first, one first substrate is provided, this first substrate has first through hole that a first surface, a second surface and run through this first surface and this second surface, this first surface is formed with a line layer and this first line layer has several contacts, this second surface is formed with a metal level, and this line layer electrically connects this metal level; Then, form a welding resisting layer on this line layer, this welding resisting layer also manifests those contacts; Afterwards, one second substrate is provided, this second substrate has one the 3rd surface, the 3rd surface and the opening on the 4th surface run through on one the 4th surface and, in this first surface of this first substrate, wherein this opening appears those contacts of this welding resisting layer and this first substrate with the 4th surface combination of this second substrate.
According to a kind of carrier of the present invention, it comprises:
One first substrate, it has a first surface and a second surface, and this first surface is formed with one first line layer, and this first line layer has several first contacts, and this second surface is formed with a metal level, and this first line layer electrically connects this metal level;
One first welding resisting layer, it covers this first line layer and manifests those first contacts; And one second substrate, it has one the 3rd surface, the 3rd surface and first opening on the 4th surface run through on one the 4th surface and, this second substrate is with the 4th surface this first surface towards this first substrate, and be incorporated on this first surface of this first substrate, and this first opening appears those first contacts of this first substrate.
Because those contacts of carrier of the present invention are positioned at this opening, it can increase the line configuring space, and the chip that is arranged in this opening can directly be electrically connected to those contacts, and the thickness of chip encapsulation construction is dwindled.In addition, because this carrier is formed in modes such as pressings by different substrates respectively, therefore can simplify processing procedure, and can distinctly test, to promote the fine ratio of product of this carrier.
Description of drawings
Fig. 1 is the schematic cross-section of existing chip encapsulation construction.
Fig. 2 A to Fig. 2 J is according to first specific embodiment of the present invention, the schematic cross-section in a kind of carrier manufacture process.
Fig. 3 is that one chip is arranged at the schematic cross-section of the formed chip encapsulation construction of this carrier according to first specific embodiment of the present invention.
Fig. 4 is according to second specific embodiment of the present invention, the schematic cross-section of another kind of carrier.
Fig. 5 is that chip and passive component are arranged at this schematic cross-section with carrier of opening according to second specific embodiment of the present invention.
Fig. 6 is that chip is arranged at the schematic cross-section that another kind has the carrier of opening according to the 3rd specific embodiment of the present invention.
Embodiment
See also shown in Fig. 2 A to Fig. 2 J, foundation first specific embodiment of the present invention discloses a kind of processing procedure of carrier 200, at first, sees also Fig. 2 A, and one first substrate 210 is provided, and this first substrate 210 can be multilayer (multi-layer) circuit substrate.This first substrate 210 has a first surface 211 and a second surface 212, in the present embodiment, this first substrate 210 has first through hole 213 that runs through this first surface 211 and this second surface 212 in addition, this first surface 211 is formed with first a patterned line layer 214, and this first line layer 214 has several first contacts 214a, this second surface 212 is formed with not patterned the first metal layer 215, perhaps, this the first metal layer 215 also can be patterned line layer, in the present embodiment, this the first metal layer 215 is not patterned, and this first line layer 214 electrically connects this first metal layer 215 by this through hole 213.Then, see also Fig. 2 B, form one first welding resisting layer 220 on this first line layer 214 and in this first through hole 213, this first welding resisting layer 220 also manifests those first contacts 214a, this first welding resisting layer 220 can screen painting or mode such as rotary coating form, this first welding resisting layer 220 can be green lacquer.Afterwards; see also Fig. 2 C; can form a protective layer 310 on this first line layer 214 and those first contacts 214a; this protective layer 310 is that those first contacts of covering 214a is oxidized to avoid those first contact 214a ingresss of air; this protective layer 310 can be green lacquer, photoresistance or adhesive tape; in addition; this first line layer 214 is formed with a black oxide layer 320 in addition; wherein these first surface 211 definition of this first substrate 210 have an assembly rest area A, this black oxide layer 320 to be formed at this assembly rest area A this first line layer 214 in addition.Then, see also Fig. 2 D, one second substrate 230 is provided, and this second substrate 230 is incorporated on this first substrate 210 in modes such as pressings, wherein should black oxide layer 320 have the effect that increases this second substrate 230 and 210 engaging forces of this first substrate, this second substrate 230 has one the 3rd surface 231, one the 4th surface 232 and at least one opening 233 that runs through the 3rd surface 231 and the 4th surface 232, in the present embodiment, the 3rd surface 231 is formed with one second line layer 234, this second line layer 234 is not patterned, and this second substrate 230 can be selected from the individual layer or double-deck copper clad laminate.Afterwards, with the 4th surface 232 of this second substrate 230 this first surface 211 towards this first substrate 210, and this second substrate 230 is incorporated on this first surface 211 of this first substrate 210, wherein this opening 233 of this second substrate 230 manifests those first contacts 214a of this first welding resisting layer 220 and this first substrate 210.In addition, before the step of carrying out this first substrate 210 of pressing and this second substrate 230, can remove this protective layer 310 that is covered on those first contacts 241a earlier.Then, see also Fig. 2 E, can form one and run through the 3rd surface 231 of this second substrate 230 and second through hole 235 of this second surface 212 of this first substrate 210, this second through hole 235 can machine drilling or Laser drill formation.Afterwards, see also Fig. 2 F, form a shielding layer 330 on the 3rd surface 231 of this second substrate 230, this shielding layer 330 covers this opening 233 and this second line layer 234.Then, see also Fig. 2 G, form one second metal level 240 in these second through hole, 235 inwalls to electrically connect this second line layer 234 and this first metal layer 215, in the present embodiment, this second metal level 240 is to form to electroplate, the material of this second metal level 240 is a copper, preferably, electroplating this second metal level 240 before the step of these second through hole, 235 inwalls, earlier form plating seed layer in these second through hole, 235 inwalls, be attached to this second through hole, 235 inwalls in order to this second metal level 240 in modes such as sputter, chemical vapour deposition (CVD) or electroless-platings.Then, see also Fig. 2 H, remove this shielding layer 330 to manifest those the first contacts 214a in this opening 233, and the step of carrying out this second line layer 234 of patterning is to form some second contact 234a, in addition, in this step, also simultaneously this first metal layer 215 of patterning to form some the 3rd contact 215a.At last, see also Fig. 2 I, form one second welding resisting layer 250 on this second line layer 234 and this first metal layer 215, this second welding resisting layer 250 manifests several second contact 234a of this second line layer 234 and several the 3rd contacts 215a of this first metal layer 215, and the material of this second welding resisting layer 250 can be identical with the material of this first welding resisting layer 220.Preferably, see also Fig. 2 J, form an electrodeposited coating 260 (for example nickel gold) in those first contacts 214a, those second contact 234a and those the 3rd contacts 215a, the bonding strength that it can prevent those first contacts 214a, those second contact 234a and those the 3rd contact 215a oxidations and increase those first contacts 214a, the second contact 234a and the 3rd contact 215a and projection or bonding wire.This carrier 200 of present embodiment is formed in modes such as pressings by this first substrate 210 and this second substrate 220 with this opening 233 respectively, therefore can simplify the processing procedure of this carrier 200, in addition, before steps such as pressing, can make in advance and test this first substrate 210 and this second substrate 220, therefore after the pressing step, can promote the fine ratio of product of this carrier 200.And because those first contacts 214a is positioned at this opening 233, so it can make the line configuring space of this carrier 200 increase.
See also Fig. 3, it is the packaging structure that a chip 340 is arranged at this opening 233 of this carrier 200, this chip 340 has an active surface 341, a back side 342 and several weld pads 343, those weld pads 343 are arranged at this active surface 341 of this chip 340, this back side 342 of this chip 340 is arranged in this opening 233, several bonding wires 350 electrically connect those weld pads 343 and are revealed in those first contacts 214a in this opening 233, therefore the height of those bonding wires 350 can reduce, and makes the integral thickness of chip encapsulation construction dwindle.
In addition, see also Fig. 4, it is second specific embodiment of the present invention, one carrier 400 includes one first substrate 410 and one second substrate 420, this first substrate 410 has a first surface 411 and a second surface 412, this first surface 411 is formed with first a patterned line layer 413, and this first line layer 413 has several first contacts 414, one first welding resisting layer 415 is formed on this first line layer 413, and manifest those first contacts 414, second substrate 420 has one the 3rd surface 421, one the 4th surface 422 and several run through first opening 423 on the 3rd surface 421 and the 4th surface 422,423 ', the 3rd surface 421 is formed with second a patterned line layer 424, and this second line layer 424 has several second contacts 425, one second welding resisting layer 426 covers this second line layer 424, and manifest those second contacts 425, this second substrate 420 is incorporated on this first substrate 410 in modes such as pressings, and those openings 423,423 ' manifests those first contacts 414 of this first welding resisting layer 415 and this first substrate 410, and this second line layer 424 can a through hole A and 413 electric connections of this first line layer.See also Fig. 5, in this first opening 423, be provided with one first chip 430, in this first opening 423 ', be provided with a passive component 440, this first chip 430 has several projections 431, those first contacts 414 in those projections 431 and this first opening 423 electrically connect, this passive component 440 is electrically connected at those first contacts 414 in this first opening 423 ', in addition, but one second chip, 450 storehouses are arranged at the brilliant back of this first chip 430, and electrically connect second contact 425 of this second chip 450 and this second substrate 420 with several bonding wires 460.One adhesive body 470 is filled in this first opening 423, with this first chip 430 of seal protection, this second chip 450 and those bonding wires 460.Have those first openings 423 in the present embodiment, this carrier 400 of 423 ' is formed in modes such as pressings by this first substrate 410 and this second substrate 420 with those openings 423 respectively, therefore can simplify the processing procedure of this carrier 400, in addition, before steps such as pressing, can make in advance and test this first substrate 410 and this second substrate 420, therefore after the pressing step, can promote the fine ratio of product of this carrier 400, and make the line configuring space of this carrier 400 increase, and those openings 423,423 ' can ccontaining different electronic building brick, to reduce the thickness of semiconductor packaging structure.
See also Fig. 6, it is the 3rd specific embodiment of the present invention, one carrier 500 includes one first substrate 510 and one second substrate 520, this first substrate 510 has a first surface 511 and a second surface 512, this first surface 511 is formed with first a patterned line layer 513, and this first line layer 513 has several first contacts 514, one first welding resisting layer 515 is formed on this first line layer 513, and manifest those first contacts 514, this second substrate 520 has 521 and 1 the 4th surface 522, one the 3rd surface, the 4th surface 522 is formed with second a patterned line layer 524, and this second line layer 524 has several second contacts 525, one second welding resisting layer 526 covers this second line layer 524, and manifest those second contacts 525, this second substrate 520 is incorporated on this first substrate 510 in modes such as pressings, and this first line layer 513 and this second line layer 524 are electrically connected, in the present embodiment, this second substrate 520 has one and runs through the 3rd surface 521 and first opening 523 on the 4th surface 522 and those first contacts 514 that this first opening 523 manifests this first substrate 510.This first substrate 510 has second opening 516 that runs through this first surface 511 and this second surface 512, this second opening 516 manifests second contact 525 of this second substrate 520, in this first opening 523, be provided with one first chip 530, in this second opening 516, be provided with one second chip 540, this first chip 530 has several first projections 531, and those first contacts 514 in those first projections 531 and this first opening 523 electrically connect.This second chip 540 has several second projections 541, and those second contacts 525 in those second projections 541 and this second opening 516 electrically connect.
Claims (11)
1. carrier manufacture method is characterized in that comprising following steps:
One first substrate is provided, this first substrate has first through hole that a first surface, a second surface and run through this first surface and this second surface, this first surface is formed with one first line layer and this first line layer has several first contacts, this second surface is formed with a first metal layer, and this first line layer electrically connects this first metal layer;
Form one first welding resisting layer on this first line layer, this first welding resisting layer manifests those first contacts; And
One second substrate is provided, this second substrate has one the 3rd surface, the 3rd surface and the opening on the 4th surface run through on one the 4th surface and, in this first surface of this first substrate, wherein this opening appears those first contacts of this first welding resisting layer and this first substrate with the 4th surface combination of this second substrate.
2. carrier manufacture method as claimed in claim 1 is characterized in that: this first surface definition of this first substrate has an assembly rest area, and this first line layer beyond this assembly rest area forms a black oxide layer.
3. carrier manufacture method as claimed in claim 1 is characterized in that: its also be included in aforementioned one second substrate is provided and first substrate combines after, more comprise following steps:
Form one second line layer in the 3rd surface;
Form a shielding layer in the 3rd surface of this second substrate to cover this opening;
Form one second through hole, the 3rd surface that this second through hole runs through this second substrate is with this second surface of this first substrate and electrically connect this first metal layer and this second line layer;
Remove this shielding layer to appear those first contacts in this opening;
This second line layer of patterning also forms several second contacts;
Form one second welding resisting layer in this second line layer of patterning and appear those second contacts;
Form an electrodeposited coating in those second contacts.
4. carrier manufacture method as claimed in claim 1 is characterized in that: this first metal layer has several the 3rd contacts, and after first substrate and second substrate, it comprises that also formation one electrodeposited coating is in those first contacts and those the 3rd contacts.
5. carrier, it comprises one first substrate, and it has a first surface and a second surface; And one second substrate, it has one the 3rd surface, one the 4th surface; It is characterized in that: the first surface of this first substrate is formed with one first line layer, and this first line layer has several first contacts, and this second surface is formed with a metal level, and this first line layer electrically connects this metal level; This carrier also comprises one first welding resisting layer, and it covers this first line layer and manifests those first contacts; This second substrate comprises that one runs through first opening on the 3rd surface and the 4th surface, this second substrate is with the 4th surface this first surface towards this first substrate, and be incorporated on this first surface of this first substrate, and this first opening appears those first contacts of this first substrate.
6. carrier as claimed in claim 5 is characterized in that: the 3rd surface is formed with one second line layer, and this second line layer has several second contacts.
7. carrier as claimed in claim 6 is characterized in that: it includes a through hole in addition, and this through hole electrically connects this first line layer and this second line layer.
8. carrier as claimed in claim 6 is characterized in that: this first substrate has second opening that runs through this first surface and this second surface in addition, and this second opening appears those second contacts of this second substrate.
9. carrier as claimed in claim 6 is characterized in that: it includes one second welding resisting layer in addition, and this second welding resisting layer is formed at this second line layer and appears second contact.
10. carrier as claimed in claim 5 is characterized in that: this first substrate is multilayer (multi-layer) circuit substrate; This second substrate is selected from the individual layer or double-deck copper clad laminate.
11. carrier as claimed in claim 5 is characterized in that: this first surface definition of this first substrate has an assembly rest area, and this first line layer beyond this assembly rest area has a black oxide layer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN200710168076.5A CN100521124C (en) | 2007-10-31 | 2007-10-31 | Carrier and its making method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN200710168076.5A CN100521124C (en) | 2007-10-31 | 2007-10-31 | Carrier and its making method |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN101150075A true CN101150075A (en) | 2008-03-26 |
| CN100521124C CN100521124C (en) | 2009-07-29 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN200710168076.5A Active CN100521124C (en) | 2007-10-31 | 2007-10-31 | Carrier and its making method |
Country Status (1)
| Country | Link |
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| CN (1) | CN100521124C (en) |
Cited By (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101916751A (en) * | 2010-07-30 | 2010-12-15 | 日月光半导体制造股份有限公司 | Packaging structure and manufacture method thereof |
| CN101594730B (en) * | 2008-05-26 | 2012-01-04 | 欣兴电子股份有限公司 | Circuit board with conductive structure |
| CN101789383B (en) * | 2009-01-23 | 2012-03-21 | 欣兴电子股份有限公司 | Method for making packaging substrate with recess structure |
| CN102745639A (en) * | 2011-04-22 | 2012-10-24 | 欣兴电子股份有限公司 | Micro electro mechanical bearing piece and manufacturing method thereof |
| CN101853818B (en) * | 2009-04-02 | 2013-09-11 | 欣兴电子股份有限公司 | Packaging substrate structure with recess and manufacturing method thereof |
| CN103474401A (en) * | 2012-06-06 | 2013-12-25 | 欣兴电子股份有限公司 | Support plate structure and chip packaging structure and manufacturing method thereof |
| CN104867906A (en) * | 2014-02-20 | 2015-08-26 | 矽品精密工业股份有限公司 | Semiconductor package and fabrication method thereof |
| CN105097764A (en) * | 2015-06-30 | 2015-11-25 | 南通富士通微电子股份有限公司 | Package structure |
| CN106158808A (en) * | 2015-03-25 | 2016-11-23 | 恒劲科技股份有限公司 | Electronic packing piece and preparation method thereof |
| CN106815549A (en) * | 2015-11-30 | 2017-06-09 | 矽品精密工业股份有限公司 | Package structure and method for fabricating the same |
| CN111968949A (en) * | 2020-08-27 | 2020-11-20 | 青岛歌尔微电子研究院有限公司 | Chip packaging process and packaged chip |
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2007
- 2007-10-31 CN CN200710168076.5A patent/CN100521124C/en active Active
Cited By (19)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101594730B (en) * | 2008-05-26 | 2012-01-04 | 欣兴电子股份有限公司 | Circuit board with conductive structure |
| CN101789383B (en) * | 2009-01-23 | 2012-03-21 | 欣兴电子股份有限公司 | Method for making packaging substrate with recess structure |
| CN101853818B (en) * | 2009-04-02 | 2013-09-11 | 欣兴电子股份有限公司 | Packaging substrate structure with recess and manufacturing method thereof |
| CN101916751B (en) * | 2010-07-30 | 2012-05-23 | 日月光半导体制造股份有限公司 | Packaging structure and manufacture method thereof |
| CN101916751A (en) * | 2010-07-30 | 2010-12-15 | 日月光半导体制造股份有限公司 | Packaging structure and manufacture method thereof |
| CN102745639B (en) * | 2011-04-22 | 2015-09-09 | 欣兴电子股份有限公司 | Micro electronmechanical bearing part and method for making thereof |
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