CN101393903A - Bearing board construction embedded with chip and fabrication method thereof - Google Patents
Bearing board construction embedded with chip and fabrication method thereof Download PDFInfo
- Publication number
- CN101393903A CN101393903A CNA200710152840XA CN200710152840A CN101393903A CN 101393903 A CN101393903 A CN 101393903A CN A200710152840X A CNA200710152840X A CN A200710152840XA CN 200710152840 A CN200710152840 A CN 200710152840A CN 101393903 A CN101393903 A CN 101393903A
- Authority
- CN
- China
- Prior art keywords
- chip
- support plate
- aluminium
- embedded
- opening
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L24/19—Manufacturing methods of high density interconnect preforms
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/04105—Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/12105—Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L2224/19—Manufacturing methods of high density interconnect preforms
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
- H01L2924/1815—Shape
- H01L2924/1816—Exposing the passive side of the semiconductor or solid-state body
- H01L2924/18162—Exposing the passive side of the semiconductor or solid-state body of a chip with build-up interconnect
Landscapes
- Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Insulated Metal Substrates For Printed Circuits (AREA)
Abstract
The invention relates to a carrier structure, in which a chip is embedded, and a manufacturing method thereof. The structure comprises: a first aluminum carrier provided with a first opening; a second aluminum carrier provided with a second opening which is in the position corresponding to the position of the first opening; a dielectric layer clamped between the first aluminum carrier and the second aluminum carrier; a chip, which is provided with an active surface and embedded in the first opening and the second opening; a plurality of electrode pads arranged on the active surface of the chip; and a line layer-adding structure, which is arranged on the upper surface of the first aluminum carrier, wherein the active surface of the chip and the surfaces of the electrode pads are provided with at least a conductive structure corresponding to the electrode pads, and the conductive structure is electrically connected with the electrode pads.
Description
Technical field
The present invention relates to a kind of carrying plate structure and manufacture method thereof that is embedded with chip, refer to especially a kind of improve asymmetric increase the plate prying situation that produced of layer be embedded with carrying plate structure of chip and preparation method thereof.
Background technology
Flourish along with electronic industry, electronic product also progresses into multi-functional, high performance R﹠D direction.For satisfying the encapsulation requirement of the high integration of semiconductor package part (Integration) and microminiaturized (Miniaturization), the circuit board that provides a plurality of main passive devices and circuit to connect, also develop into multi-layer sheet by lamina gradually, so that under limited space, cooperate integrated circuit (Integrated circuit) demand of high electron density by available wiring area on interlayer interconnection technique (Interlayer connection) the expansion circuit board.
But the processing procedure of general semiconductor device is at first produced the chip support plate that is applicable to this semiconductor device by the chip support plate manufacturer, as substrate or lead frame.Those chip support plates being transferred to the semiconductor packages dealer afterwards puts crystalline substance, pressing mold and plants processing procedures such as ball again.At last, can finish the semiconductor device of the required electric function of client.Therefore relate to different manufacturers during this time, not only complex steps and integration of interface are difficult in actual manufacture process.Moreover when desiring to change the function design as if client, it is complicated especially with concordant bedding that it involves change, also do not meet requirement change elasticity and economic benefit.
The conventional semiconductor packages structure is that semiconductor chip is sticked in substrate top surface in addition, carries out routing and engages (wire bonding) or chip bonding (Flip chip) encapsulation, plants with the tin ball to electrically connect in the back side of substrate again.So, though can reach the purpose of high pin number.But when high frequency more uses or during high speed operation, its usefulness that will produce electrical characteristic because of the lead access path is long can't promote, and limits to some extent.In addition, because of conventional package needs connecting interface repeatedly, relatively increase the complexity of processing procedure.
For this reason, many researchs are adopted in the chip buried base plate for packaging, and this chip that is embedded in base plate for packaging can be directly and the exterior electrical components conducting, in order to shortening electrical conducting path, and can reduce the ability of signal loss, signal distortion and lifting high speed operation.
The carrying plate structure that is embedded with chip comprises as shown in Figure 1: a support plate 101, and this support plate 101 is formed with opening; One chip 102, this chip 102 is placed in this opening, and the active surface of this chip 102 is formed with a plurality of electronic padses 103; One is formed on this support plate that is embedded with chip 102 101, and the corresponding protective layer 104 that manifests electronic pads 103; A plurality of electronic pads 103 lip-deep metal levels 105 that are formed at; An and circuit layer reinforced structure 106 that is formed at this loading plate 101 and this chip 102 surfaces.Wherein, circuit layer reinforced structure 106 is formed at chip 102 and support plate 101 surfaces, and electrically connects the electronic pads 103 of this support plate 101 and chip 102.
At present, to be usually used in being embedded with the material of support plate 101 of the carrying plate structure of chip be copper or BT resin (Bismaleimide Triazine Resin) to industry.Yet, when being the material of support plate 101 with the above-mentioned material, the carrying plate structure that is embedded with chip forms under the situation of circuit layer reinforced structure 106 at single face, tend to because circuit increases aspect and non-ly increases the aspect unbalanced stress and produce plate prying problem, cause produce being difficult for, and its finished product also can yield be on the low side, reliability is not good because the plate prying is excessive.
Therefore, increasing the plate prying situation that layer produces in order to reduce the loading plate that is embedded with chip because of single face, and improve the production yield, is that the support plate of material can not satisfy instructions for use with copper or BT resin.
Summary of the invention
Shortcoming in view of above-mentioned prior art, the objective of the invention is to overcome the deficiencies in the prior art and defective, a kind of carrying plate structure that is embedded with chip is proposed, and a kind of manufacture method that is embedded with the carrying plate structure of chip, the loading plate that is embedded with chip with reduction increases the plate prying situation that layer produces because of single face, and improve and produce yield, satisfy instructions for use.
For reaching above-mentioned purpose, the invention provides a kind of carrying plate structure that is embedded with chip, comprising: one first aluminium support plate has one first opening; One second aluminium support plate has one second opening, and the position of this second opening is to position that should first opening; One dielectric layer is folded between this first aluminium support plate and this second aluminium support plate; One chip, this chip embedding bury and have an active surface in this first opening and this second opening; A plurality of electronic padses, this electronic pads are disposed at this active surface of this chip; An and circuit layer reinforced structure, this circuit layer reinforced structure is disposed at this first aluminium upper surface of said carrier plate, the active surface of this chip and the surface of this electronic pads, wherein, this circuit layer reinforced structure has a plurality of conductive structures, and at least one this conductive structure is electrically connected at this electronic pads.
That is to say that because industry is with copper or BT resin (Bismaleimide Triazine Resin) during as the support plate of the carrying plate structure that is embedded with chip, loading plate usually produces serious plate prying situation under the situation that single face increases layer.Therefore, the present invention can obviously improve the situation of plate prying with " aluminium " or " aluminium alloy " carrier plate material as the carrying plate structure that is embedded with chip, and solves industry when production is embedded with the carrying plate structure of chip, the permanent problem that exists.
In addition, the present invention improves outside the plate prying situation except with " aluminium " or " aluminium alloy " carrier plate material as the carrying plate structure that is embedded with chip.The different execution modes (consulting embodiment one to four) of also can arranging in pairs or groups further improve the plate prying of loading plate, make loading plate present smooth state.
The carrying plate structure that is embedded with chip of the present invention, wherein, the material of this first aluminium support plate and the second aluminium support plate can be aluminum or aluminum alloy, is preferably aluminium alloy.In addition, the carrying plate structure that is embedded with chip of the present invention, wherein, this first aluminium upper surface of said carrier plate or lower surface optionally are formed with an alumina layer.Same, this second aluminium upper surface of said carrier plate or lower surface optionally are formed with an alumina layer.Aluminium oxide/aluminium composite material the support plate that forms by surface oxidation treatment can increase the rigidity of support plate, therefore, can be used as the core base of embedded chip encapsulation, can further improve the plate prying situation that produces because of asymmetric layer reinforced structure.
The carrying plate structure that is embedded with chip of the present invention, wherein the alumina layer thickness of this first aluminium support plate and the second aluminium support plate does not have special restriction, decide on needed rigidity of loading plate or toughness, and the control method of this alumina layer thickness also do not have special restriction, can reach by different method for oxidation or condition.
The carrying plate structure that is embedded with chip of the present invention, wherein, the thickness of this first aluminium support plate and the second aluminium support plate does not limit, and is preferably the thickness that the surface is formed with the first aluminium support plate of circuit layer reinforced structure, less than the thickness of the second aluminium support plate.Because, the carrying plate structure that is embedded with chip do not form as yet before the circuit layer reinforced structure can be slightly to the direction prying of the second aluminium support plate, and forming after circuit increases into structure, two aluminium support plates can offset because of circuit increase the back stress of layer, so that it is more smooth to be embedded with the carrying plate structure of chip.
The carrying plate structure that is embedded with chip of the present invention, wherein, the material of this electronic pads is not limit and is used any metal, preferably is an aluminum metal or copper metal.
The carrying plate structure that is embedded with chip of the present invention, wherein, also can be filled with one between this first aluminium support plate and this chip and between this second aluminium support plate and this chip sticks together material or is filled in the gap that chip and two aluminium support plates are generated, to fix this chip in this first opening and second opening because of extruding by the aforementioned dielectric layer that is located between two aluminium support plates.
The carrying plate structure that is embedded with chip of the present invention, wherein, this circuit layer reinforced structure includes at least one insulating barrier, is stacked and placed on line layer and a plurality of conductive structure on this insulating barrier, and at least one this conductive structure is electrically connected to this electronic pads.
And, the insulating layer material of this circuit layer reinforced structure does not limit, preferably be selected from by ABF (Ajinomoto Build-up Film), two along butyryl diacid acid imide/three nitrogen traps (BT, Bismaleimide triazine), phenylbenzene cyclobutadiene (benzocylobutene at least one; BCB), liquid crystal polymer (Liquid Crystal Polymer), pi (Polyimide; PI), any group that forms in the materials such as polyvinylether (Poly (phenylene ether)), polytetrafluoroethylene (Poly (tetra-fluoroethylene)), aramid fiber (Aramide), epoxy resin and glass fibre.The material of this line layer and this conductive structure does not limit, and preferably is copper, tin, nickel, chromium, titanium, copper/evanohm or tin/lead alloy.
The carrying plate structure that is embedded with chip of the present invention also includes a plurality of solder projections, and has at least a conductive structure to be connected to this solder projection in this circuit layer reinforced structure.
The carrying plate structure that is embedded with chip of the present invention, wherein the alumina layer thickness of this first aluminium support plate and the second aluminium support plate does not have special restriction, decide on needed rigidity of loading plate or toughness, and the control method of this alumina layer thickness also do not have special restriction, can reach by different method for oxidation or condition.
The carrying plate structure that is embedded with chip of the present invention, wherein, the thickness of this first aluminium support plate and the second aluminium support plate does not limit, and is preferably the thickness that the surface is formed with the first aluminium support plate of circuit layer reinforced structure, less than the thickness of the second aluminium support plate.
In addition, for reaching above-mentioned purpose, the present invention also provides a kind of manufacture method that is embedded with the loading plate of chip, and it comprises step: A. provides one first aluminium support plate and one second aluminium support plate; B. form one first opening in this first aluminium support plate, and form one second opening in this second aluminium support plate, wherein the position of this second opening is to position that should first opening; C. between this first aluminium support plate and this second aluminium support plate, a dielectric layer is set; D. a chip is embedded in this first opening and this second opening, wherein, this active surface of this chip has a plurality of electronic padses, this first aluminium support plate of pressing subsequently combines two aluminium support plates with this second aluminium support plate, push simultaneously this dielectric layer make its be filled to this first aluminium support plate, the second aluminium support plate, and this chip between the gap, to fix this chip in this first opening and this second opening; And E. forms a circuit layer reinforced structure in the active surface of this first aluminium upper surface of said carrier plate, this chip and the surface of this electronic pads, wherein, this circuit layer reinforced structure have at least one insulating barrier, be stacked and placed on line layer on this insulating barrier, with a plurality of conductive structures, and at least one this conductive structure is electrically connected at this electronic pads.
Method of the present invention as the carrier plate material that is embedded with the carrying plate structure of chip, can obviously be improved the situation of plate prying by " aluminium " or " aluminium alloy ", and solve industry when production is embedded with the carrying plate structure of chip, the permanent problem that exists.
The manufacture method that is embedded with the loading plate of chip of the present invention, wherein, the material of this first aluminium support plate and the second aluminium support plate can be aluminum or aluminum alloy, is preferably aluminium alloy.In addition, the manufacture method that is embedded with the loading plate of chip of the present invention, wherein, this first aluminium upper surface of said carrier plate or lower surface optionally are formed with an alumina layer.Same, this second aluminium upper surface of said carrier plate or lower surface optionally are formed with an alumina layer.This surface is formed with the first aluminium support plate of aluminium oxide or the second aluminium support plate can form by any mode of oxidizing, preferablely forms in the anodic oxidation mode.Aluminium oxide/aluminium composite material the support plate that forms by surface oxidation treatment can increase the rigidity of support plate, and therefore, the core base that can be used as the embedded chip encapsulation is further improved because of the asymmetric layer plate prying situation that is produced that increase.
The manufacture method that is embedded with the loading plate of chip of the present invention, wherein, the material of this electronic pads is not limit and is used any metal, preferably is an aluminum metal or copper metal.
The manufacture method that is embedded with the loading plate of chip of the present invention, wherein, in the step of making this circuit layer reinforced structure, the material of this insulating barrier does not limit, be preferably at least one being selected from by ABF (Ajinomoto Build-up Film), two along butyryl diacid acid imide/three nitrogen traps (BT, Bismaleimide triazine), phenylbenzene cyclobutadiene (benzocylobutene; BCB), liquid crystal polymer (Liquid Crystal Polymer), pi (Polyimide; PI), any group that forms in the materials such as polyvinylether (Poly (phenylene ether)), polytetrafluoroethylene (Poly (tetra-fluoroethylene)), aramid fiber (Aramide), epoxy resin and glass fibre.
The manufacture method that is embedded with the loading plate of chip of the present invention, wherein, in the step of making this circuit layer reinforced structure, the material of this electroplated metal layer there is no particular restriction, preferably be copper, tin, nickel, chromium, palladium, titanium, tin/lead or its alloy, more preferably, be copper.
Again, the present invention provides a kind of manufacture method that is embedded with the loading plate of chip again, and its step comprises: A. provides one first aluminium support plate and one second aluminium support plate; B. pressing one dielectric layer is between this first aluminium support plate and this second aluminium support plate, and forms a clad aluminum support plate; C. form an opening in this clad aluminum support plate; D. a chip is embedded and be fixed in this opening, wherein, the active surface of this chip has a plurality of electronic padses; And E. is in the active surface of this first aluminium upper surface of said carrier plate, this chip, form a circuit layer reinforced structure with the surface of this electronic pads, wherein, this circuit layer reinforced structure have at least one insulating barrier, be stacked and placed on line layer on this insulating barrier, with a plurality of conductive structures, and at least one this conductive structure is electrically connected at this electronic pads.
Method of the present invention as the carrier plate material that is embedded with the carrying plate structure of chip, can obviously be improved the situation of plate prying by " aluminium " or " aluminium alloy ", and solve industry when production is embedded with the carrying plate structure of chip, the permanent problem that exists.
The manufacture method that is embedded with the loading plate of chip of the present invention, wherein, step (D) also can be inserted one and stick together the gap of material between this chip and this opening, to fix this chip after chip embedding and being fixed in this opening.
The manufacture method that is embedded with the loading plate of chip of the present invention, wherein, the material of this first aluminium support plate and the second aluminium support plate can be aluminum or aluminum alloy, is preferably aluminium alloy.In addition, the manufacture method that is embedded with the loading plate of chip of the present invention, wherein, this first aluminium upper surface of said carrier plate or lower surface optionally are formed with an alumina layer.Same, this second aluminium upper surface of said carrier plate or lower surface optionally are formed with an alumina layer.This surface is formed with the first aluminium support plate of aluminium oxide or the second aluminium support plate can form by any mode of oxidizing, preferablely forms in the anodic oxidation mode.Aluminium oxide/aluminium composite material the support plate that forms by surface oxidation treatment can increase the rigidity of support plate, and therefore, the core base that can be used as the embedded chip encapsulation can further be improved because of the asymmetric layer plate prying situation that is produced that increase.
The manufacture method that is embedded with the loading plate of chip of the present invention, wherein, the material of this electronic pads is not limit and is used any metal, preferably is an aluminum metal or copper metal.
The manufacture method that is embedded with the loading plate of chip of the present invention, wherein, in the step of making this circuit layer reinforced structure, the material of this insulating barrier does not limit, be preferably at least one being selected from by ABF (Ajinomoto Build-up Film), two along butyryl diacid acid imide/three nitrogen traps (BT, Bismaleimide triazine), phenylbenzene cyclobutadiene (benzocylobutene; BCB), liquid crystal polymer (Liquid Crystal Polymer), pi (Polyimide; PI), any group that forms in the materials such as polyvinylether (Poly (phenylene ether)), polytetrafluoroethylene (Poly (tetra-fluoroethylene)), aramid fiber (Aramide), epoxy resin and glass fibre.
The manufacture method that is embedded with the loading plate of chip of the present invention, wherein, in the step of making this circuit layer reinforced structure, the material of this electroplated metal layer there is no particular restriction, preferably be copper, tin, nickel, chromium, palladium, titanium, tin/lead or its alloy, more preferably, be copper.
Description of drawings
Fig. 1 is the generalized section that has the electric connection structure of the loading plate that is embedded with chip now;
Fig. 2 a to 2e is the generalized section of manufacture method of the loading plate that is embedded with chip of a preferred embodiment of the present invention;
Fig. 3 a to 3c is the generalized section of manufacture method of the circuit layer reinforced structure of a preferred embodiment of the present invention;
Fig. 4 a to 4d is the generalized section of the manufacture method of the loading plate that is embedded with chip of another preferred embodiment of the present invention;
Fig. 5 a to 5e is the present invention's generalized section of the manufacture method of the loading plate that is embedded with chip of a preferred embodiment again,
Fig. 6 a to 6d is the generalized section of the manufacture method of the loading plate that is embedded with chip of the another preferred embodiment of the present invention.
Symbol description among the figure
10,40,50,60 first aluminium support plates 11,41,51,61 second aluminium support plates
12,52 first openings, 13,53 second openings
14,42,54,62 dielectric layers, 15,45,55,65 upper surfaces
21 chips, 22 active surfaces
23 electronic padses, 24 non-active surfaces
25 stick together material
31 circuit layer reinforced structures, 32 insulating barriers
33 insulating barrier openings, 34 patterning resistance layers
35 resistance layer openings, 36 electroplated metal layers
37 line layers, 38 conductive structures
39 solder projections, 43,63 compound support plates
44,64 openings, 56,66 alumina layers
57,67 aluminium laminations, 101 support plates
102 chips, 103 electronic padses
104 protective layers, 105 metal levels
106 circuit layer reinforced structures, 39 ' patterned anti-soldering layer
Embodiment
Embodiment 1
See also Fig. 2 a to 2e, be the generalized section of the carrying plate structure method for making that is embedded with chip of present embodiment.
Shown in Fig. 2 a, at first provide one first aluminium support plate 10 and one second aluminium support plate 11.This first aluminium support plate 10 and the second aluminium support plate 11 respectively are formed with one first opening 12 and second opening 13, and the position of this second opening is also to position that should first opening.
Thereupon, shown in Fig. 2 b, then, provide a dielectric layer 14 in this first aluminium support plate 10, and this second aluminium support plate 11 between, then shown in Fig. 2 c, a chip 21 of having finished wafer integrated circuit manufacture process and excision forming is embedded in first opening 12 and second opening 13 imposes pressing again.Wherein, have a plurality of electronic padses 23 on the active surface 22 of chip 21, the material of this electronic pads 23 is a copper.This dielectric layer 14 is in the process of pressing, and dielectric layer 14 can be fixed in first opening 12 and second opening 13 chip 21 by overflowing between this first aluminium support plate 10 and this second aluminium support plate 11, fixes this first aluminium support plate 10 and this second aluminium support plate 11 simultaneously.This dielectric layer 14 is folded between this first aluminium support plate 10, this second aluminium support plate 11 and this chip 21 at last, and its structure is shown in Fig. 2 c.In the present embodiment, the non-active surface 24 exposed chip coolings that help of chip 21.
In addition, in the present embodiment, the thickness of the first aluminium support plate 10 (D1) is less than the thickness (D2) of the second aluminium support plate 11.So the carrying plate structure that is embedded with chip does not form (shown in Fig. 2 d) before the circuit layer reinforced structure 31 as yet, this loading plate can omit downward prying.
After finishing above-mentioned steps, shown in Fig. 2 e, form a circuit layer reinforced structure 31 in the upper surface 15 of the first aluminium support plate 10, the active surface 22 and electronic pads 23 surfaces of chip 21.The formation method of this circuit layer reinforced structure 31 as shown in Figure 3, lower surface 15 in the second aluminium support plate 11, the active surface 22 of chip 21 forms an insulating barrier 32 with electronic pads 23 surfaces, the material of this insulating barrier 32 is ABF (Ajinomoto Build-up Film) material, and form a plurality of insulating barrier openings 33 in this insulating barrier 32 with laser drill, wherein at least one insulating barrier opening is corresponding to electronic pads 23 positions of chip 21, just when utilize the technology of laser drill, also need carry out de-smear (De-smear) operation to remove the glue slag that is residued in because of holing in this dielectric layer opening.Then, form patterning resistance layer 34 on insulating barrier 32, this patterning resistance layer 34 forms a plurality of resistance layer openings 35 with exposure, visualization way, and at least one resistance layer opening 35 corresponds to the position of the electronic pads 23 of this chip 21.Then, electroplate one deck electroplated metal layer 36, remove this resistance layer 34 again in these a plurality of resistance layer openings 35.This circuit layer reinforced structure 31 can use and increase layer technology according to the stacked structure that gets on to make multilayer of the needed number of plies.Circuit layer reinforced structure 31 shown in Fig. 2 d uses and increases layer technology according to the stacked structure that gets on to make multilayer of the needed number of plies, wherein, and the conductive structure 38 that this electroplated metal layer 36 includes line layer 37 and is connected with the electronic pads 23 of chip 21.
At last, form patterned anti-soldering layer 39 ' in this layer reinforced structure 31 surfaces again, and form a plurality of solder projections 39, promptly and finish the loading plate that is embedded with chip of present embodiment in the electric connection pad place that this patterned anti-soldering layer 39 ' manifests layer reinforced structure 31.
The carrying plate structure that is embedded with chip of present embodiment is that single face increases layer, therefore, the carrying plate structure that is embedded with chip does not form before the circuit layer reinforced structure 31 (shown in Fig. 2 e) as yet can slightly downward prying, and after the formation circuit increases into structure 31 (shown in Fig. 2 e), prying can turn back, and forms the smooth carrying plate structure that is embedded with chip.
Embodiment two
See also Fig. 4 a to 4d, be the generalized section of the carrying plate structure method for making that is embedded with chip of present embodiment.
Shown in Fig. 4 a, at first provide one first aluminium support plate 40 and one second aluminium support plate 41.Provide a dielectric layer 42 again between this first aluminium support plate 40 and the second aluminium support plate 41, and impose pressing.Thus, dielectric layer 42 can be fixed this first aluminium support plate 40 and the second aluminium support plate 41, and forms a compound support plate 43.
Thereupon, shown in Fig. 4 b, form one in this compound support plate 43 thereafter and run through opening 44.Then, a chip 21 of having finished wafer integrated circuit manufacture process and excision forming is embedded in the opening 44 of compound support plate 43.This chip 21 has a plurality of electronic padses 23 on the active surface 22 of chip 22, the material of this electronic pads is a copper.Then, will stick together material 25 and insert space between compound support plate 43 and the chip 21, and make chip 21 be fixed in the opening 44 of compound support plate 43 its structure such as Fig. 4 c.Wherein this sticks together material 25 and can be epoxy resin.And in the present embodiment, the non-active surface 24 exposed chip coolings that help of chip 21.
In addition, in the present embodiment, the thickness of the first aluminium support plate 40 (D1) is less than the thickness (D2) of the second aluminium support plate 41.So the carrying plate structure that is embedded with chip does not form (shown in Fig. 4 c) before the circuit layer reinforced structure 31 as yet, this loading plate can omit downward prying.
After finishing above-mentioned steps, shown in Fig. 4 d, form a circuit layer reinforced structure 31 in the upper surface 45 of the first aluminium support plate 40, the active surface 22 and electronic pads 23 surfaces of chip 21.The conductive structure 38 that this circuit layer reinforced structure 31 includes line layer 37 and is connected with the electronic pads 23 of chip 21, its formation method is identical with embodiment one.At last, form patterned anti-soldering layer 39 ' in this layer reinforced structure 31 surfaces again, and form a plurality of solder projections 39, promptly and finish the loading plate that is embedded with chip of present embodiment in the electric connection pad place that this patterned anti-soldering layer 39 ' manifests layer reinforced structure 31.
The carrying plate structure that is embedded with chip of present embodiment is that single face increases layer, therefore, the carrying plate structure that is embedded with chip does not form before the circuit layer reinforced structure 31 (shown in Fig. 4 c) as yet can slightly downward prying, and after the formation circuit increases into structure 31, prying can turn back, and forms the smooth carrying plate structure that is embedded with chip.
Embodiment three
The manufacture method and the embodiment one of the loading plate that is embedded with chip of present embodiment are closely similar, except the first aluminium support plate and the second aluminium upper surface of said carrier plate and lower surface all peroxidating respectively be formed with the alumina layer, all the other steps and embodiment one are roughly the same.
See also Fig. 5 a to 5e, be the generalized section of the carrying plate structure method for making that is embedded with chip of present embodiment.
Shown in Fig. 5 a, at first provide one first aluminium support plate 50 and one second aluminium support plate 51.This first aluminium support plate 50 and the second aluminium support plate 51 are placed an electrolysis tank, carry out oxidation reaction, make the upper surface and the equal oxidation of lower surface of the first aluminium support plate 50 and one second aluminium support plate 51 form alumina layer 56, and be gripped with an aluminium lamination 57 naturally in the middle of the two-layer aluminium oxide 56.In the present embodiment, the first aluminium support plate 50 and one second aluminium support plate 51 place an electrolysis tank, carry out anodic oxidation reactions, and by adjusting anodizing time, come the thickness of controlled oxidation aluminium lamination 56.
Then, shown in Fig. 5 b, respectively be formed with one first opening 52 and second opening 53, and the position of this second opening is also to position that should first opening in this first aluminium support plate 50 and the second aluminium support plate 51.Then, a dielectric layer 54 is set between this first aluminium support plate 50 and this second aluminium support plate 51.
Thereupon, shown in Fig. 5 c.Then, a chip 21 of having finished wafer integrated circuit manufacture process and excision forming is embedded in first opening 52 and second opening 53 imposes pressing again.Wherein, have a plurality of electronic padses 23 on the active surface 22 of chip 21, the material of this electronic pads is a copper.This dielectric layer 54 is in the process of pressing, and dielectric layer 54 can be fixed in first opening 52 and second opening 53 chip 21 by overflowing between this first aluminium support plate 50 and this second aluminium support plate 51, fixes this first aluminium support plate 50 and this second aluminium support plate 51 simultaneously.This dielectric layer 54 is folded between this first aluminium support plate 50, this second aluminium support plate 51 and this chip 21 at last, and its structure is shown in Fig. 5 d.In the present embodiment, the non-active surface 24 exposed chip coolings that help of chip 21.In the present embodiment, the thickness of the first aluminium support plate 50 (D1) equals the thickness (D2) of the second aluminium support plate 51.
After finishing above-mentioned steps, shown in Fig. 5 e, in the active surface 22 of the upper surface 55 of the first aluminium support plate 50, chip 21, form circuit layer reinforced structures 31 with electronic pads 23 surfaces, the conductive structure 38 that includes line layer 37 and be connected with the electronic pads 23 of chip 21, its formation method is identical with embodiment one.At last, form patterned anti-soldering layer 39 ' in this layer reinforced structure 31 surfaces again, and form a plurality of solder projections 39, promptly and finish the loading plate that is embedded with chip of present embodiment in the electric connection pad place that this patterned anti-soldering layer 39 ' manifests layer reinforced structure 31.
Because the first aluminium support plate 50 and the second aluminium support plate 51 all are formed with alumina layer 56 (aluminium oxide is a ceramic material) with mode of oxidizing, therefore, can increase the rigidity of the first aluminium support plate 50 and the second aluminium support plate 51.This event increases layer though the carrying plate structure that is embedded with chip of present embodiment is a single face, still can form the smooth carrying plate structure that is embedded with chip.
Embodiment four
The manufacture method and the embodiment one of the loading plate that is embedded with chip of present embodiment are closely similar, except the first aluminium support plate and the second aluminium upper surface of said carrier plate and lower surface all peroxidating respectively be formed with the alumina layer, all the other steps and embodiment two are roughly the same.
See also Fig. 6 a to 6d, be the generalized section of the carrying plate structure method for making that is embedded with chip of present embodiment.
Shown in Fig. 6 a, at first provide one first aluminium support plate 60 and one second aluminium support plate 61.This first aluminium support plate 60 and the second aluminium support plate 61 are placed an electrolysis tank, carry out oxidation reaction, make the upper surface and the equal oxidation of lower surface of the first aluminium support plate 60 and one second aluminium support plate 61 form alumina layer 66, and be gripped with an aluminium lamination 67 naturally in the middle of the two-layer aluminium oxide 66.In the present embodiment, the first aluminium support plate 60 and one second aluminium support plate 61 place an electrolysis tank, carry out anodic oxidation reactions, and by adjusting anodizing time, come the thickness of controlled oxidation aluminium lamination 66.
Then, provide a dielectric layer 62 between this first aluminium support plate 60 and this second aluminium support plate 61, and impose pressing.Thus, this dielectric layer 62 can be fixed this first aluminium support plate 60 and the second aluminium support plate 61, and forms a compound support plate 63.
Then, shown in Fig. 6 b, on this compound support plate 63, form one thereafter and run through opening 64.Then, a chip 21 of having finished wafer integrated circuit manufacture process and excision forming is embedded in the opening 64 of compound support plate 63.This chip 21 has a plurality of electronic padses 23 on the active surface 22 of chip 22, the material of this electronic pads is a copper.Then, will stick together material 25 and insert space between compound support plate 63 and the chip 21, and make chip 21 be fixed in the opening 64 of compound support plate 63 its structure such as Fig. 6 c.Wherein this sticks together material 25 and can be epoxy resin.And in the present embodiment, the non-active surface 24 exposed chip coolings that help of chip 21.In the present embodiment, the thickness of the first aluminium support plate 60 (D1) equals the thickness (D2) of the second aluminium support plate 61.
After finishing above-mentioned steps, shown in Fig. 6 d, form a circuit layer reinforced structure 31 in the upper surface 65 of the first aluminium support plate 60, the active surface 22 and electronic pads 23 surfaces of chip 21, the conductive structure 38 that includes line layer 37 and be connected with the electronic pads 23 of chip 21, its formation method is identical with embodiment one.At last, form patterned anti-soldering layer 39 ' in this layer reinforced structure 31 surfaces again, and form a plurality of solder projections 39, promptly and finish the loading plate that is embedded with chip of present embodiment in the electric connection pad place that this patterned anti-soldering layer 39 ' manifests layer reinforced structure 31.
Because the first aluminium support plate 60 and the second aluminium support plate 61 all are formed with alumina layer 66 (aluminium oxide is a ceramic material) with mode of oxidizing, therefore, can increase the rigidity of the first aluminium support plate 60 and the second aluminium support plate 61.This event increases layer though the carrying plate structure that is embedded with chip of present embodiment is a single face, still can form the smooth carrying plate structure that is embedded with chip.
The foregoing description is only given an example for convenience of description, and the interest field that the present invention advocated should be as the criterion so that claims are described certainly, but not only limits to the foregoing description.
Claims (14)
1. a carrying plate structure that is embedded with chip is characterized in that, comprising:
One first aluminium support plate has one first opening;
One second aluminium support plate has one second opening, and the position of this second opening is to position that should first opening;
One dielectric layer is folded between this first aluminium support plate and this second aluminium support plate;
One chip, this chip embedding bury is in this first opening and this second opening, and this chip has an active surface;
A plurality of electronic padses, those electronic padses are disposed at this active surface of this chip; And
One circuit layer reinforced structure, this circuit layer reinforced structure is disposed at this first aluminium upper surface of said carrier plate, the active surface of this chip and the surface of this electronic pads, wherein, this circuit layer reinforced structure has a plurality of conductive structures, and at least one this conductive structure is electrically connected at this electronic pads.
2. the carrying plate structure that is embedded with chip as claimed in claim 1, wherein, the material of this first aluminium support plate and this second aluminium support plate is an aluminum or aluminum alloy.
3. the carrying plate structure that is embedded with chip as claimed in claim 1, wherein, the thickness of this first aluminium support plate is less than the thickness of this second aluminium support plate.
4. the carrying plate structure that is embedded with chip as claimed in claim 1, wherein, this first aluminium upper surface of said carrier plate and lower surface respectively are formed with an alumina layer, and this second aluminium upper surface of said carrier plate and lower surface respectively are formed with an alumina layer.
5. the carrying plate structure that is embedded with chip as claimed in claim 1, wherein, between this first aluminium support plate and this chip and be filled with one between this second aluminium support plate and this chip and stick together material, to fix this chip in this first opening and second opening.
6. the carrying plate structure that is embedded with chip as claimed in claim 1, wherein, be filled with a dielectric layer between this first aluminium support plate and this chip and between this second aluminium support plate and this chip, be filled in the gap that chip and two aluminium support plates are generated, by pushing this dielectric material to fix this chip in this first opening and second opening.
7. the carrying plate structure that is embedded with chip as claimed in claim 1, wherein, this circuit layer reinforced structure includes at least one insulating barrier, and is stacked and placed on line layer and a plurality of conductive structure on this insulating barrier, and at least one this conductive structure is electrically connected to this electronic pads.
8. a manufacture method that is embedded with the loading plate of chip is characterized in that, comprises step:
A., one first aluminium support plate and one second aluminium support plate are provided;
B. form one first opening in this first aluminium support plate, and form one second opening in this second aluminium support plate, wherein the position of this second opening is to position that should first opening;
C. between this first aluminium support plate and this second aluminium support plate, a dielectric layer is set;
D. a chip is embedded in this first opening and this second opening, wherein, the active surface of this chip has a plurality of electronic padses, this first aluminium support plate of pressing subsequently combines two aluminium support plates with this second aluminium support plate, push simultaneously this dielectric layer make its be filled to this first aluminium support plate, this second aluminium support plate, and this chip between the gap, to fix this chip in this first opening and second opening; And
E. in the active surface of this first aluminium upper surface of said carrier plate, this chip, form a circuit layer reinforced structure with the surface of this electronic pads, wherein, this circuit layer reinforced structure have at least one insulating barrier, be stacked and placed on line layer on this insulating barrier, with a plurality of conductive structures, and at least one this conductive structure is electrically connected at this electronic pads.
9. the manufacture method that is embedded with the loading plate of chip as claimed in claim 8, wherein, in steps A, this first aluminium upper surface of said carrier plate and lower surface respectively are formed with an alumina layer, and this second aluminium upper surface of said carrier plate and lower surface respectively are formed with an alumina layer.
10. the manufacture method that is embedded with the loading plate of chip as claimed in claim 9, wherein, this alumina layer utilizes anode oxidation method to form.
11. a manufacture method that is embedded with the loading plate of chip is characterized in that, comprises step:
A., one first aluminium support plate and one second aluminium support plate are provided;
B. pressing one dielectric layer is between this first aluminium support plate and this second aluminium support plate, and forms a clad aluminum support plate;
C. form an opening in this clad aluminum support plate;
D. a chip is embedded and be fixed in this opening, wherein, the active surface of this chip has a plurality of electronic padses; And
E. form a circuit layer reinforced structure in the active surface of this first aluminium upper surface of said carrier plate, this chip and the surface of this electronic pads, wherein, this circuit layer reinforced structure has at least one insulating barrier, and is stacked and placed on line layer and a plurality of conductive structure on this insulating barrier, and at least one this conductive structure is electrically connected at this electronic pads.
12. the manufacture method that is embedded with the loading plate of chip as claimed in claim 11 wherein, after step D is embedded in a chip in the opening, also can be inserted one and stick together the gap of material between this chip and this opening, to fix this chip.
13. the manufacture method that is embedded with the loading plate of chip as claimed in claim 11, wherein, in steps A, this first aluminium support plate is that upper surface and lower surface respectively are formed with an alumina layer, and this second aluminium upper surface of said carrier plate and lower surface respectively are formed with an alumina layer.
14. the manufacture method that is embedded with the loading plate of chip as claimed in claim 13, wherein, this alumina layer utilizes anode oxidation method to form.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNA200710152840XA CN101393903A (en) | 2007-09-18 | 2007-09-18 | Bearing board construction embedded with chip and fabrication method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNA200710152840XA CN101393903A (en) | 2007-09-18 | 2007-09-18 | Bearing board construction embedded with chip and fabrication method thereof |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN101393903A true CN101393903A (en) | 2009-03-25 |
Family
ID=40494110
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNA200710152840XA Pending CN101393903A (en) | 2007-09-18 | 2007-09-18 | Bearing board construction embedded with chip and fabrication method thereof |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN101393903A (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102044500B (en) * | 2009-10-16 | 2013-08-07 | 相互股份有限公司 | Chip carrier plate as well as encapsulating structure and method thereof |
| CN103474401A (en) * | 2012-06-06 | 2013-12-25 | 欣兴电子股份有限公司 | Support plate structure and chip packaging structure and manufacturing method thereof |
| CN103794514A (en) * | 2012-10-29 | 2014-05-14 | 欣兴电子股份有限公司 | Method for manufacturing packaging substrate |
| CN105101636A (en) * | 2014-05-23 | 2015-11-25 | 三星电机株式会社 | Printed circuit board, method for manufacturing the same and package on package having the same |
-
2007
- 2007-09-18 CN CNA200710152840XA patent/CN101393903A/en active Pending
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102044500B (en) * | 2009-10-16 | 2013-08-07 | 相互股份有限公司 | Chip carrier plate as well as encapsulating structure and method thereof |
| CN103474401A (en) * | 2012-06-06 | 2013-12-25 | 欣兴电子股份有限公司 | Support plate structure and chip packaging structure and manufacturing method thereof |
| CN103474401B (en) * | 2012-06-06 | 2016-12-14 | 欣兴电子股份有限公司 | Carrying board structure and chip-packaging structure and preparation method thereof |
| CN103794514A (en) * | 2012-10-29 | 2014-05-14 | 欣兴电子股份有限公司 | Method for manufacturing packaging substrate |
| CN105101636A (en) * | 2014-05-23 | 2015-11-25 | 三星电机株式会社 | Printed circuit board, method for manufacturing the same and package on package having the same |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JP3591524B2 (en) | Semiconductor device mounting board, method of manufacturing the same, board inspection method thereof, and semiconductor package | |
| US6921977B2 (en) | Semiconductor package, method of production of same, and semiconductor device | |
| TWI308382B (en) | Package structure having a chip embedded therein and method fabricating the same | |
| US7474538B2 (en) | Semiconductor device mounting board, method of manufacturing the same, method of inspecting the same, and semiconductor package | |
| US8710669B2 (en) | Semiconductor device manufacture in which minimum wiring pitch of connecting portion wiring layer is less than minimum wiring pitch of any other wiring layer | |
| US7598610B2 (en) | Plate structure having chip embedded therein and the manufacturing method of the same | |
| WO2010010910A1 (en) | Coreless wiring substrate, semiconductor device, and methods for manufacturing same | |
| JP2002198462A (en) | Wiring board for mounting semiconductor device and its manufacturing method, and semiconductor package | |
| KR101470885B1 (en) | Multilayer electronic structure with integral metal core | |
| CN101364581A (en) | Loading board construction embedded with chip and preparation thereof | |
| US6787896B1 (en) | Semiconductor die package with increased thermal conduction | |
| CN101409238A (en) | Method for preparing seedless layer package substrate | |
| US20080029872A1 (en) | Plate structure having chip embedded therein and the manufacturing method of the same | |
| JP5029581B2 (en) | Manufacturing method of semiconductor package | |
| CN101393903A (en) | Bearing board construction embedded with chip and fabrication method thereof | |
| CN112420524B (en) | Support frame and manufacturing method thereof | |
| JP4345679B2 (en) | Manufacturing method of wiring board for mounting semiconductor device | |
| US20080217748A1 (en) | Low cost and low coefficient of thermal expansion packaging structures and processes | |
| CN101383329B (en) | Package construction embedded with chip and preparation thereof | |
| JP4819304B2 (en) | Semiconductor package | |
| JP4063240B2 (en) | Semiconductor device mounting substrate, manufacturing method thereof, and semiconductor package | |
| JP4340832B2 (en) | Wiring board and manufacturing method thereof | |
| US6634543B2 (en) | Method of forming metallic z-interconnects for laminate chip packages and boards | |
| CN101364582A (en) | Loading board construction embedded with chip and preparation thereof | |
| JP3757766B2 (en) | SEMICONDUCTOR DEVICE, ITS MANUFACTURING METHOD, AND ELECTRONIC DEVICE |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C02 | Deemed withdrawal of patent application after publication (patent law 2001) | ||
| WD01 | Invention patent application deemed withdrawn after publication |
Open date: 20090325 |