CN103426734A - Ion implantation method and device, field-effect tube manufacturing method and field-effect tube - Google Patents
Ion implantation method and device, field-effect tube manufacturing method and field-effect tube Download PDFInfo
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- CN103426734A CN103426734A CN201210149143XA CN201210149143A CN103426734A CN 103426734 A CN103426734 A CN 103426734A CN 201210149143X A CN201210149143X A CN 201210149143XA CN 201210149143 A CN201210149143 A CN 201210149143A CN 103426734 A CN103426734 A CN 103426734A
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Abstract
The invention discloses an ion implantation method which is used for implanting ions better and is simple in manufacturing process. The method comprises the steps that etching is conducted on an epitaxial layer on a substrate and a protective layer on the epitaxial layer, so that a groove is formed in the epitaxial layer; the etching width is a first width value; P type ions are implanted into the lateral wall of the groove with a first angle, the first angle is an included angle formed between a connection line and the lateral wall, wherein the connection line is formed between the depth point reached by the P type ions on the lateral wall of the groove and the top point of the protecting layer facing to the lateral wall, and the top point is away from the epitaxial layer; the P type ions are diffused to the outer side of the groove and diffused into the epitaxial layer to form a P type drifting area; a first medium layer is manufactured, the first medium layer covers the protecting layer and the groove, and the first medium layer and the protecting layer on the surface of the epitaxial layer are removed. The invention further discloses an ion implantation device, a field-effect tube manufacturing method and system and a field-effect tube.
Description
Technical field
The present invention relates to semiconductor manufacture and mechanical field, particularly ion injection method and equipment, field effect transistor manufacture method and field effect transistor.
Background technology
Super junction MOSFET (super knot metal-oxide layer-semiconductor-field-effect transistor), also can be called COOL MOSFET, and it all has larger advantage than conventional power MOSFET at aspects such as puncture voltage, conducting resistance.As shown in Figure 1A, the structure of COOL MOS as shown in Figure 1B for the structure of common power MOSFET.
But, for the device of COOL MOS structure, the longitudinal size of P type drift region (P-drift) wherein is generally darker, 50 μ m left and right are generally arranged, as shown in Figure 1B, and the lateral dimension of P type drift region may be less, makes and have larger difficulty.Wherein, the S in Figure 1B means source electrode, and D means drain electrode.Current existing manufacture method has two kinds:
First method: repeatedly grown epitaxial layer, repeatedly carry out Implantation and drive in, the final darker P type drift region of longitudinal size that forms in the N-type epitaxial loayer.This way is due to needs grown epitaxial layer and inject ion repeatedly, so manufacturing process is very loaded down with trivial details, and it is also very high repeatedly to generate the cost of epitaxial loayer.
Second method: first grow thick epitaxial loayer, then carry out repeatedly the Implantation of different-energy, then ion is driven in, finally in epitaxial loayer, form P type drift region.Although this way is simpler than first method, but make the ion injected be deep into tens microns of epitaxial loayers, Implantation Energy at least will reach tens million-electron-volts, and current most ion implantor does not reach this energy at all, so this method is very high to the requirement of equipment, also more difficult realization.
Summary of the invention
The embodiment of the present invention provides ion injection method and equipment, field effect transistor manufacture method and field effect transistor, and for injecting better ion, manufacturing process is simple.
A kind of ion injection method comprises the following steps:
Protective layer on epitaxial loayer on substrate and described epitaxial loayer is carried out to etching, thereby form a groove in described epitaxial loayer; The width of described etching is the first width value;
Sidewall injection P type ion with from the first angle to described groove, the point of the degree of depth that the above P type ion of the sidewall that wherein, described the first angle is described groove can reach with the described protective layer relative with described sidewall away from the line on the summit of described epitaxial loayer and the angle of described sidewall;
Make the P type ion injected be diffused into the described groove outside, described epitaxial loayer, form P type drift region;
Make the first medium layer, make described first medium layer cover described protective layer and described groove;
Remove described first medium layer and the described protective layer of described epi-layer surface.
A kind of field effect transistor manufacture method comprises the following steps:
Described ion injection method injects P type ion;
The first polycrystal layer that gate oxide in described epi-layer surface surface is made carries out etching, obtains the second polycrystal layer;
Inject P type ion in the described P type drift region in the described groove outside, make the P type ion diffusion of injecting, form the P tagma in described P type drift region;
Inject the N-type ion in described P tagma, the N-type ion injected is spread in described P tagma, form the N-type source region;
Make the second medium layer on surperficial and described the second polycrystal layer surface of described gate oxide, and described second medium layer and described gate oxide are carried out to etching;
Described epi-layer surface and described substrate surface after etching are all made metal level.
A kind of field effect transistor manufacturing system comprises:
Described ion implantation device, for injecting P type ion;
The 4th operating means, the first polycrystal layer of making for the surface of the gate oxide in described epi-layer surface carries out etching, obtains the second polycrystal layer;
The first injection device, inject P type ion for the described P type drift region in the described groove outside, makes the P type ion diffusion of injecting, and forms the P tagma in described P type drift region;
The second injection device, for inject the N-type ion in described P tagma, make the N-type ion injected spread in described P tagma, forms the N-type source region;
The second producing device, on surperficial and described the second polycrystal layer surface of described gate oxide, making the second medium layer, and carry out etching to described second medium layer and described gate oxide;
The 3rd producing device, all make metal level for the described epi-layer surface after etching and described substrate surface.
Embodiment of the present invention intermediate ion method for implanting is for to carry out etching to the protective layer on the epitaxial loayer on substrate and described epitaxial loayer, thereby forms a groove in described epitaxial loayer; The width of described etching is the first width value; Sidewall injection P type ion with from the first angle to described groove, the point of the degree of depth that the above P type ion of the sidewall that wherein, described the first angle is described groove can reach with the described protective layer relative with described sidewall away from the line on the summit of described epitaxial loayer and the angle of described sidewall; Make the P type ion injected be diffused into the described groove outside, described epitaxial loayer, form P type drift region; Make the first medium layer, make described first medium layer cover described protective layer and described groove; Remove described first medium layer and the described protective layer of described epi-layer surface.In epitaxial loayer, direct etching goes out a groove, then injects ion to the sidewall of this groove, can make ion reach the darker position of epitaxial loayer, and, without higher Implantation Energy, technique is simple, and less demanding to equipment.
The accompanying drawing explanation
Figure 1A is common MOSFET structural representation in prior art;
Figure 1B is COOL MOS structural representation in prior art;
Fig. 2 A is the main method flow chart that embodiment of the present invention intermediate ion injects;
The main method flow chart that Fig. 2 B is field effect pipe manufacturer in the embodiment of the present invention;
Fig. 3 A manufactures in the embodiment of the present invention in the field effect transistor process protective layer is carried out to the profile after etching;
Fig. 3 B manufactures in the embodiment of the present invention in the field effect transistor process protective layer and epitaxial loayer are all carried out to the profile after etching;
Fig. 3 C manufactures the profile after injection P type ion in the field effect transistor process in the embodiment of the present invention;
Fig. 3 D manufactures the profile after growth the first dielectric layer in the field effect transistor process in the embodiment of the present invention;
Fig. 3 E manufactures in the field effect transistor process profile of removing after first medium layer and protective layer in the embodiment of the present invention;
Fig. 3 F manufactures the profile after growth the first polycrystal layer in the field effect transistor process in the embodiment of the present invention;
Fig. 3 G manufactures in the embodiment of the present invention in the field effect transistor process the first polycrystal layer is carried out to the profile after etching;
Fig. 3 H manufactures the profile behind formation P tagma in the field effect transistor process in the embodiment of the present invention;
Fig. 3 I manufactures the profile behind formation N-type source region in the field effect transistor process in the embodiment of the present invention;
Fig. 3 J manufactures in the embodiment of the present invention in the field effect transistor process second medium layer and gate oxide are carried out to the profile after etching;
Fig. 3 K manufactures the profile after the growing metal layer in the field effect transistor process in the embodiment of the present invention;
The primary structure figure that Fig. 4 is embodiment of the present invention intermediate ion injection device;
The primary structure figure that Fig. 5 is field effect pipe manufacturer system in the embodiment of the present invention.
Embodiment
Embodiment of the present invention intermediate ion method for implanting is for to carry out etching to the protective layer on the epitaxial loayer on substrate and described epitaxial loayer, thereby forms a groove in described epitaxial loayer; The width of described etching is the first width value; Sidewall injection P type ion with from the first angle to described groove, the point of the degree of depth that the above P type ion of the sidewall that wherein, described the first angle is described groove can reach with the described protective layer relative with described sidewall away from the line on the summit of described epitaxial loayer and the angle of described sidewall; Make the P type ion injected be diffused into the described groove outside, described epitaxial loayer, form P type drift region; Make the first medium layer, make described first medium layer cover described protective layer and described groove; Remove described first medium layer and the described protective layer of described epi-layer surface.In epitaxial loayer, direct etching goes out a groove, then injects ion to the sidewall of this groove, can make ion reach the darker position of epitaxial loayer, and, without higher Implantation Energy, technique is simple, and less demanding to equipment.
Referring to Fig. 2 A, the main method flow process that embodiment of the present invention intermediate ion injects is as follows:
Step 2A01: the protective layer on the epitaxial loayer on substrate and described epitaxial loayer is carried out to etching, thereby form a groove in described epitaxial loayer; The width of described etching is the first width value.
At first at upper epitaxial loayer and the described protective layer made of substrate (SUB).The material of described substrate can be monocrystalline silicon.The N-type substrate of take in the embodiment of the present invention describes as example.The mode of making epitaxial loayer can be at described Grown epitaxial loayer, and the thickness of the epitaxial loayer of growth (i.e. height) can be not less than 50 μ m.For example, there is the special epitaxial furnace can be for grown epitaxial layer.The material of epitaxial loayer can be the monocrystalline silicon that quality is fabulous, and the quality of the monocrystalline silicon that it can be more used than substrate is good.Described epitaxial loayer covers on described substrate.
After described outer layer growth, the described protective layer of can growing on described epitaxial loayer, described protective layer can cover on described epitaxial loayer, and the material of described protective layer can be silicon dioxide, or described protective layer can be silicon nitride.It is fixed, also relevant with factors such as etching apparatus used, technological parameters that the thickness of described protective layer can come according to the gash depth of required etching.
After described protective layer growth, can carry out etching to described protective layer and described epitaxial loayer.The material of described protective layer of take is that silicon dioxide is example, and now described protective layer also can be called the first oxide layer.The width of etching can be the first width value, and described the first width value can mean with w.Described protective layer is carried out to profile after etching as shown in Figure 3A, described protective layer and described epitaxial loayer are all carried out to profile after etching as shown in Figure 3 B.Wherein, in the embodiment of the present invention; the part of described protective layer etching is fully corresponding with the part of described epitaxial loayer etching; and the groove etched in described epitaxial loayer be take U-shaped body and is described as example; its profile means to be U-shaped; take this U-shaped sidewall is reference, and the depth value that the ion of injection can reach can be described the first length value, and this first length value can mean with d1.Perhaps described groove can be also other shapes, and all shapes of inventive concept that meets are all within protection scope of the present invention.
Step 2A02: the sidewall injection P type ion with the first angle to described groove; the point of the degree of depth that the above P type ion of the sidewall that wherein, described the first angle is described groove can reach with the described protective layer relative with described sidewall away from the line on the summit of described epitaxial loayer and the angle of described sidewall.
When the sidewall to described groove injects P type ion, can at first to a side sidewall, inject, a side is injected to the opposite side sidewall after injecting again.As shown in Figure 3 C, the profile after all injecting for both sides.Wherein, the point of the degree of depth that the A point can reach for the above P type ion of sidewall of described groove; the B point is the described protective layer relative with the described sidewall summit away from described epitaxial loayer; line between these 2 and a side sidewall form described the first angle; the scope of described the first angle can be (0 °, 60 °].The height that d2 in Fig. 3 C is described protective layer.Described the first angle can mean with Φ.
After injecting P type ion, the P type ion of injection can be driven in to described epitaxial loayer, wherein, the mode driven in can be not make complete field effect transistor and be put in high temperature furnace pipe whole, the ion P type ion diffusion of injecting is come, and described P type drift region is the zone that described P type ion is diffused into.
By the described groove of etching in described epitaxial loayer, and adopt angle of inclination inject and drive in P type ion to described trenched side-wall, formed P type drift region.The curved portion that is positioned at two sidewall both sides of described groove in Fig. 3 C is described P type drift region.
Wherein, between A/F (being described the first width value) the w three of the depth d 1 of P type drift region, the angle of inclination of Implantation (being described the first angle) Φ and groove, can there is certain relation, as shown in Equation 1:
D1+d2=w/tan Φ formula 1
That is, the height value sum of the injection depth value of the described P type of described groove width ion in described epitaxial loayer and described protective layer and ratio equal the inverse of the tangent value of described the first angle.
Like this, by the width w of adjustment groove opening and the thickness d 1 of described protective layer, can obtain the depth d 2 of different P type drift regions.
Step 2A03: make the P type ion injected be diffused into the described groove outside, described epitaxial loayer, form P type drift region.
The P type ion of injection is driven in, make the P type ion injected be diffused into the described groove outside, described epitaxial loayer, to form P type drift region.
Step 2A04: make the first medium layer, make described first medium layer cover described protective layer and described groove.
The described first medium layer of growth on described protective layer, the material of described first medium layer can be insulating material, can be for example silicon dioxide.As shown in Figure 3 D, described first medium layer can cover on the described protective layer do not etched away, and described first medium layer can fill up described groove.
Step 2A05: described first medium layer and the described protective layer of removing described epi-layer surface.
Described first medium layer and the described protective layer of described epi-layer surface can be removed by methods such as chemical polishing or mechanical polishinges, as shown in Fig. 3 E.
Referring to Fig. 2 B, in the embodiment of the present invention, the main method flow process of field effect pipe manufacturer is as follows:
Step 2B01: according to described ion injection method, inject P type ion.
Inject P type ion according to the described ion injection method in Fig. 2 A.
Step 2B02: the first polycrystal layer that the surface of the gate oxide in described epi-layer surface is made carries out etching, obtains the second polycrystal layer.
At first make the first polycrystal layer in described epi-layer surface manufacturing gate oxide layers, and on described gate oxide surface, and described the first polycrystal layer is carried out to etching, described the first polycrystal layer after etching can be called the second polycrystal layer.
Wherein, before described epi-layer surface is made described gate oxide, can at first in described epi-layer surface, generate one deck sacrificial oxide layer.Because of when described epi-layer surface is made described gate oxide, require described epi-layer surface to guarantee to a certain degree clean and smooth, therefore can at first in described epi-layer surface, make one deck sacrificial oxide layer, and then described sacrificial oxide layer is etched away, like this can guarantee clean-up performance and the smooth degree of described epi-layer surface.The material of described sacrificial oxide layer can be silicon dioxide.
After etching away described sacrificial oxide layer, can generate one deck gate oxide in described epi-layer surface, described gate oxide can cover described epi-layer surface, the material of this gate oxide can be silicon dioxide, after described gate oxide generates, can also be at this gate oxide Surface Creation one deck the first polycrystal layer, described the first polycrystal layer can cover described gate oxide surface, and the material of this first polycrystal layer can be polysilicon.The profile of growing after the first polycrystal layer is as shown in Fig. 3 F.
After described the first polycrystal layer growth, can carry out photoetching and etching to described the first polycrystal layer, profile after etching is as shown in Fig. 3 G, now remaining described the first polycrystal layer can be called described the second polycrystal layer, and described the first polycrystal layer not part of etching (being described the second polycrystal layer) can be used as the grid of described field effect transistor.
Step 2B03: inject P type ion in the described P type drift region in the described groove outside, make the P type ion diffusion of injecting, form the P tagma in described P type drift region.
Can directly to the described groove outside, inject P type ion, the P type ion injected be driven in after injection again, make the P type ion diffusion of injecting, to form the P tagma, the P tagma of formation has taken the zone at place, part P type drift region, as shown in Fig. 3 H.
Step 2B04: inject the N-type ion in described P tagma, the N-type ion injected is spread in described P tagma, form the N-type source region.
Inject the N-type ion in described P tagma, to form the N-type source region, as shown in Fig. 3 I.Wherein, before injecting the N-type ion, can cover with photoresist the part of described gate oxide, so that the N-type ion is injected into described P tagma from the position outside described photoresist covering.
Step 2B05: make the second medium layer on surperficial and described the second polycrystal layer surface of described gate oxide, and described second medium layer and described gate oxide are carried out to etching.
By the N-type Implantation to behind described P tagma, can remove described photoresist, at described gate oxide surface and the described second medium layer of described polycrystal layer Surface Creation, the material of described second medium layer can be silicon dioxide afterwards.
After described second medium layer growth, can carry out etching to described second medium layer, wherein, when etching, can be that the second medium layer outside area of grid is etched away, and, when etching, can in the lump the described gate oxide below the second medium layer etched away also be etched away, as shown in Fig. 3 J.
Step 2B06: described epi-layer surface and described substrate surface after etching are all made metal level.
Described epi-layer surface after etching and the described substrate surface described metal level of all growing, as shown in Fig. 3 K, the material of described metal level can be Al-Si-Cu alloy.S in Fig. 3 K means the source electrode of described field effect transistor, and D means the drain electrode of described field effect transistor.
Referring to Fig. 4, the present invention also provides a kind of ion implantation device, and it can comprise the first operating means 401, the second operating means 402, the 3rd operating means 403, the first producing device 404 and removal device 405.
The first operating means 401 carries out etching for the protective layer on the epitaxial loayer on substrate and described epitaxial loayer, thereby forms a groove in described epitaxial loayer; The width of described etching is the first width value.
The second operating means 402 is for the sidewall injection P type ion to described groove with the first angle; the point of the degree of depth that the above P type ion of the sidewall that wherein, described the first angle is described groove can reach with the described protective layer relative with described sidewall away from the line on the summit of described epitaxial loayer and the angle of described sidewall.
The 3rd operating means 403 is diffused into the described groove outside, described epitaxial loayer for the P type ion that makes to inject, and forms P type drift region.The 3rd operating means 403 is driven in the P type ion of injection, makes the P type ion injected be diffused into the described groove outside, described epitaxial loayer, forms P type drift region.
The first producing device 404, for making the first medium layer, makes described first medium layer cover described protective layer and described groove.
Referring to Fig. 5, the present invention also provides a kind of field effect transistor manufacturing system, and it can comprise the first operating means 401, the second operating means 402, the 3rd operating means 403, the first producing device 404, removal device 405, the 4th operating means 406, the first injection device 407, the second injection device 408, the second producing device 409 and the 3rd producing device 410.Be to comprise described ion implantation device, the 4th operating means 406, the first injection device 407, the second injection device 408, the second producing device 409 and the 3rd producing device 410 in described field effect transistor manufacturing system.
The first polycrystal layer that the 4th operating means 406 is made for the surface of the gate oxide in described epi-layer surface carries out etching, obtains the second polycrystal layer.
The first injection device 407 injects P type ion for the described P type drift region in the described groove outside, makes the P type ion diffusion of injecting, and forms the P tagma in described P type drift region.
The second injection device 408, for inject the N-type ion in described P tagma, makes the N-type ion injected spread in described P tagma, forms the N-type source region.
The second producing device 409 on described gate oxide surface and described the second polycrystal layer surface make the second medium layer, and described second medium layer and described gate oxide are carried out to etching.
The 3rd producing device 410 is all made metal level for the described epi-layer surface after etching and described substrate surface.
The present invention also provides a kind of field effect transistor, and it can adopt the manufacture of described field effect transistor manufacture method to form by described field effect transistor manufacturing system.
Embodiment of the present invention intermediate ion method for implanting is for to carry out etching to the protective layer on the epitaxial loayer on substrate and described epitaxial loayer, thereby forms a groove in described epitaxial loayer; The width of described etching is the first width value; Sidewall injection P type ion with from the first angle to described groove, the point of the degree of depth that the above P type ion of the sidewall that wherein, described the first angle is described groove can reach with the described protective layer relative with described sidewall away from the line on the summit of described epitaxial loayer and the angle of described sidewall; Make the P type ion injected be diffused into the described groove outside, described epitaxial loayer, form P type drift region; Make the first medium layer, make described first medium layer cover described protective layer and described groove; Remove described first medium layer and the described protective layer of described epi-layer surface.In epitaxial loayer, direct etching goes out a groove, then injects ion to the sidewall of this groove, can make ion reach the darker position of epitaxial loayer, and, without higher Implantation Energy, technique is simple, and less demanding to equipment.
The present invention also provides a kind of field effect transistor manufacture method, has adopted described ion injection method while wherein injecting ion, and the technique that makes to manufacture field effect transistor is more simple, and the field effect transistor produced more meets the requirements.
Obviously, those skilled in the art can carry out various changes and modification and not break away from the spirit and scope of the present invention the present invention.Like this, if within of the present invention these are revised and modification belongs to the scope of the claims in the present invention and equivalent technologies thereof, the present invention also is intended to comprise these changes and modification interior.
Claims (13)
1. an ion injection method, is characterized in that, comprises the following steps:
Protective layer on epitaxial loayer on substrate and described epitaxial loayer is carried out to etching, thereby form a groove in described epitaxial loayer; The width of described etching is the first width value;
Sidewall injection P type ion with from the first angle to described groove, the point of the degree of depth that the above P type ion of the sidewall that wherein, described the first angle is described groove can reach with the described protective layer relative with described sidewall away from the line on the summit of described epitaxial loayer and the angle of described sidewall;
Make the P type ion injected be diffused into the described groove outside, described epitaxial loayer, form P type drift region;
Make the first medium layer, make described first medium layer cover described protective layer and described groove;
Remove described first medium layer and the described protective layer of described epi-layer surface.
2. the method for claim 1, is characterized in that, the scope of described the first angle be (0 °, 60 °].
3. the method for claim 1, is characterized in that, the height value sum of the injection depth value of described P type ion in described epitaxial loayer and described protective layer and the ratio of described groove width equal the inverse of the tangent value of described the first angle.
4. the method for claim 1; it is characterized in that; removing the described first medium layer of described epi-layer surface and the step of described protective layer comprises: remove described first medium layer and the described protective layer of described epi-layer surface by the mode of chemical polishing, or remove described first medium layer and the described protective layer of described epi-layer surface by the mode of mechanical polishing.
5. a field effect transistor manufacture method, is characterized in that, comprises the following steps:
Ion injection method as described as claim 1-4 any one injects P type ion;
The first polycrystal layer that gate oxide in described epi-layer surface surface is made carries out etching, obtains the second polycrystal layer;
Inject P type ion in the described P type drift region in the described groove outside, make the P type ion diffusion of injecting, form the P tagma in described P type drift region;
Inject the N-type ion in described P tagma, the N-type ion injected is spread in described P tagma, form the N-type source region;
Make the second medium layer on surperficial and described the second polycrystal layer surface of described gate oxide, and described second medium layer and described gate oxide are carried out to etching;
Described epi-layer surface and described substrate surface after etching are all made metal level.
6. method as claimed in claim 5, is characterized in that, described first medium layer and described second medium layer are silicon dioxide.
7. a field effect transistor, is characterized in that, adopts method as described as claim 5 or 6 to make.
8. an ion implantation device, is characterized in that, comprising:
The first operating means, carry out etching for the protective layer on the epitaxial loayer on substrate and described epitaxial loayer, thereby form a groove in described epitaxial loayer; The width of described etching is the first width value;
The second operating means, for the sidewall injection P type ion to described groove with the first angle, the point of the degree of depth that the above P type ion of the sidewall that wherein, described the first angle is described groove can reach with the described protective layer relative with described sidewall away from the line on the summit of described epitaxial loayer and the angle of described sidewall;
The 3rd operating means, be diffused into the described groove outside, described epitaxial loayer for the P type ion that makes to inject, and forms P type drift region;
The first producing device, for making the first medium layer, make described first medium layer cover described protective layer and described groove;
Removal device, for removing described first medium layer and the described protective layer of described epi-layer surface.
9. equipment as claimed in claim 8, is characterized in that, the scope of described the first angle be (0 °, 60 °].
10. equipment as claimed in claim 8, is characterized in that, the height value sum of the injection depth value of described P type ion in described epitaxial loayer and described protective layer and the ratio of described groove width equal the inverse of the tangent value of described the first angle.
11. equipment as claimed in claim 8; it is characterized in that; described removal device is removed described first medium layer and the described protective layer of described epi-layer surface specifically for the mode by chemical polishing, or removes described first medium layer and the described protective layer of described epi-layer surface by the mode of mechanical polishing.
12. a field effect transistor manufacturing system, is characterized in that, comprising:
As the described ion implantation device of claim 8-11 any one, for injecting P type ion;
The 4th operating means, the first polycrystal layer of making for the surface of the gate oxide in described epi-layer surface carries out etching, obtains the second polycrystal layer;
The first injection device, inject P type ion for the described P type drift region in the described groove outside, makes the P type ion diffusion of injecting, and forms the P tagma in described P type drift region;
The second injection device, for inject the N-type ion in described P tagma, make the N-type ion injected spread in described P tagma, forms the N-type source region;
The second producing device, on surperficial and described the second polycrystal layer surface of described gate oxide, making the second medium layer, and carry out etching to described second medium layer and described gate oxide;
The 3rd producing device, all make metal level for the described epi-layer surface after etching and described substrate surface.
13. system as claimed in claim 12, is characterized in that, described first medium layer and described second medium layer are silicon dioxide.
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| CN111244182A (en) * | 2020-01-19 | 2020-06-05 | 深圳市昭矽微电子科技有限公司 | Metal oxide semiconductor field effect transistor and manufacturing method thereof |
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| CN1823423A (en) * | 2003-12-26 | 2006-08-23 | 罗姆股份有限公司 | Semiconductor device and its manufacturing method |
| US6982193B2 (en) * | 2004-05-10 | 2006-01-03 | Semiconductor Components Industries, L.L.C. | Method of forming a super-junction semiconductor device |
| CN1992342A (en) * | 2005-12-29 | 2007-07-04 | 东部电子股份有限公司 | Semiconductor device and method of manufacturing the same |
| CN101510557A (en) * | 2008-01-11 | 2009-08-19 | 艾斯莫斯技术有限公司 | Superjunction device having a dielectric termination and methods for manufacturing the device |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN111244182A (en) * | 2020-01-19 | 2020-06-05 | 深圳市昭矽微电子科技有限公司 | Metal oxide semiconductor field effect transistor and manufacturing method thereof |
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