CN103413772B - A kind of method that wafer is thinning - Google Patents
A kind of method that wafer is thinning Download PDFInfo
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- CN103413772B CN103413772B CN201310256826.XA CN201310256826A CN103413772B CN 103413772 B CN103413772 B CN 103413772B CN 201310256826 A CN201310256826 A CN 201310256826A CN 103413772 B CN103413772 B CN 103413772B
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Abstract
The method that a kind of wafer of the present invention is thinning, including: multilamellar wafer is carried out bonding technology；The edge slot of wafer after bonding applies implant；Implant is carried out cured；The superiors' wafer and/or the orlop wafer of para-linkage carry out reduction process；Implant is removed.The method of the present invention, when carrying out thinning to wafer, crystal round fringes will not produce forced breakage, it is to avoid the chip produced during fracture forms cut and residual at crystal column surface；Owing to need not deburring technique, simplify technical process, reduce cost, improve wafer area utilization rate.
Description
Technical field
The present invention relates to technical field of manufacturing semiconductors, be specifically related to a kind of method that wafer is thinning.
Background technology
In the art of semiconductor manufacturing, due to thinning wafer can beneficially encapsulate, effective transmission ray etc., so, wafer reduction process becomes one important operation in field of semiconductor manufacture such as integrated circuit fields.
Referring to Fig. 1-4, Fig. 1 is the schematic flow sheet of the thinning method of common wafer, the Fig. 2-4 cross section structure schematic diagram corresponding to each preparation process of the thinning method of common wafer, and the thinning method of common wafer includes:
Step S11: refer to Fig. 2, carries out bonding technology to wafer 101 and 102；
Step S12: refer to Fig. 3, the wafer 101 of para-linkage carries out deburring technique；
Step S13: refer to Fig. 4, the wafer 101 of para-linkage carries out reduction process.
In the method that above-mentioned wafer is thinning, wafer 101 includes substrate 1 and multilayer film 2, multilayer film 2 usually plurality of layers metal or the sull at the back side of wafer 101, such as include epitaxial layer, gate oxide, polysilicon film etc., existence due to multilayer film 2, and the radian that the marginal existence of wafer 101 and 102 is certain, when bonding, as shown in Figure 2, two wafer 101 and 102 can not fit together closely, the marginal existence gap of the wafer 101 and 102 of bonding, if directly carrying out reduction process, the edge of wafer 101 is owing to can not get attachment and supporting, the most easily forced breakage, and wafer 101 and 102 is all caused damage.
In order to avoid in reduction process, the wafer of bonding ruptures, industry generally uses deburring technique, before reduction process is carried out, first the crystal round fringes of bonding is ground off, i.e. carry out deburring technique, but, deburring technique needs to carry out the cutting of large-size to inside wafer, the actually used area that so can cause wafer reduces, thus reduces the utilization rate of wafer area, and improves process costs.
Summary of the invention
In order to overcome the problems referred to above, the purpose of the present invention is intended to improve wafer reduction process, reduces cost, and improves wafer area utilization rate.
The method that a kind of wafer of the present invention is thinning, including:
Step S01: multilamellar wafer is carried out bonding technology；
Step S02: apply implant in the edge slot of the wafer after described bonding；
Step S03: described implant is carried out cured；
Step S04: the superiors' wafer and/or orlop wafer to described bonding carry out reduction process；
Step S05: described implant is removed.
Preferably, the number of plies of described multilamellar wafer is two-layer.
Preferably, the outer surface of described implant exceeds or is flush to the described the superiors or the edge of orlop wafer.
Preferably, described implant is in close contact with the edge of described wafer.
Preferably, injection device is used to apply described implant.
Preferably, in step S03, before carrying out described cured, first described crystal column surface is carried out, removes the residual charge on its surface.
Preferably, described cured is that described implant carries out heat treated, forms the described implant with some strength.
Preferably, after described reduction process, use cleaning, and/or described implant is removed by Technology for Heating Processing.
Preferably, described implant is to have the colloid of cohesive.
Preferably, described implant is dissolved in particular liquid.
The method that the wafer of the present invention is thinning; by applying implant in the edge slot of the wafer of bonding; utilize the good fillibility of implant, stickiness and the certain intensity after cured; crystal round fringes can be played protection, the effect supported; so; when carrying out thinning to wafer, crystal round fringes will not produce forced breakage, it is to avoid the chip produced during fracture forms cut and residual at crystal column surface；Owing to need not deburring technique, simplify technical process, reduce cost, improve wafer area utilization rate.
Accompanying drawing explanation
Fig. 1 is the schematic flow sheet of the thinning method of common wafer
The Fig. 2-4 cross section structure schematic diagram corresponding to each preparation process of the thinning method of common wafer
Fig. 5 is the schematic flow sheet of the thinning method of the wafer of a preferred embodiment of the present invention
Fig. 6-11 is the cross section structure schematic diagram that each preparation process of the wafer thining method of the above-mentioned preferred embodiment of the present invention is formed
Detailed description of the invention
Embodiment feature of present invention will describe with the embodiment of advantage in the explanation of back segment in detail.Iting should be understood that the present invention can have various changes in different examples, it neither departs from the scope of the present invention, and explanation therein and being shown in substantially as purposes of discussion, and is not used to limit the present invention.
Below in conjunction with accompanying drawing 5-11, by specific embodiment, the method that the wafer of the present invention is thinning is described in further detail.Wherein, Fig. 5 is the schematic flow sheet of the thinning method of the wafer of a preferred embodiment of the present invention, and Fig. 6-11 is the cross section structure schematic diagram that each preparation process of the wafer thining method of the above-mentioned preferred embodiment of the present invention is formed.
It should be noted that, accompanying drawing all uses the form simplified very much, uses non-ratio accurately, and only in order to reach to aid in illustrating the purpose of the embodiment of the present invention conveniently, lucidly.
In the wafer thining method of the present invention, the wafer used can be, but not limited to as silicon chip, the back of wafer can include multiple layer metal or the oxide-film thin film such as epitaxial layer, gate oxide, polysilicon film, and the edge of wafer has certain radian, so can cause two wafer are bonded when, edge at wafer can not well fit, as previously mentioned, although using conventional method can avoid crystal round fringes forced breakage, but reduce the usable floor area of wafer, thus add cost.
Refer to Fig. 5, the method that the wafer of the present embodiment of the present invention is thinning, including:
Step S01: multilamellar wafer is carried out bonding technology；
Here, in the present embodiment, multilamellar wafer is two-layer, and including upper wafer 201 and lower wafer 202, upper wafer 201 includes substrate 21 and multilayer film 22；Refer to Fig. 6, wafer 201 and 202 is carried out bonding technology；As previously mentioned, wafer 201 and wafer 202 are bonded, wafer 201 includes wafer substrate 21 and multilayer film 22, multilayer film 22 can include multiple layer metal or the oxide-film thin film such as epitaxial layer, gate oxide, polysilicon film, owing to wafer 201 and wafer 202 are being carried out in bonding technology, the reasons such as the marginal existence certain radian of multilayer film 22, wafer 201 and 202 are contained at wafer 201 back side, wafer 201 and wafer 202 can not well fit together, in wafer 201 and the marginal existence gap of wafer 202 of bonding.
In another embodiment in the present invention, wafer is multilamellar wafer, and multilamellar wafer carries out upper and lower stacking bonding.
Step S02: apply implant in the crystal round fringes gap of bonding；
In the present embodiment, refer to Fig. 7, the edge slot of the wafer 201 and 202 after two panels is bonded applies implant 203；
Concrete, injection device can be used to apply implant 203, such as, there is the syringe of pipeline, implant 203 can be expelled in gap by pipeline；Selected implant 203 is the colloid with cohesive, and such as implant is viscose；Implant 203 can also be dissolved in particular liquid, is so conducive to implant 203 to be full of whole gap, improves the filling capacity of implant 203；Owing to implant 203 has certain filling capacity and stickiness; and there is after follow-up cured certain intensity; the edge of wafer 201 and wafer 202 can play protection and supporting role, and carrying out thinning when, the edge of wafer 201 will not rupture easily due to stress.
Additionally, in another embodiment in the present invention, in the wafer of multilamellar bonding, all apply implant in the crystal round fringes gap of every layer of bonding.
Step S03: implant is carried out cured；
Here, in the present embodiment, before implant 203 is carried out cured, wafer 201 and wafer 202 surface of first para-linkage are carried out, and remove the residual charge on its surface；Referring to Fig. 8, cleaning process can use chemical liquids to be carried out；Why it is carried out, it is due to during applying implant 203, inevitably the remained on surface at wafer 201 or 202 has implant, in order to avoid these remain the impact on follow-up reduction process of the implant of crystal column surfaces, so being first carried out the surface of wafer 201 or 202.
Refer to Fig. 9, the cured mode used, can use and implant 203 is carried out mode of heating, big owing to being in the insufficient strength of the implant 203 of viscous state, advantageously can not be played a supporting role in the edge of wafer 201 and wafer 202, therefore, also need it is carried out cured, strengthen the intensity of implant；Further, in the curing process, implant preferably can bond with the edge of wafer 201 and wafer 202, thus improves the filling capacity of implant 203, adhesive power.
From this, implant 203 needs to have good filling capacity, adhesive power, and there is after cured certain intensity.It is that the edge to wafer 201 and wafer 202 plays protection and supporting role owing to applying the purpose of implant 203; so; in the present embodiment; the outer surface of implant 203 exceeds or is flush to wafer 201 and the edge of wafer 202 of bonding; implant 203 is in close contact with the edge of wafer 201 and wafer 202; this way it is possible to avoid make the effect of implant 203 be substantially reduced owing to filling insufficient.
In another embodiment of the invention, first the surface of wafer of multilamellar bonding is carried out technique, uses the most again but be not limited to the mode of heating and implant is carried out cured.
Step S04: the superiors' wafer and/or the orlop wafer of para-linkage carry out reduction process.
In the present embodiment, referring to Figure 10, the wafer 201 of para-linkage carries out reduction process.
After above-mentioned steps, the edge of wafer 201 and wafer 202 is served and well supports and adhesive effect by the implant applied, time the wafer 201 of para-linkage carries out reduction process, the forced breakage at the edge of wafer 201 can be avoided, reduce fragment in wafer 201 and the residual on wafer 202 surface.
In another embodiment of the present invention, the superiors of the wafer of multilamellar bonding or orlop wafer can be carried out reduction process, such as, first the superiors' wafer of the wafer of multilamellar bonding can be carried out reduction process, then, wafer multilamellar being bonded is inverted, and the orlop wafer of the wafer of multilamellar bonding is carried out reduction process；Only the superiors' wafer or orlop wafer to the wafer of multilamellar bonding can also carry out reduction process.
Step S05: remove implant.
In the present embodiment, refer to Figure 11, after the thinning process, use cleaning or Technology for Heating Processing or cleaning and Technology for Heating Processing to be combined together, the implant in the edge slot of wafer 201 and 202 is removed.
To sum up; the method that the wafer of the present invention is thinning; by applying implant in the edge slot of the wafer of bonding; utilize the good fillibility of implant, stickiness and the certain intensity after cured; crystal round fringes can be played protection, the effect supported, so, when carrying out thinning to wafer; crystal round fringes will not produce forced breakage, it is to avoid the chip produced during fracture forms cut and residual at crystal column surface；Owing to need not deburring technique, simplify technical process, reduce cost, improve wafer area utilization rate.
The above-described embodiments of the invention that are only, described embodiment is also not used to limit the scope of patent protection of the present invention, and the equivalent structure change that the description of the most every utilization present invention and accompanying drawing content are made in like manner should be included in protection scope of the present invention.
Claims (9)
1. the method that a wafer is thinning, it is characterised in that including:
Step S01: multilamellar wafer is carried out bonding technology；
Step S02: apply implant in the edge slot of the wafer after described bonding；Described implant
It is dissolved in the liquid that described implant dissolves in, so that described implant is full of whole gap；
Step S03: be first carried out described crystal column surface, removes the residual charge on its surface；So
After, described implant is carried out cured；
Step S04: the superiors' wafer and/or orlop wafer to described bonding carry out reduction process；
Step S05: described implant is removed.
The method that wafer the most according to claim 1 is thinning, it is characterised in that described many layer crystals
The number of plies of circle is two-layer.
The method that wafer the most according to claim 1 is thinning, it is characterised in that described implant
Outer surface exceeds or is flush to the described the superiors or the edge of orlop wafer.
The method that wafer the most according to claim 1 is thinning, it is characterised in that described implant with
The edge of described wafer is in close contact.
The method that wafer the most according to claim 1 is thinning, it is characterised in that use injection device
Apply described implant.
The method that wafer the most according to claim 1 is thinning, it is characterised in that at described solidification
Reason is that described implant is carried out heat treated.
The method that wafer the most according to claim 1 is thinning, it is characterised in that described reduction process
Afterwards, use cleaning, and/or described implant is removed by Technology for Heating Processing.
The method that wafer the most according to claim 1 is thinning, it is characterised in that described implant
For having the colloid of cohesive.
The method that wafer the most according to claim 1 is thinning, it is characterised in that described implant
After described cured, there is intensity.
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| CN103413772B true CN103413772B (en) | 2016-08-10 |
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Families Citing this family (15)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104716056B (en) * | 2013-12-17 | 2018-04-13 | 中芯国际集成电路制造(上海)有限公司 | A kind of wafer bonding method |
| CN104118844B (en) * | 2014-07-15 | 2017-01-25 | 电子科技大学 | Method for thinning silicon-base back surface |
| CN104409581A (en) * | 2014-11-19 | 2015-03-11 | 迪源光电股份有限公司 | Improved wafer thinning processing method |
| CN105845548A (en) * | 2015-01-16 | 2016-08-10 | 中芯国际集成电路制造(上海)有限公司 | Silicon substrate and a manufacturing method thereof |
| CN105984837A (en) * | 2015-02-17 | 2016-10-05 | 中芯国际集成电路制造(上海)有限公司 | Wafer of stack structure and thinning method thereof |
| CN106348245B (en) * | 2015-07-23 | 2018-02-06 | 中芯国际集成电路制造(上海)有限公司 | A kind of MEMS and preparation method thereof, electronic installation |
| CN106571376A (en) * | 2015-10-13 | 2017-04-19 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor device and manufacturing method thereof, and electronic device |
| CN108022836B (en) * | 2016-10-31 | 2021-04-06 | 中芯国际集成电路制造(上海)有限公司 | Grinding method of multilayer stacked wafer |
| CN109461647A (en) * | 2018-11-16 | 2019-03-12 | 德淮半导体有限公司 | The manufacturing method of semiconductor device |
| CN110394910A (en) * | 2019-07-23 | 2019-11-01 | 芯盟科技有限公司 | Wafer thining method |
| CN110854039A (en) * | 2019-09-30 | 2020-02-28 | 芯盟科技有限公司 | Stack bonding wafer processing apparatus |
| CN110854011A (en) * | 2019-09-30 | 2020-02-28 | 芯盟科技有限公司 | Method for processing stacked bonded wafers |
| CN111298854B (en) * | 2020-02-27 | 2021-08-06 | 西人马联合测控（泉州）科技有限公司 | Chip forming method and wafer |
| CN111430276B (en) * | 2020-04-24 | 2021-04-23 | 武汉新芯集成电路制造有限公司 | Multi-wafer stacking trimming method |
| CN112959211B (en) * | 2021-02-22 | 2021-12-31 | 长江存储科技有限责任公司 | Wafer processing apparatus and processing method |
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| CN101327572A (en) * | 2007-06-22 | 2008-12-24 | 中芯国际集成电路制造(上海)有限公司 | Technique for thinning back side of silicon wafer |
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| JP2006295030A (en) * | 2005-04-14 | 2006-10-26 | Nitto Denko Corp | Method of manufacturing semiconductor device and adhesive sheet to be used therefor |
| US8753460B2 (en) * | 2011-01-28 | 2014-06-17 | International Business Machines Corporation | Reduction of edge chipping during wafer handling |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN101327572A (en) * | 2007-06-22 | 2008-12-24 | 中芯国际集成电路制造(上海)有限公司 | Technique for thinning back side of silicon wafer |
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