CN104409581A - Improved wafer thinning processing method - Google Patents
Improved wafer thinning processing method Download PDFInfo
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- CN104409581A CN104409581A CN201410659890.7A CN201410659890A CN104409581A CN 104409581 A CN104409581 A CN 104409581A CN 201410659890 A CN201410659890 A CN 201410659890A CN 104409581 A CN104409581 A CN 104409581A
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- wafer
- thickness
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- polishing
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/005—Processes
- H01L33/0095—Post-treatment of devices, e.g. annealing, recrystallisation or short-circuit elimination
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/304—Mechanical treatment, e.g. grinding, polishing, cutting
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
- H01L22/10—Measuring as part of the manufacturing process
- H01L22/12—Measuring as part of the manufacturing process for structural parameters, e.g. thickness, line width, refractive index, temperature, warp, bond strength, defects, optical inspection, electrical measurement of structural dimensions, metallurgic measurement of diffusions
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/005—Processes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2933/00—Details relating to devices covered by the group H01L33/00 but not provided for in its subgroups
- H01L2933/0008—Processes
Abstract
The invention applies to the field of production of LED chips, and improves an improved wafer thinning processing method. The improved wafer thinning processing method comprises the steps of acquiring a wafer on which a gallium nitride layer is prepared by epitaxial growth; acquiring a chamfer angle of the side edge of the wafer and the wafer thickness of each point on the wafer surface; calculating the distance from the thickness of a plurality of wafers on the side edge to the thickness of a circular wafer to determine one or a plurality of points of which the distance exceeds the threshold; and grinding the side edge of the wafer according to the distance from one or the plurality of points to the side edge of the wafer and the chamfer angle, so as to finish the subsequent thinning process of the grinded wafer. The improved wafer thinning processing method has the advantages that the thickness of the side edge of the wafer subjected to the processing of the gallium nitride layer is detected to recognize the area without meeting the thickness requirement, the side edge of the wafer exceeding the thickness threshold is grinded in light of the chamfer angle of the side edge of the wafer, and thus the excessively small thickness of the final wafer caused by the wafer side edge with wax extruding thickness exceeding the threshold can be avoided in the subsequent grinding process.
Description
Technical field
The invention belongs to LED chip production field, particularly relate to a kind of thinning processing method of wafer of improvement.
Background technology
Because the reasons such as technology cause crystal round fringes to occur remaining in the process of epitaxial growth gallium nitride layer, do in the process of chip electrode higher (in as the Fig. 1 shown in crystal round fringes) that can cause the thickness of crystal round fringes follow-up, when waxing paster to wafer due to the warped that crystal round fringes is partially thick and wafer itself exists, wax 16 outwards exclusion can be deposited on crystal round fringes (wafer 14 shown in polishing state as started in Fig. 2), wafer is thinning complete after wax cleaned up can find that crystal round fringes thickness is on the low side with amesdial measurement.Splitting in the course of processing at follow-up stroke to cause wafer to occur disorderly splitting phenomenon, and method the most frequently used is at present absorbed by the core grain disorderly split.
The method of prior art not only wastes and is used in processing raw material and manufacturing procedure on the random core grain split, and described warped phenomenon also can affect the thinning effect of wafer entirety, makes overall thinning result uneven.
In prior art, normally directly brought by the wafer after the process of epitaxial growth of gallium nitride layer and make thinning process, the present invention utilizes follow-up step 204-208 to realize the improvement of the thinning processing of wafer.If in wafer fabrication processes, also have other operations to produce and produce similar edge thickness problem as during the process of epitaxial growth of gallium nitride layer, be also applicable to the solution of the present invention.
In step 204, the wafer thickness of each point on the chamfer angle at edge of wafer and wafer face is obtained.
In preferred implementation, the pre-test that chamfer angle is carrying out described epitaxial growth of gallium nitride layer at the edge of described wafer obtains.
Wherein, measurement means comprises: gamma thickness gage, eddy current thickness meter, magnetic thickness tester, sonigauge or mechanical calibrator.Because the present invention uses the wafer thickness of each point on the wafer face detected, therefore, by this area other detecting instrument or detection means obtain one-tenth-value thickness 1/10 also belong within protection scope of the present invention.
In step 206, by the spacing of the multiple wafer thickness in edge calculation and central wafer thickness, determine that described distance exceedes one or more points of threshold value.
Described threshold value decides according to the thickness of wafer and the size of wafer.Through the result that inventor's many experiments obtains, for 280*200 micron LED chip, described threshold value adopts 10 microns of optimums.
In a step 208, according to the edge of described one or more point to the described wafer of polishing through chamfer angle described in long Distance geometry of crystal round fringes, so that the wafer completing described polishing carries out follow-up thinning process.
In optional scheme; described " according to the edge of described one or more point to the described wafer of polishing through chamfer angle described in long Distance geometry of crystal round fringes " also can be described as at " according to the edge of described one or more point to the described wafer of polishing through chamfer angle described in long Distance geometry in the wafer center of circle "; only the difference on describing mode, and to be expressed be the common meaning also belong to protection category of the present invention.
The embodiment of the present invention, by detecting the edge thickness of the wafer through gallium nitride layer process, identifying and not meeting the region of thickness, and in conjunction with the chamfering of crystal round fringes, the crystal round fringes this being exceeded thickness threshold value polishes off.Thus ensure that in follow-up grinding step, can not extrude because of wax the crystal round fringes that thickness exceedes threshold value and cause the warped of wafer, make finally to grind out wafer thickness and meet even requirement.
Summary of the invention
The object of the embodiment of the present invention is to provide a kind of wafer of improvement thinning processing method, to improve the thinning effect that prior art warped phenomenon also can affect wafer entirety, makes the problem that overall thinning result is uneven.
The embodiment of the present invention is achieved in that the thinning processing method of a kind of wafer of improvement, said method comprising the steps of:
Obtain the wafer through the process of epitaxial growth of gallium nitride layer; Obtain the wafer thickness of each point on the chamfer angle at edge of wafer and wafer face; By the spacing of the multiple wafer thickness in edge calculation and central wafer thickness, determine that described distance exceedes one or more points of threshold value; According to the edge of described one or more point to the described wafer of polishing through chamfer angle described in long Distance geometry of crystal round fringes, so that the wafer completing described polishing carries out follow-up thinning process.
The embodiment of the present invention, by detecting the edge thickness of the wafer through gallium nitride layer process, identifying and not meeting the region of thickness, and in conjunction with the chamfering of crystal round fringes, the crystal round fringes this being exceeded thickness threshold value polishes off.Thus ensure that in follow-up grinding step, can not extrude because of wax the crystal round fringes that thickness exceedes threshold value and cause the warped of wafer, make finally to grind out wafer thickness and meet even requirement.
Accompanying drawing explanation
In order to be illustrated more clearly in the technical scheme in the embodiment of the present invention, be briefly described to the accompanying drawing used required in embodiment or description of the prior art below, apparently, accompanying drawing in the following describes is only some embodiments of the present invention, for those of ordinary skill in the art, under the prerequisite not paying creative work, other accompanying drawing can also be obtained according to these accompanying drawings.
Fig. 1 is the design sketch higher in kind of the thickness of the crystal round fringes that the present invention provides in the introduction;
Fig. 2 is the wafer warped design sketch caused because crystal round fringes thickness is higher in the prior art that provides of the embodiment of the present invention;
Fig. 3 is the thinning processing method flow chart of wafer of a kind of improvement that the embodiment of the present invention provides;
Fig. 4 is the thinning processing method flow chart of wafer of a kind of improvement that the embodiment of the present invention provides;
Fig. 5 is the thinning processing method flow chart of wafer of a kind of improvement that the embodiment of the present invention provides;
Fig. 6 is the schematic diagram of a kind of wafer polishing region setting that the embodiment of the present invention provides.
Embodiment
In order to make object of the present invention, technical scheme and advantage clearly understand, below in conjunction with drawings and Examples, the present invention is further elaborated.Should be appreciated that specific embodiment described herein only in order to explain the present invention, be not intended to limit the present invention.
In order to technical solutions according to the invention are described, be described below by specific embodiment.
Embodiment one
Be illustrated in figure 3 the flow chart of the thinning processing method of wafer of a kind of improvement provided by the invention, said method comprising the steps of:
In step 202., the wafer through the process of epitaxial growth of gallium nitride layer is obtained.
Embodiment two
Be illustrated in figure 4 the flow chart of the thinning processing method of wafer of a kind of improvement that the embodiment of the present invention provides, the present embodiment two is further for the improvement project through growing refinement and/or the optimization done how determining to polish on the basis based on embodiment one, in a step 208, specifically realized by step 209.
In step 209, calculating described one or more point to crystal round fringes through growing the maximum in distance, using described chamfering and the described maximum calculated as the distance of polishing, completing the edge polishing of described wafer.
The present embodiment, by the restriction of maximum, to ensure that on crystal round fringes that thickness exceedes threshold portion to greatest extent and is polished in bruting process, thus ensure that the quality of follow-up thinning process.
Embodiment three
Be illustrated in figure 5 the flow chart of the thinning processing method of wafer of a kind of improvement that the embodiment of the present invention provides, the present embodiment three be on the basis based on embodiment one and embodiment two further for the improvement project through the long refinement done and optimization how determining to polish, be embodied in.
Specifically step 302-310 can be comprised in step 208 or step 209.
In step 302, described one or more point is calculated to crystal round fringes through growing the maximum in distance.
In step 304, using the value obtained after former wafer radius deducts described maximum as new radius, calculate the circle that described new radius forms and whether overlap with the drift angle of multiple LED chip unit.
Within step 306, if result of calculation is not for all to overlap, then step 308 is entered; If result of calculation for there is coincidence situation, then enters step 310.
In step 308, described new radius is reduced further, until overlap with the drift angle of multiple LED chip unit, now described new radius value is the radius of target of wafer after polishing, and the circle made from described polishing radius to be polished the edge of described wafer for indicating range.
In order to how clearer explanation step 308 realizes, present invention also offers the schematic diagram of a kind of wafer polishing of Fig. 6 region setting.In figure, the multiple LED chip unit 12 r1 ~ r68 labels comprised in wafer are marked.The first polishing index line 16 described in figure (compares the second polishing index line 18, closer to the border of wafer described in first polishing index line 16), be the value obtained after deducting described maximum based on former wafer radius draw as new radius circle (namely describe in step 208 and in possibility arrive crystal round fringes through long distance).But, by finding shown in figure, described first polishing index line 16 be all part run through LED chip unit 12, there is not the situation that to coincide with the drift angle of certain LED chip unit 12.Due to, LED chip unit be symmetrical, be distributed among wafer uniformly, therefore, if described first polishing index line 16 and described multiple LED chip unit 12 exist the coincidence of corner point, also will be symmetrical appearance.In figure, the second polishing index line 18 is the radius of target calculating wafer after polishing through step 308, can find that the second polishing index line 18 is close to the first polishing index line 16 by Fig. 6, ensure that under the prerequisite that complete LED chip unit is not destroyed in bruting process, the brilliant radius of a circle after polishing is controlled at minimum zone.
In the step 310, the circle made from described new radius to be polished the edge of described wafer for indicating range.
In embodiments of the present invention, ensure that under the prerequisite that complete LED chip unit is not destroyed in bruting process, brilliant radius of a circle after polishing is controlled at minimum zone, thus optimize the use of auxiliary material in follow-up thinning work, and improve the treatment effeciency (because decreasing the process on impaired LED chip unit) to wafer.
In conjunction with the present embodiment three, preferably perform the present invention perform in the main frame of step at server or for storing, store the distance set of each LED chip unit drift angle in the wafer center of circle to wafer, then for the new radius value calculated in step 209 or 308, only need to mate in the distance set of the wafer center of circle of described storage each LED chip unit drift angle in wafer, and navigate between certain two value.Radius of target then in step 308 and described two value in smaller value.
Preferably, when calculating and store the distance set of each LED chip unit drift angle in the wafer center of circle to wafer, due to the symmetry that LED chip unit distributes on wafer, generally only need to calculate the distance of the LED chip unit summit in wafer in first quartile to the wafer center of circle.
Those of ordinary skill in the art it is also understood that, the all or part of step realized in above-described embodiment method is that the hardware that can carry out instruction relevant by program has come, described program can be stored in a computer read/write memory medium, described storage medium, comprises ROM/RAM, disk, CD etc.
The foregoing is only preferred embodiment of the present invention, not in order to limit the present invention, all any amendments done within the spirit and principles in the present invention, equivalent replacement and improvement etc., all should be included within protection scope of the present invention.
Claims (7)
1. the thinning processing method of wafer improved, it is characterized in that, described method comprises:
Obtain the wafer through the process of epitaxial growth of gallium nitride layer;
Obtain the wafer thickness of each point on the chamfer angle at edge of wafer and wafer face;
By the spacing of the multiple wafer thickness in edge calculation and central wafer thickness, determine that described distance exceedes one or more points of threshold value;
According to the edge of described one or more point to the described wafer of polishing through chamfer angle described in long Distance geometry of crystal round fringes, so that the wafer completing described polishing carries out follow-up thinning process.
2. the method for claim 1, is characterized in that, described threshold value decides according to the thickness of wafer and the size of wafer.
3. the method for claim 1, is characterized in that, when described wafer is used for the LED chip generating 280*200 micron, described threshold value is 10 μm.
4. the method as described in as arbitrary in claim 1-3, is characterized in that, described according to the edge of described one or more point to the described wafer of polishing through chamfer angle described in long Distance geometry of crystal round fringes, specifically comprises:
Calculate described one or more point to crystal round fringes through growing the maximum in distance;
Using described chamfering and the described maximum calculated as the distance of polishing, complete the edge polishing of described wafer.
5. the method as described in as arbitrary in claim 1-3, is characterized in that, described according to the edge of described one or more point to the described wafer of polishing through chamfer angle described in long Distance geometry of crystal round fringes, specifically comprises:
Calculate described one or more point to crystal round fringes through growing the maximum in distance;
Using the value obtained after former wafer radius deducts described maximum as new radius, calculate the circle that described new radius forms and whether overlap with the drift angle of multiple LED chip unit;
If result of calculation is not for all to overlap, then described new radius is reduced further, until overlap with the drift angle of multiple LED chip unit, now described new radius value is the radius of target of wafer after polishing, and the circle made from described polishing radius to be polished the edge of described wafer for indicating range.
6. as described in as arbitrary in claim 1-5 method, it is characterized in that, the wafer thickness of each point on the chamfer angle at the edge of described acquisition wafer and wafer face, comprising:
The pre-test that chamfer angle is carrying out described epitaxial growth of gallium nitride layer at the edge of described wafer obtains.
7. the method as described in as arbitrary in claim 1-6, is characterized in that, the wafer thickness of each point on the chamfer angle at the edge of described measurement wafer and wafer face, and its measurement means comprises:
Gamma thickness gage, eddy current thickness meter, magnetic thickness tester, sonigauge or mechanical calibrator.
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| Application Number | Priority Date | Filing Date | Title |
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| CN201410659890.7A CN104409581A (en) | 2014-11-19 | 2014-11-19 | Improved wafer thinning processing method |
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| CN201410659890.7A CN104409581A (en) | 2014-11-19 | 2014-11-19 | Improved wafer thinning processing method |
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| CN104409581A true CN104409581A (en) | 2015-03-11 |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106248008A (en) * | 2016-08-31 | 2016-12-21 | 惠晶显示科技（苏州）有限公司 | A kind of thinning after liquid crystal panel method for measuring thickness |
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| US20100255682A1 (en) * | 2009-04-01 | 2010-10-07 | Tokyo Electron Limited | Method for thinning a bonding wafer |
| CN102832223A (en) * | 2012-09-06 | 2012-12-19 | 豪威科技(上海)有限公司 | Wafer thinning method |
| CN103056742A (en) * | 2012-11-07 | 2013-04-24 | 上海合晶硅材料有限公司 | Monocrystalline silicon slice chamfer processing method |
| CN103413772A (en) * | 2013-06-25 | 2013-11-27 | 上海华力微电子有限公司 | Wafer thinning method |
| CN104078345A (en) * | 2014-06-13 | 2014-10-01 | 北京工业大学 | Thinning method for ultra-thin wafers |
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2014
- 2014-11-19 CN CN201410659890.7A patent/CN104409581A/en active Pending
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20100059862A1 (en) * | 2008-09-08 | 2010-03-11 | Seddon Michael J | Thinned semiconductor wafer and method of thinning a semiconductor wafer |
| US20100255682A1 (en) * | 2009-04-01 | 2010-10-07 | Tokyo Electron Limited | Method for thinning a bonding wafer |
| CN102832223A (en) * | 2012-09-06 | 2012-12-19 | 豪威科技(上海)有限公司 | Wafer thinning method |
| CN103056742A (en) * | 2012-11-07 | 2013-04-24 | 上海合晶硅材料有限公司 | Monocrystalline silicon slice chamfer processing method |
| CN103413772A (en) * | 2013-06-25 | 2013-11-27 | 上海华力微电子有限公司 | Wafer thinning method |
| CN104078345A (en) * | 2014-06-13 | 2014-10-01 | 北京工业大学 | Thinning method for ultra-thin wafers |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN106248008A (en) * | 2016-08-31 | 2016-12-21 | 惠晶显示科技（苏州）有限公司 | A kind of thinning after liquid crystal panel method for measuring thickness |
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