CN103368568B - Improve method and the phase-locked loop frequency synthesizer thereof of phase-lock-ring output frequency precision - Google Patents
Improve method and the phase-locked loop frequency synthesizer thereof of phase-lock-ring output frequency precision Download PDFInfo
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Abstract
A kind of method and phase-locked loop frequency synthesizer thereof improving phase-lock-ring output frequency precision, wherein, method is included in central processing unit runs following program, and carrying corresponding direct-current control voltage by the voltage-controlled pin of VC_TCXO to phase-locked loop circuit, CPU is according to target frequency configuration pll parameter; CPU reads the magnitude of voltage Vref of more accurate frequency; Calculate frequency division value; If the fractional part of frequency division value is less than between 0.5 between being more than or equal to 0, then calculate the first direct-current control voltage by formula (1); Voffset1=2* Δ VFsetp/2*a+Vref(1); If the fractional part of frequency division value is less than between 1 between being more than or equal to 0.5, then calculate the second direct-current control voltage by formula (2); Voffset2=Vref-2* Δ VFsetp/2*b; First direct-current control voltage or the second direct-current control voltage are delivered to the voltage-controlled pin of VC_TCXO by DAC by CPU; Target frequency is converged to by phase-locked loop.Realization of the present invention does not need to increase any hardware cost, only need do respective handling on software, so implementation is simple, cost is lower, very easily promotes the use of.<!-- 2 -->
Description
Technical field
The present invention relates to a kind of method and the phase-locked loop frequency synthesizer thereof that improve phase-lock-ring output frequency precision.
Background technology
Along with the development of the systems such as public network communication, private network communication, WLAN (wireless local area network), cordless telephone, mobile phone, Digital Television, satellite fix, frequency synthesizer not only market is huge, and in machine system, acts on great, is directly connected to system safety.Frequency synthesizer provides the frequency source of needs for system in the communications, and the performance index of frequency source are directly connected to the performance of whole system, therefore more and more higher to the requirement of the frequency stability of frequency source, spectral purity, frequency range and output frequency number.
Along with the development of large scale integrated circuit, phase-lock frequency synthetic technology occupies more and more consequence, and, Phase Lock Technique is in fields such as communication, space flight, measurement, TV, atomic energy, Electric Machine Control, can the high-performance ground extraction of settling signal, the tracking of signal is with synchronous, the function such as modulation and demodulation, frequency synthesis, filtering of analog-and digital-communication, has become one of basic element of character commonly used in electronic equipment.Phase-locked loop is one of parts most crucial in phase-lock frequency synthetic technology, it is a phase error control system, phase difference between its comparator input signal and oscillator output signal, thus produce the frequency that error controling signal adjusts oscillator, to reach and the object of input signal with frequency homophase.
Phase-lock frequency synthesizer is divided into phase-locking type integer frequency synthesizer and phase-locking type fractional synthesizer, wherein, the output signal frequency of phase-locking type fractional synthesizer needs not be the integral multiple of reference signal frequency, and can be the little several times of reference signal frequency.The minimum frequency space of fractional synthesizer output signal, i.e. output frequency precision, is determined by the resolution figure place of reference signal frequency and fractional synthesizer.Visible, fractional synthesizer, while the reference signal supporting upper frequency, can obtain higher output frequency precision.
But, the minimum half also only having minimum frequency stepping of precision of the output frequency precision of existing fractional phase locked loop frequency synthesizer, that is, when the decimal place of fractional phase locked loop frequency synthesizer be more than or equal to 0 be less than 0.5 time, phase-locked loop is phase-locked to low side, when the decimal place of fractional phase locked loop frequency synthesizer be more than or equal to 0.5 be less than 1 time, phase-locked loop is to high-end phase-locked.Also do not have which phase-locked loop to can be implemented in any frequency in existing phase-locked loop and carry out phase-locked object.
Summary of the invention
In order to overcome the problems referred to above, the present invention provides a kind of to society can carry out phase-locked phase-locked loop frequency synthesizer at any frequency.
Second object of the present invention provides a kind of method improving phase-lock-ring output frequency precision to society.
Technical scheme of the present invention is: provide a kind of phase-locked loop frequency synthesizer, comprise central processing unit, digital to analog converter, voltage controlled temperature compensated crystal oscillator, phase-locked loop circuit, low pass filter and voltage controlled oscillator, modulation signal is flowed to phase-locked loop circuit by the voltage-controlled pin of voltage controlled temperature compensated crystal oscillator by central processing unit domination number weighted-voltage D/A converter, phase-locked loop circuit exports the target frequency with modulation signal by low pass filter and voltage controlled oscillator again, when phase-locked, central processing unit works as follows, and carry corresponding direct-current control voltage by the voltage-controlled pin of VC---_TCXO to phase-locked loop circuit,
S100, program start;
S200, CPU are according to target frequency configuration pll parameter;
The magnitude of voltage Vref of the more accurate frequency prestored is called in temporary storage by S300, CPU;
S400, draw frequency division value with the output frequency of phase-locked loop divided by the minimum frequency stepping-in amount of this phase-locked loop;
S500, the selection of frequency division value fractional part and the calculating of direct-current control voltage;
If the fractional part of S510 frequency division value is less than between 0.5 between being more than or equal to 0, then calculate the first direct-current control voltage by formula (1);
Voffset1=2*△VFsetp/2*a+Vref（1）
In formula, Voffset1 is the first direct-current control voltage; △ VFsetp/2 is the direct voltage corrected value of 1/2 minimum frequency stepping-in amount; A be frequency division value be less than fractional part between 0.5 between being more than or equal to 0; Vref is the DC voltage value of more accurate frequency;
If the fractional part of S520 frequency division value is less than between 1 between being more than or equal to 0.5, then calculate the second direct-current control voltage by formula (2);
Voffset2=Vref-2*△VFsetp/2*b
In formula, Voffset2 is the second direct-current control voltage; △ VFsetp/2 is the direct voltage corrected value of 1/2 minimum frequency stepping-in amount; B be frequency division value be less than fractional part between 1 between being more than or equal to 0.5; Vref is the DC voltage value of more accurate frequency;
First direct-current control voltage or the second direct-current control voltage are delivered to the voltage-controlled pin of VC---_TCXO by DAC by S600, CPU;
S700, converge to target frequency by phase-locked loop;
S800, end.
As the improvement to phase-locked loop frequency synthesizer, described Voffset1 and Voffset2 draws in the steps below:
(1), in operating frequency range, frequency is divided into N section by minimum frequency stepping-in amount (Fsetp), in N section, gets wherein one section of N1, from N1, gather M frequency;
(2), with M the frequency gathered, M be more than or equal to 2 positive integer, choose wherein minimum Frequency point (f0) as calibration frequency reference point (Fref), record the voltage-controlled pin voltage (Vref) of VC_TCXO corresponding to this Frequency point, calibrate output frequency by the voltage of the voltage-controlled pin of VC_TCXO adjusting other M-1 frequency again, thus find the relation between the voltage-controlled voltage of this M-1 frequency and Vref;
(3), formula is utilized
=A.B(3) calculate the value of Voffset1 and Voffset2;
In formula (3), Fvco is the output frequency of PLL; Fsetp is minimum frequency stepping-in amount; Wherein A is the integer part in the frequency division value that draws of formula (3), and B is the fractional part in the frequency division value that draws of formula (3); The fractional part B of formula (3) has two kinds of situations,
The first: the value of fractional part B is more than or equal to 0 and is less than <0.5; The value of the second: fractional part B is more than or equal to 0.5 and is less than 1;
When the value of fractional part B be more than or equal to 0 be less than <0.5 time,
Δ Fvco=(A.B-A) * Fsetp, make A.B-A=a then Δ Fvco=a*Fsetp therefore, the first direct-current control voltage Voffset1 is drawn by formula (4):
Voffset1=
* Δ Fvco+Vref(4) simplify after,
Voffset1=
When the value of fractional part B be more than or equal to 0.5 be less than 1 time,
Δ Fvco '=(A.B-A-1) * Fsetp, make A.B-A-1=b then Δ Fvco=b*Fsetp therefore, the second direct-current control voltage Voffset2 is drawn by formula (5):
Voffset2=
* Δ Fvco '+Vref(5) simplify after,
Voffset2=
=Vref-2*△VFsetp/2*b。
The present invention also provides a kind of method improving phase-lock-ring output frequency precision, runs following program in central processing unit, and it is phase-locked to carry corresponding direct-current control voltage to carry out by the voltage-controlled pin of VC---_TCXO to phase-locked loop circuit,
S100, program start;
S200, CPU are according to target frequency configuration pll parameter;
The magnitude of voltage Vref of the more accurate frequency prestored is called in temporary storage by S300, CPU;
S400, draw frequency division value with the output frequency of phase-locked loop divided by the minimum frequency stepping-in amount of this phase-locked loop;
S500, the selection of frequency division value fractional part and the calculating of direct-current control voltage;
If the fractional part of S510 frequency division value is less than between 0.5 between being more than or equal to 0, then calculate the first direct-current control voltage by formula (1);
Voffset1=2*△VFsetp/2*a+Vref（1）
In formula, Voffset1 is the first direct-current control voltage; △ VFsetp/2 is the direct voltage corrected value of 1/2 minimum frequency stepping-in amount; A be frequency division value be less than fractional part between 0.5 between being more than or equal to 0; Vref is the DC voltage value of more accurate frequency;
If the fractional part of S520 frequency division value is less than between 1 between being more than or equal to 0.5, then calculate the second direct-current control voltage by formula (2);
Voffset2=Vref-2*△VFsetp/2*b
In formula, Voffset2 is the second direct-current control voltage; △ VFsetp/2 is the direct voltage corrected value of 1/2 minimum frequency stepping-in amount; B be frequency division value be less than fractional part between 1 between being more than or equal to 0.5; Vref is the DC voltage value of more accurate frequency;
First direct-current control voltage or the second direct-current control voltage are delivered to the voltage-controlled pin of VC---_TCXO by DAC by S600, CPU;
S700, converge to target frequency by phase-locked loop;
S800, end.
As the improvement of the method to raising phase-lock-ring output frequency precision, described Voffset1 and Voffset2 draws in the steps below:
(1), in operating frequency range, frequency is divided into N section by minimum frequency stepping-in amount (Fsetp), in N section, gets wherein one section of N1, from N1, gather M frequency;
(2), with M the frequency gathered, M be more than or equal to 2 positive integer, choose wherein minimum Frequency point (f0) as calibration frequency reference point (Fref), record the voltage-controlled pin voltage (Vref) of VC_TCXO corresponding to this Frequency point, calibrate output frequency by the voltage of the voltage-controlled pin of VC_TCXO adjusting other M-1 frequency again, thus find the relation between the voltage-controlled voltage of this M-1 frequency and Vref;
(3), formula is utilized
=A.B(3) calculate the value of Voffset1 and Voffset2;
In formula (3), Fvco is the output frequency of PLL; Fsetp is minimum frequency stepping-in amount; Wherein A is the integer part in the frequency division value that draws of formula (3), and B is the fractional part in the frequency division value that draws of formula (3); The fractional part B of formula (3) has two kinds of situations,
The first: the value of fractional part B is more than or equal to 0 and is less than <0.5; The value of the second: fractional part B is more than or equal to 0.5 and is less than 1;
When the value of fractional part B be more than or equal to 0 be less than <0.5 time,
Δ Fvco=(A.B-A) * Fsetp, make A.B-A=a then Δ Fvco=a*Fsetp therefore, the first direct-current control voltage Voffset1 is drawn by formula (4):
Voffset1=
* Δ Fvco+Vref(4) simplify after,
Voffset1=
When the value of fractional part B be more than or equal to 0.5 be less than 1 time,
Δ Fvco '=(A.B-A-1) * Fsetp, make A.B-A-1=b then Δ Fvco=b*Fsetp therefore, the second direct-current control voltage Voffset2 is drawn by formula (5):
Voffset2=
* Δ Fvco '+Vref(5) simplify after,
Voffset2=
=Vref-2*△VFsetp/2*b。
The present invention passes through the computing formula of establishment first direct-current control voltage or the second direct-current control voltage, utilizes software algorithm to make locking frequency finally converge to target frequency; Reference frequency Fref only need calibrate by the used time, again by the computing formula of software according to the first direct-current control voltage or the second direct-current control voltage, automatically the direct-current control voltage of each frequency is calculated, the voltage-controlled voltage exporting corresponding frequency finally by central processor CPU control DAC makes phase lock loop locks on target frequency, can improve phase-lock-ring output frequency precision widely.Realization of the present invention does not need to increase any hardware cost, only need do respective handling on software, so implementation is simple, cost is lower, very easily promotes the use of.
Accompanying drawing explanation
Fig. 1 is the schematic flow sheet of an embodiment of the present invention.
Fig. 2 is phase-locked loop frequency synthesizer frame structure schematic diagram of the present invention.
Fig. 3 is direct-current control voltage computation schema schematic diagram of the present invention.
Fig. 4 is the frame structure schematic diagram of a kind of application example of phase-locked loop frequency synthesizer of the present invention.
Fig. 5 is the physical circuit principle schematic of Fig. 4.
Embodiment
Refer to Fig. 1, what Fig. 1 disclosed is a kind of method improving phase-lock-ring output frequency precision, runs following program in central processing unit, and it is phase-locked to carry corresponding direct-current control voltage to carry out by the voltage-controlled pin of VC---_TCXO to phase-locked loop circuit,
S100, program start;
S200, CPU are according to target frequency configuration pll parameter;
The magnitude of voltage Vref of the more accurate frequency prestored is called in temporary storage by S300, CPU;
S400, draw frequency division value with the output frequency of phase-locked loop divided by the minimum frequency stepping-in amount of this phase-locked loop;
S500, the selection of frequency division value fractional part and the calculating of direct-current control voltage;
If the fractional part of S510 frequency division value is less than between 0.5 between being more than or equal to 0, then calculate the first direct-current control voltage by formula (1);
Voffset1=2*△VFsetp/2*a+Vref（1）
In formula, Voffset1 is the first direct-current control voltage; △ VFsetp/2 is the direct voltage corrected value of 1/2 minimum frequency stepping-in amount; A be frequency division value be less than fractional part between 0.5 between being more than or equal to 0; Vref is the DC voltage value of more accurate frequency;
If the fractional part of S520 frequency division value is less than between 1 between being more than or equal to 0.5, then calculate the second direct-current control voltage by formula (2);
Voffset2=Vref-2*△VFsetp/2*b
In formula, Voffset2 is the second direct-current control voltage; △ VFsetp/2 is the direct voltage corrected value of 1/2 minimum frequency stepping-in amount; B be frequency division value be less than fractional part between 1 between being more than or equal to 0.5; Vref is the DC voltage value of more accurate frequency;
First direct-current control voltage or the second direct-current control voltage are delivered to the voltage-controlled pin of VC---_TCXO by DAC by S600, CPU;
S700, converge to target frequency by phase-locked loop;
S800, end.
Refer to Fig. 2, what Fig. 2 disclosed is a kind of phase-locked loop frequency synthesizer, comprise central processor CPU, digital to analog converter DAC, voltage controlled temperature compensated crystal oscillator VCTCXO, phase-locked loop circuit PLLIC, low pass filter LPF and voltage controlled oscillator VCO, modulation signal is flowed to phase-locked loop circuit PLLIC by the voltage-controlled pin of voltage controlled temperature compensated crystal oscillator VCTCXO by central processor CPU domination number weighted-voltage D/A converter DAC, phase-locked loop circuit PLLIC exports the target frequency RFOUT with modulation signal by low pass filter LPF and voltage controlled oscillator VCO again, when phase-locked, central processor CPU runs following program, and carry corresponding direct-current control voltage by the voltage-controlled pin of voltage controlled temperature compensated crystal oscillator VC---_TCXO to phase-locked loop circuit PLLIC, namely the first direct-current control voltage Voffset1 or the second direct-current control voltage Voffset2 is carried,
S100, program start;
S200, CPU are according to target frequency configuration pll parameter;
The magnitude of voltage Vref of the more accurate frequency prestored is called in temporary storage by S300, CPU;
S400, draw frequency division value with the output frequency of phase-locked loop divided by the minimum frequency stepping-in amount of this phase-locked loop;
S500, the selection of frequency division value fractional part and the calculating of direct-current control voltage;
If the fractional part of S510 frequency division value is less than between 0.5 between being more than or equal to 0, then calculate the first direct-current control voltage by formula (1);
Voffset1=2*△VFsetp/2*a+Vref（1）
In formula, Voffset1 is the first direct-current control voltage; △ VFsetp/2 is the direct voltage corrected value of 1/2 minimum frequency stepping-in amount; A be frequency division value be less than fractional part between 0.5 between being more than or equal to 0; Vref is the DC voltage value of more accurate frequency;
If the fractional part of S520 frequency division value is less than between 1 between being more than or equal to 0.5, then calculate the second direct-current control voltage by formula (2);
Voffset2=Vref-2*△VFsetp/2*b
In formula, Voffset2 is the second direct-current control voltage; △ VFsetp/2 is the direct voltage corrected value of 1/2 minimum frequency stepping-in amount; B be frequency division value be less than fractional part between 1 between being more than or equal to 0.5; Vref is the DC voltage value of more accurate frequency;
First direct-current control voltage or the second direct-current control voltage are delivered to the voltage-controlled pin of VC---_TCXO by DAC by S600, CPU;
S700, converge to target frequency by phase-locked loop;
S800, end.
Refer to Fig. 3, Fig. 3 is the step calculating Voffset1 and Voffset2 in said method and phase-locked loop frequency synthesizer:
(1), in operating frequency range, frequency is divided into N section by minimum frequency stepping-in amount (Fsetp), in N section, gets wherein one section of N1, from N1, gather M frequency;
(2), with M the frequency gathered, M be more than or equal to 2 positive integer, choose wherein minimum Frequency point (f0) as calibration frequency reference point (Fref), record the voltage-controlled pin voltage (Vref) of VC_TCXO corresponding to this Frequency point, calibrate output frequency by the voltage of the voltage-controlled pin of VC_TCXO adjusting other M-1 frequency again, thus find the relation between the voltage-controlled voltage of this M-1 frequency and Vref;
(3), formula is utilized
=A.B(3) calculate the value of Voffset1 and Voffset2;
In formula (3), Fvco is the output frequency of PLL; Fsetp is minimum frequency stepping-in amount; Wherein A is the integer part in the frequency division value that draws of formula (3), and B is the fractional part in the frequency division value that draws of formula (3); The fractional part B of formula (3) has two kinds of situations,
The first: the value of fractional part B is more than or equal to 0 and is less than <0.5; The value of the second: fractional part B is more than or equal to 0.5 and is less than 1;
When the value of fractional part B be more than or equal to 0 be less than <0.5 time,
Δ Fvco=(A.B-A) * Fsetp, make A.B-A=a then Δ Fvco=a*Fsetp therefore, the first direct-current control voltage Voffset1 is drawn by formula (4):
Voffset1=
* Δ Fvco+Vref(4) simplify after,
Voffset1=
When the value of fractional part B be more than or equal to 0.5 be less than 1 time,
Δ Fvco '=(A.B-A-1) * Fsetp, make A.B-A-1=b then Δ Fvco=b*Fsetp therefore, the second direct-current control voltage Voffset2 is drawn by formula (5):
Voffset2=
* Δ Fvco '+Vref(5) simplify after,
Voffset2=
=Vref-2*△VFsetp/2*b。
The test data not adopting software algorithm to calibrate and the test data result after adopting software algorithm are as following table:
As can be seen from the above data, the output frequency worst error not adding software algorithm is 2340Hz, and uses the output frequency worst error after the inventive method to be 15Hz, very little with target frequency error.
For DMR full duplex digital handset system (330MHZ-400MHZ), the invention will be further described below, and what in this system, Phase Lock Loop IC adopted is that SKY72300, SKY72300 have following features:
Adopt loop design, the mode of operation of control main ring independently and secondary ring during use, can be carried out by software control; Main ring has integral frequency divisioil, 18 fractional frequency divisions, 10 fractional frequency division Three models, secondary ring has integral frequency divisioil and 10 fractional frequency divisions.Its circuit block diagram is shown in Fig. 4, and physical circuit schematic diagram is shown in Fig. 5.
In the present embodiment, consider the requirement of DMR full duplex digital handset system and the index of phase-locked loop, the main ring (transmitting path) of phase-locked loop adopts the mode of operation of 18 fractional frequency divisions, the mode of operation of what phase-locked loop secondary ring (receiving path) adopted is 10 fractional frequency divisions, that in Fig. 5, reference clock Fosc adopts is the VC_TCXO of 19.2MHZ, in order to the fractional stray of solid phase-locked loop of holding concurrently, the index such as locking time and phase noise reference clock frequency divider Rosc_div adopts 4 frequency divisions, so phase demodulation frequency Fpd=Fosc/4=19.2MHZ/4=4.8MHZ, be respectively by the minimum frequency stepping of the known launching and receiving path of phase demodulation frequency 4.8MHZ: Fsetp=Fpd/218=4.8MHZ/218=18.31HZ (radiating portion), Fsetp=Fpd/210=4.8MHZ/210=4687.5HZ (receiving unit), therefore, the frequency accuracy of receiving unit cannot meet system requirements (according to ETSIEN301166-1V1.3.2 standard, during requirement hand-held terminal device 300MHZ-500MHZ, frequency error is ± 0.1CSP, and system CSP is arrowband 12.5KHz herein, so the frequency error required is for being less than 1.25KHz).
(1) calculating of direct-current control voltage;
Direct-current control voltage (DAC exports compensation rate) formula: because transmitting path (main ring) frequency error is that 18.31HZ meets system requirements, so do not state herein; Calculate the direct-current control voltage of secondary ring below;
Choose a more accurate output frequency of frequency Fref, adjustment magnitude of voltage now saves as Vref;
Take frequency range as 330MHz ~ 400MHz, phase demodulation frequency Fpd=4.8MHz be example,
Receiving unit (secondary ring) minimum frequency step value is Fsetp=Fpd/210=4.8MHZ/210=4687.5HZ, so Fsetp ÷ 2=2343.75HZ
Frequency as locked is F01=365.65MHZ, getting (365.65MHZ/4687.5HZ=78005.33) fractional part is 0.33, equally, as the frequency F02=365.6468MHZ that will lock, getting (365.6468MHZ/4687.5HZ=78004.65) fractional part is 0.65, makes decimal be c herein, and can measure from circuit, frequency change 2343.75HZ, VC_TCXO need the voltage deviation of about 750mV to go adjustment to control, so herein
=750mV.Then there are two kinds of situations below:
The first: 0≤fractional part < 0.5
Voffset1=
=1500*c+Vref
The second: 0.5≤fractional part < 1
Voffset2=
=1500*(c-1)+Vref
Be more than the voltage-controlled voltage model drawn, utilize software algorithm to make locking frequency finally converge to target frequency by this model; Only need by a certain frequency calibration during use, then software can pass through this calibration value, automatically converts, draw the voltage-controlled magnitude of voltage of each frequency, finally obtain target frequency accurately according to voltage-controlled voltage model.
(2) test data contrast
Table 1 to table 4 is use this invention technology and do not use the every data target contrast of this invention technology.
Table one, phase-lock-ring output frequency test data
Table two is phase noise vs's test data:
Table three is contrast test data locking time:
Table four is the table of comparisons of fractional stray frequency
As can be seen from the data of above four forms, after using this invention technology, not only phase-lock-ring output frequency precision significantly improves, and fractional stray frequency obviously reduces simultaneously, and phase noise and locking time all can not be affected.
The DMR full duplex digital handset system mentioned in above-mentioned enforcement sample and literary composition is available to be familiar with person in the art to realize or to use of the present invention; those familiar with ordinary skill in the art can be without departing from the present invention in the case of the inventive idea; various modifications or change are made to above-mentioned enforcement sample; thus protection scope of the present invention not limit by above-mentioned enforcement sample, and should be the maximum magnitude meeting the inventive features that patent requirements is mentioned.
The Chinese and English noun table of comparisons related in the present invention.
Claims (4)
1. improves a method for phase-lock-ring output frequency precision, it is characterized in that: central processing unit works as follows, and it is phase-locked to carry corresponding direct-current control voltage to carry out by the voltage-controlled pin of VC---_TCXO to phase-locked loop circuit,
S100, program start;
S200, CPU are according to target frequency configuration pll parameter;
The magnitude of voltage Vref of the more accurate frequency prestored is called in temporary storage by S300, CPU;
S400, draw frequency division value with the output frequency of phase-locked loop divided by the minimum frequency stepping-in amount of this phase-locked loop;
S500, the selection of frequency division value fractional part and the calculating of direct-current control voltage;
If the fractional part of S510 frequency division value is less than between 0.5 between being more than or equal to 0, then calculate the first direct-current control voltage by formula (1);
Voffset1=2*△VFsetp/2*a+Vref（1）
In formula, Voffset1 is the first direct-current control voltage; △ VFsetp/2 is the direct voltage corrected value of 1/2 minimum frequency stepping-in amount; A be frequency division value be less than fractional part between 0.5 between being more than or equal to 0; Vref is the DC voltage value of more accurate frequency;
If the fractional part of S520 frequency division value is less than between 1 between being more than or equal to 0.5, then calculate the second direct-current control voltage by formula (2);
Voffset2=Vref-2*△VFsetp/2*b
In formula, Voffset2 is the second direct-current control voltage; △ VFsetp/2 is the direct voltage corrected value of 1/2 minimum frequency stepping-in amount; B be frequency division value be less than fractional part between 1 between being more than or equal to 0.5; Vref is the DC voltage value of more accurate frequency;
First direct-current control voltage or the second direct-current control voltage are delivered to the voltage-controlled pin of VC---_TCXO by DAC by S600, CPU;
S700, converge to target frequency by phase-locked loop;
S800, end.
2. the method for raising phase-lock-ring output frequency precision according to claim 1, is characterized in that: described Voffset1 and Voffset2 draws in the steps below:
(1), in operating frequency range, frequency is divided into N section by minimum frequency stepping-in amount (Fsetp), in N section, gets wherein one section of N1, from N1, gather M frequency;
(2), with M the frequency gathered, M be more than or equal to 2 positive integer, choose wherein minimum Frequency point (f0) as calibration frequency reference point (Fref), record the voltage-controlled pin voltage (Vref) of VC_TCXO corresponding to this Frequency point, calibrate output frequency by the voltage of the voltage-controlled pin of VC_TCXO adjusting other M-1 frequency again, thus find the relation between the voltage-controlled voltage of this M-1 frequency and Vref;
(3), formula is utilized
=A.B(3) calculate the value of Voffset1 and Voffset2;
In formula (3), Fvco is the output frequency of PLL; Fsetp is minimum frequency stepping-in amount; Wherein A is the integer part in the frequency division value that draws of formula (3), and B is the fractional part in the frequency division value that draws of formula (3); The fractional part B of formula (3) has two kinds of situations,
The first: the value of fractional part B is more than or equal to 0 and is less than <0.5; The value of the second: fractional part B is more than or equal to 0.5 and is less than 1;
When the value of fractional part B be more than or equal to 0 be less than <0.5 time,
Δ Fvco=(A.B-A) * Fsetp, make A.B-A=a then Δ Fvco=a*Fsetp therefore, the first direct-current control voltage Voffset1 is drawn by formula (4):
Voffset1=
* Δ Fvco+Vref(4) simplify after,
Voffset1=
When the value of fractional part B be more than or equal to 0.5 be less than 1 time,
Δ Fvco '=(A.B-A-1) * Fsetp, make A.B-A-1=b then Δ Fvco=b*Fsetp therefore, the second direct-current control voltage Voffset2 is drawn by formula (5):
Voffset2=
* Δ Fvco '+Vref(5) simplify after,
Voffset2=
=Vref-2*△VFsetp/2*b。
3. a phase-locked loop frequency synthesizer, comprise central processing unit, digital to analog converter, voltage controlled temperature compensated crystal oscillator, phase-locked loop circuit, low pass filter and voltage controlled oscillator, modulation signal is flowed to phase-locked loop circuit by the voltage-controlled pin of voltage controlled temperature compensated crystal oscillator by central processing unit domination number weighted-voltage D/A converter, phase-locked loop circuit exports the target frequency with modulation signal by low pass filter and voltage controlled oscillator again, it is characterized in that: when phase-locked, central processing unit works as follows, and carry corresponding direct-current control voltage by the voltage-controlled pin of VC---_TCXO to phase-locked loop circuit,
S100, program start;
S200, CPU are according to target frequency configuration pll parameter;
The magnitude of voltage Vref of the more accurate frequency prestored is called in temporary storage by S300, CPU;
S400, draw frequency division value with the output frequency of phase-locked loop divided by the minimum frequency stepping-in amount of this phase-locked loop;
S500, the selection of frequency division value fractional part and the calculating of direct-current control voltage;
If the fractional part of S510 frequency division value is less than between 0.5 between being more than or equal to 0, then calculate the first direct-current control voltage by formula (1);
Voffset1=2*△VFsetp/2*a+Vref（1）
In formula, Voffset1 is the first direct-current control voltage; △ VFsetp/2 is the direct voltage corrected value of 1/2 minimum frequency stepping-in amount; A be frequency division value be less than fractional part between 0.5 between being more than or equal to 0; Vref is the DC voltage value of more accurate frequency;
If the fractional part of S520 frequency division value is less than between 1 between being more than or equal to 0.5, then calculate the second direct-current control voltage by formula (2);
Voffset2=Vref-2*△VFsetp/2*b
In formula, Voffset2 is the second direct-current control voltage; △ VFsetp/2 is the direct voltage corrected value of 1/2 minimum frequency stepping-in amount; B be frequency division value be less than fractional part between 1 between being more than or equal to 0.5; Vref is the DC voltage value of more accurate frequency;
First direct-current control voltage or the second direct-current control voltage are delivered to the voltage-controlled pin of VC---_TCXO by DAC by S600, CPU;
S700, converge to target frequency by phase-locked loop;
S800, end.
4. phase-locked loop frequency synthesizer according to claim 3, is characterized in that: described Voffset1 and Voffset2 draws in the steps below:
(1), in operating frequency range, frequency is divided into N section by minimum frequency stepping-in amount (Fsetp), in N section, gets wherein one section of N1, from N1, gather M frequency;
(2), with M the frequency gathered, M be more than or equal to 2 positive integer, choose wherein minimum Frequency point (f0) as calibration frequency reference point (Fref), record the voltage-controlled pin voltage (Vref) of VC_TCXO corresponding to this Frequency point, calibrate output frequency by the voltage of the voltage-controlled pin of VC_TCXO adjusting other M-1 frequency again, thus find the relation between the voltage-controlled voltage of this M-1 frequency and Vref;
(3), formula is utilized
=A.B(3) calculate the value of Voffset1 and Voffset2;
In formula (3), Fvco is the output frequency of PLL; Fsetp is minimum frequency stepping-in amount; Wherein A is the integer part in the frequency division value that draws of formula (3), and B is the fractional part in the frequency division value that draws of formula (3); The fractional part B of formula (3) has two kinds of situations,
The first: the value of fractional part B is more than or equal to 0 and is less than <0.5; The value of the second: fractional part B is more than or equal to 0.5 and is less than 1;
When the value of fractional part B be more than or equal to 0 be less than <0.5 time,
Δ Fvco=(A.B-A) * Fsetp, make A.B-A=a then Δ Fvco=a*Fsetp therefore, the first direct-current control voltage Voffset1 is drawn by formula (4):
Voffset1=
* Δ Fvco+Vref(4) simplify after,
Voffset1=
When the value of fractional part B be more than or equal to 0.5 be less than 1 time,
Δ Fvco '=(A.B-A-1) * Fsetp, make A.B-A-1=b then Δ Fvco=b*Fsetp therefore, the second direct-current control voltage Voffset2 is drawn by formula (5):
Voffset2=
* Δ Fvco '+Vref(5) simplify after,
Voffset2=
=Vref-2*△VFsetp/2*b。
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| CN202455335U (en) * | 2012-02-29 | 2012-09-26 | 湖北广兴通信科技有限公司 | Low-noise high-resolution fractional division frequency synthesizer |
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