CN102420606B - Low phase-noise and small step-frequency synthesized realizing method - Google Patents

Low phase-noise and small step-frequency synthesized realizing method Download PDF

Info

Publication number
CN102420606B
CN102420606B CN 201110369118 CN201110369118A CN102420606B CN 102420606 B CN102420606 B CN 102420606B CN 201110369118 CN201110369118 CN 201110369118 CN 201110369118 A CN201110369118 A CN 201110369118A CN 102420606 B CN102420606 B CN 102420606B
Authority
CN
China
Prior art keywords
phase
locked loop
making
pass filter
output
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
CN 201110369118
Other languages
Chinese (zh)
Other versions
CN102420606A (en
Inventor
冯伟
史浩
刘金川
王凯
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Beijing Aerospace Measurement and Control Technology Co Ltd
Original Assignee
Beijing Aerospace Measurement and Control Technology Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Beijing Aerospace Measurement and Control Technology Co Ltd filed Critical Beijing Aerospace Measurement and Control Technology Co Ltd
Priority to CN 201110369118 priority Critical patent/CN102420606B/en
Publication of CN102420606A publication Critical patent/CN102420606A/en
Application granted granted Critical
Publication of CN102420606B publication Critical patent/CN102420606B/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Landscapes

  • Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)

Abstract

The invention discloses a low phase-noise and small step-frequency synthesized realizing method, which comprises the following steps: taking constant temperature crystal oscillator output as a reference signal to be input into a phase locked loop system and selecting a low pass filter meeting the low phase-noise condition as a low pass filter in the phase locked loop system; increasing the orders of the low pass filter to four orders, and making the product of the resistance by the capacitance of the fourth order be matched with the product of the resistance by the capacitance of the third order, wherein the capacitance value of the fourth order is larger than 10 times the voltage control end parasitic capacitance of a voltage control oscillator; and regulating the output current of a charge pump of a phase locked loop chip in the phase locked loop system until eliminating phase noise bulges in an output phase-noise curve of the phase locked loop system, and taking the output under a set feedback frequency dividing coefficient of a feedback divider as the output of the phase locked loop system. Through the verification of an experiment, the method disclosed by the invention can realize 2MHz stepping uninterruptedly under the condition without DDS (digital display scope) as a reference so as to ensure the phase-noise stable transition.

Description

A kind of low little Step Frequency of making an uproar is mutually combined implementation method
Technical field
The present invention relates to the frequency synthesis technique field, relate in particular to a kind of low little Step Frequency of making an uproar mutually and combine implementation method.
Background technology
Along with the growing tension of radio resource and developing rapidly of radiotechnics, more and more stricter to the test accuracy requirement of radio signal, thus more and more higher to frequency resolution and two index requests of phase noise of local oscillator in test macro.The main body of local oscillator is phase-locked loop systems, and the frequency resolution of phase-locked loop systems and phase noise determine frequency resolution and the phase noise of local oscillator substantially.
As shown in Figure 1, phase-locked loop systems generally comprises a high stable, low referrer module of making an uproar mutually, a low pass filter, the VCO (Voltage-Controlled Oscillator, voltage controlled oscillator) of phase-locked loop chip and corresponding frequencies.What phase-locked loop chip was completed is the function in the dotted line frame in Fig. 1, and R is the coefficient of parametric frequency divider, and N is the coefficient of feedback divider.After phase-locked loop systems is stable, the reference frequency f of referrer module input refOutput frequency f with VCO vcoRelation as follows:
f ref R = f vco N
Frequency resolution refers to the minimum step of phase-locked loop systems between can two carrier waves of continual output.Phase noise characterizes the carrier wave output of phase-locked loop systems in the uncertainty of frequency domain, and its size can normalize to 1Hz with the ratio of the power spectral density of offset carrier certain frequency deviation place such as 1MHz and carrier power and weigh, and phase noise is hereinafter to be referred as making an uproar mutually.
Present phase-locked loop systems generally makes reference to realize the high-resolution of carrier frequency output with DDS, its resolution is to inferior 1Hz rank, can worsen 20log (N) doubly but the near-end of DDS is spuious, wherein N is Clock Multiplier Factor, and be mapped in the loop bandwidth of phase-locked loop systems, thereby make carrier wave output spuious with larger near-end; Realize that by reducing merely loop bandwidth the low of carrier wave output make an uproar mutually, the deterioration that can make near-end make an uproar mutually, and form larger noise projection near loop bandwidth, in the frequency of observing on the Phase noise measurement analyzer---the logarithmic curve of making an uproar mutually can show one obvious " bulge " (phase noisehump) on (being called for short the curve of making an uproar mutually), is called make an uproar mutually bulge or phase noise bulge.
The Spurious Free Dynamic Range of the spuious meeting of larger near-end reduction system, and form measure error; The bulge of making an uproar mutually on curve of making an uproar mutually not only affects attractive in appearance, and in some cases, the measurement result that can make the mistake.
Summary of the invention
The technical problem to be solved in the present invention is, provides a kind of low little Step Frequency of making an uproar mutually to combine implementation method, in the situation that do not adopt DDS as a reference, reduces when realizing the frequency output of high frequency resolution and makes an uproar mutually.
The technical solution used in the present invention is, the described low little Step Frequency of making an uproar is mutually combined implementation method, phase-locked loop systems comprises phase-locked loop chip, low pass filter and voltage controlled oscillator, and phase-locked loop chip comprises parametric frequency divider, phase discriminator and feedback divider, and described method comprises:
The output of constant-temperature crystal oscillator is inputted phase-locked loop systems as the reference signal, and select a low pass filter that satisfies the low condition of making an uproar mutually as the low pass filter in phase-locked loop systems;
The exponent number of described low pass filter is increased to quadravalence, and makes the resistance capacitance product of quadravalence and the resistance capacitance product coupling on the 3rd rank, and the capacitance of quadravalence is greater than the voltage-controlled end parasitic capacitance of 10 times of voltage controlled oscillators;
Regulate the size of the charge pump output current of phase-locked loop chip in phase-locked loop systems, the bulge of making an uproar mutually until the output of elimination phase-locked loop systems is made an uproar mutually in curve, this moment is with the output of the output under the feedback division coefficient of the feedback divider of setting as phase-locked loop systems.
Further, the described low condition of making an uproar mutually specifically comprises:
The output of phase-locked loop systems stable the showing of curve of making an uproar mutually: the bulge of not making an uproar mutually at the cut-off frequency place of low pass filter, and differ in the theoretical value that the cut-off frequency of low pass filter calculates according to the normalization noise floor of phase-locked loop chip with the interior beguine of the value of making an uproar mutually and be no more than 20dB.
Further, the resistance capacitance product of described quadravalence and the resistance capacitance product on the 3rd rank coupling specifically comprise:
The resistance capacitance product of quadravalence is 1～1.5 times of resistance capacitance product on the 3rd rank.
Further, described phase-locked loop chip is HMC700, HMC704 or ADF4350.
Further, the feedback division coefficient of the feedback divider of described setting is 1～17.
Further, the voltage controlled oscillator in described phase-locked loop systems is the V600ME20-LF chip of Z～communications company.
Further, described low pass filter is second order, three rank or quadravalence low pass filter.
Adopt technique scheme, the present invention has following advantages at least:
The low little Step Frequency of making an uproar mutually of the present invention is combined implementation method, through experimental verification, can be in the situation that for referencial use without DDS, continually realize the 2MHz stepping, even can reach the kHz stepping in some cases, the 1MHz of 2GHz carrier wave skew place mutually the value of making an uproar be only-135dBc/Hz, and with loop bandwidth in smooth place make an uproar mutually and compare the bulge of making an uproar mutually less than 3dB, guarantee to make an uproar mutually smooth transition.
Description of drawings
Fig. 1 is existing phase-locked loop systems structural representation;
Fig. 2 is phase-locked loop systems structural representation in first embodiment of the invention;
Fig. 3 is that in first embodiment of the invention, the low little Step Frequency of making an uproar is mutually combined the implementation method flow chart;
Fig. 4 is third-order low-pass filter structural representation in second embodiment of the invention;
Fig. 5 (a), (b) are for replacing second order and the quadravalence low-pass filter structure schematic diagram of third-order low-pass filter in second embodiment of the invention;
The contrast schematic diagram of Fig. 6 (a), (b), (c) make an uproar mutually curve and make an uproar mutually curve and curve of making an uproar mutually that adopts technical solution of the present invention to export when adopting common phase-locked loop active loop filter when for referencial use for the existing DDS of employing.
Embodiment
Reach for further setting forth the present invention technological means and the effect that predetermined purpose is taked, below in conjunction with accompanying drawing and preferred embodiment, the present invention is described in detail as after.
First embodiment of the invention, a kind of low little Step Frequency of making an uproar is mutually combined implementation method, the composition of phase-locked loop systems comprises phase-locked loop chip 10, low pass filter 20 and voltage controlled oscillator 30 as shown in Figure 2, and 10 of phase-locked ring cores comprise parametric frequency divider 11, phase discriminator 12 and feedback divider 13; Phase-locked loop chip can adopt the chips such as HMC700, HMC704 or ADF4350.Voltage controlled oscillator 30 in phase-locked loop systems adopts the V600ME20-LF chip of Z～communications company.The signal processing of above-mentioned phase-locked loop systems is prior art, so locate not describe in detail.
As shown in Figure 3, the described low little Step Frequency of making an uproar is mutually combined implementation method, comprises following concrete steps:
Step S101 inputs phase-locked loop systems with the output of constant-temperature crystal oscillator 40 as the reference signal, and selects a low pass filter 20 that satisfies the low condition of making an uproar mutually as the low pass filter in phase-locked loop systems.
Concrete, this low condition of making an uproar mutually specifically comprises:
The output of phase-locked loop systems stable the showing of curve of making an uproar mutually: the bulge of not making an uproar mutually at the cut-off frequency place of low pass filter, and differ in the theoretical value that the cut-off frequency of low pass filter calculates according to the normalization noise floor of phase-locked loop chip with the interior beguine of the value of making an uproar mutually and be no more than 20dB.
Low pass filter 20 can be second order, three rank or quadravalence low pass filter, preferably second-order low-pass filter.
Step S102 is increased to quadravalence with the exponent number of described low pass filter 20, and makes the resistance capacitance product of quadravalence and the resistance capacitance product coupling on the 3rd rank, and the capacitance of quadravalence is greater than the voltage-controlled end parasitic capacitance of 10 times of voltage controlled oscillators.To exponent number of the every increase of low pass filter 20, be exactly in fact resistance and the capacitive branch of a series connection of output point place's increase in its back-end.If the low pass filter that locks in step S101 20 has been quadravalence, need not increases exponent number to it again.
Concrete, the resistance capacitance product of described quadravalence mates with the resistance capacitance product on the 3rd rank, specifically comprises: the resistance capacitance product of quadravalence is 1～1.5 times of resistance capacitance product on the 3rd rank.
Step S103, by regulating the charge pump output current of phase-locked loop chip in phase-locked loop systems, the bulge of making an uproar mutually until the output of elimination phase-locked loop systems is made an uproar mutually in curve, this moment is with the output of the output under the feedback division coefficient of the feedback divider 13 of setting as phase-locked loop systems.Preferably, the feedback division coefficient of the feedback divider of this setting is 1～17.
Second embodiment of the invention, the given phase-locked loop system that forms take a selected chip adopts the 100MHz constant-temperature crystal oscillator as high stable, the low reference of making an uproar mutually as example; Adopt one to have the fractional frequency-division phase-locked loop chip HMC700 that regulates charge pump output current function, the reference divide ratio range of set value of its parametric frequency divider is R=1～16383, the feedback division coefficient of feedback divider comprises integral frequency divisioil coefficient part and little tree divide ratio part, and wherein fractional frequency division coefficient settings value scope is N Frac=0～(2 24-1); Adopt the V600ME20-LF of Z～communications company as VCO, its 2GHz carrier wave departs from the 1MHz place and makes an uproar mutually less than-135dBc/Hz.
The low little Step Frequency of making an uproar mutually of the present invention is combined implementation method, and detailed process is as follows:
S1: at first set up a lockable third-order low-pass filter in phase-locked loop systems, as shown in Figure 4.concrete, with a third-order low-pass filter access phase-locked loop systems, by the output of observing the upper phase-locked loop systems that shows of analyzer (also can watch by the Phase noise measurement function of frequency spectrograph) of making an uproar the mutually curve of making an uproar mutually, see and whether satisfy the low condition of making an uproar mutually, the low condition of making an uproar mutually refers to: the bulge (phase noise hump) of not making an uproar mutually at the cut-off frequency place of low pass filter, and differ in the theoretical value that the cut-off frequency of low pass filter calculates according to the normalization noise floor of phase-locked loop chip with the interior beguine of the value of making an uproar mutually and be no more than 20dB, if do not satisfy, change the element of three rank filters, mainly that the capacitance resistance value in three rank filters is finely tuned, until satisfy the low condition of making an uproar mutually, namely determine a more suitable phase-locked loop systems low pass filter this moment.This low pass filter that satisfies the low condition of making an uproar mutually has following feature: loop bandwidth is roughly the best theoretical loop bandwidth of 1.2 times, best theoretical loop bandwidth is to make an uproar mutually in PLL loop bandwidth and make an uproar mutually deviant when equating of VCO, for example make an uproar mutually in PLL loop bandwidth and be-109dBc/Hz, and VCO is-110dBc/Hz making an uproar mutually of offset carrier 200kHz place, and best theoretical loop bandwidth is 200kHz.In this step, third-order low-pass filter can also secondary low pass filter or the quadravalence low pass filter as shown in Fig. 5 (b) as shown in Fig. 5 (a) replace.
S2: realize the little step frequency output of phase-locked loop systems.Concrete, by the reference divide ratio set point of adjusting parametric frequency divider and the feedback division coefficient settings value of feedback divider, realize the little stepping of whole cycle of phase-locked loop.Its final output is determined by formula (1):
F vco = F int + F frac = F xtal R × N int + F xtal R × 2 24 × N frac = F pfd × N int + F pfd × N frac 2 24 - - - ( 1 )
Wherein, F vcoBe final output frequency, F int, F FracBe respectively integral frequency divisioil frequency, fractional frequency division frequency; F XtalBe reference frequency, take 100MHz as example;
F pfd = F xtal R Be phase demodulation frequency;
N intBe the integral frequency divisioil part set point of feedback divider, its span is 36～65567;
N FracBe the fractional frequency division part set point of feedback divider, its span is 0～(2 24-1);
R is with reference to the frequency division set point, and its span is 1～16383;
2 24The effective value of the fractional frequency division part of expression feedback divider is 24.
For this phase-locked loop systems, the minimum value Δ F of its output frequency resolution rate Δ F minAccomplish in theory:
ΔF min = 100 × 10 6 2 24 × 16383 × 36 = 0.013 Hz
In fact the frequency resolution of 0.013Hz is impossible, because the increase along with the reference divide ratio set point R of parametric frequency divider, the phase demodulation frequency of phase-locked loop chip sharply reduces, thereby causes the whole system loop bandwidth sharply to broaden, and causing makes an uproar in loop bandwidth mutually degenerates and even losing lock.Actual the value of R is generally 1～17 in application, and the output resolution ratio of whole phase-locked loop systems can unremittingly be accomplished (decimal is ignored in round numbers):
During R=17, ΔF min = 100 × 10 6 2 24 × 17 × 36 = 12 Hz ;
During R=1, ΔF min = 100 × 10 6 2 24 × 1 × 36 = 214 Hz .
But, in view of the value of R can change continuously from 1～17, if decimal is ignored in round numbers, in 12～214Hz scope, all can travel through every 12Hz, with these group data as base.In the reference frequency output of coupling VCO, as long as this group base of output frequency aliquot, phase-locked loop systems namely can be realized this Frequency point output, and the minimum resolution of obvious above-mentioned phase-locked loop systems output frequency is 12Hz.
Should be noted that a problem, phase-locked loop uses the fractional frequency division pattern, can form fractional stray, if F FracBe positioned at PLL loop bandwidth with or be positioned at phase demodulation frequency and deduct the PLL loop bandwidth scope, fractional stray will fall into PLL loop bandwidth and can't suppress, and forms more spuious.That is to say, preferred, establishing carrier wave is F 0, loop bandwidth is the cut-off frequency Fc of second-order low-pass filter, is preferably in (F 0-2Fc, F 0+ 2Fc) use technical scheme of the present invention outside scope, can obtain technique effect preferably.
S3: realize the low carrier wave output of making an uproar mutually of phase-locked loop systems.After the little stepping that successfully realizes phase-locked loop systems, take following way to realize the low output of making an uproar mutually of phase-locked loop systems.
Because the phase-locked loop systems that contains second order, third-order low-pass filter can cause phase noise leakage in PLL loop bandwidth, making to be made an uproar mutually by prevailing skew place of the noise floor of VCO own degenerates, and passive fourth-order system is under the same index of making an uproar mutually, the frequency output area is narrower, need to adjust its parameter.Therefore, adopt the method that increases the loop filter exponent number, increase the i.e. exponent number of a limit on the basis of the third-order low-pass filter that first step S1 again sets up, form the quadravalence low pass filter as shown in Fig. 5 (b), and the resistance capacitance product R4 * C4 of quadravalence is equated with the resistance capacitance product R3 * C3 on the 3rd rank, and guarantee the capacitance of quadravalence greater than the voltage-controlled end parasitic capacitance of 10 times of voltage controlled oscillators, thereby guarantee that the output of phase-locked loop systems carrier wave equals VCO in the noise floor at 1MHz place making an uproar mutually of the far-end skew of distance carrier wave as 1MHz place.
S4: that realizes that loop makes an uproar mutually seamlessly transits.
Concrete, by regulating the charge pump output current of phase-locked loop chip in phase-locked loop systems, the bulge of making an uproar mutually until the output of elimination phase-locked loop systems is made an uproar mutually in curve is at this moment with the output of the output under the feedback division coefficient of setting as phase-locked loop systems.By this means, can effectively reduce the fluctuating of making an uproar mutually of phase-locked loop systems carrier wave output, guarantee the smooth transition of making an uproar mutually.
The contrast schematic diagram of make an uproar mutually curve and the curve of making an uproar mutually when adopting common phase-locked loop active loop filter when adopting the curve of making an uproar mutually of technical solution of the present invention output for referencial use with existing employing DDS as shown in Figure 6.Fig. 6 (a) expression be DDS when making reference, when phase-locked loop realizes that the characteristic frequency small step is advanced, the curve of making an uproar mutually of output, wherein have larger near-end spuious (Near Band Spur); The curve of making an uproar mutually that Fig. 6 (a) expression adopts common phase-locked loop active loop filter to obtain has obvious phase noise bulge; Fig. 6 (c) expression be to adopt the curve of making an uproar mutually of exporting under technical solution of the present invention, can accomplish there is no near-end spuious, and there is no obvious phase noise bulge to have the better near-end inhibition of making an uproar mutually and seamlessly transit effect with making an uproar mutually.
The low little Step Frequency of making an uproar mutually of the present invention is combined implementation method, through experimental verification, can be in the situation that for referencial use without DDS, continually realize the 2MHz stepping, even can reach the kHz stepping in some cases, the 1MHz of 2GHz carrier wave skew place mutually the value of making an uproar be only-135dBc/Hz, and with loop bandwidth in smooth place make an uproar mutually and compare the bulge of making an uproar mutually less than 3dB, guarantee to make an uproar mutually smooth transition.
By the explanation of embodiment, should be to reach technological means and the effect that predetermined purpose takes to be able to more deeply and concrete understanding to the present invention, yet appended diagram only be to provide with reference to the use of explanation, the present invention is limited.

Claims (5)

1. the one kind low little Step Frequency of making an uproar is mutually combined implementation method, and phase-locked loop systems comprises phase-locked loop chip, low pass filter and voltage controlled oscillator, and phase-locked loop chip comprises parametric frequency divider, phase discriminator and feedback divider, it is characterized in that, described method comprises:
The output of constant-temperature crystal oscillator is inputted phase-locked loop systems as the reference signal, and select a low pass filter that satisfies the low condition of making an uproar mutually as the low pass filter in phase-locked loop systems;
The exponent number of described low pass filter is increased to quadravalence, and makes the resistance capacitance product of quadravalence and the resistance capacitance product coupling on the 3rd rank, and the capacitance of quadravalence is greater than the voltage-controlled end parasitic capacitance of 10 times of voltage controlled oscillators;
Regulate the size of the charge pump output current of phase-locked loop chip in phase-locked loop systems, the bulge of making an uproar mutually until the output of elimination phase-locked loop systems is made an uproar mutually in curve, this moment is with the output of the output under the feedback division coefficient of the feedback divider of setting as phase-locked loop systems;
The described low condition of making an uproar mutually specifically comprises:
The output of phase-locked loop systems stable the showing of curve of making an uproar mutually: the bulge of not making an uproar mutually at the cut-off frequency place of low pass filter, and differ in the theoretical value that the cut-off frequency of low pass filter calculates according to the normalization noise floor of phase-locked loop chip with the interior beguine of the value of making an uproar mutually and be no more than 20dB;
The resistance capacitance product of described quadravalence and the resistance capacitance product on the 3rd rank coupling specifically comprise:
The resistance capacitance product of quadravalence is 1～1.5 times of resistance capacitance product on the 3rd rank.
2. the low little Step Frequency of making an uproar mutually according to claim 1 is combined implementation method, it is characterized in that, described phase-locked loop chip is HMC700, HMC704 or ADF4350.
3. the low little Step Frequency of making an uproar mutually according to claim 2 is combined implementation method, it is characterized in that, the feedback division coefficient of the feedback divider of described setting is 1～17.
4. the low little Step Frequency of making an uproar mutually according to claim 1 is combined implementation method, it is characterized in that, the voltage controlled oscillator in described phase-locked loop systems is the V600ME20-LF chip of Z～communications company.
5. the low little Step Frequency of making an uproar mutually according to claim 1 is combined implementation method, it is characterized in that, described low pass filter is second order, three rank or quadravalence low pass filter.
CN 201110369118 2011-11-18 2011-11-18 Low phase-noise and small step-frequency synthesized realizing method Active CN102420606B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN 201110369118 CN102420606B (en) 2011-11-18 2011-11-18 Low phase-noise and small step-frequency synthesized realizing method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN 201110369118 CN102420606B (en) 2011-11-18 2011-11-18 Low phase-noise and small step-frequency synthesized realizing method

Publications (2)

Publication Number Publication Date
CN102420606A CN102420606A (en) 2012-04-18
CN102420606B true CN102420606B (en) 2013-11-06

Family

ID=45944867

Family Applications (1)

Application Number Title Priority Date Filing Date
CN 201110369118 Active CN102420606B (en) 2011-11-18 2011-11-18 Low phase-noise and small step-frequency synthesized realizing method

Country Status (1)

Country Link
CN (1) CN102420606B (en)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN111835340B (en) * 2020-09-21 2020-12-08 成都雷通科技有限公司 Double-loop frequency source for driving PLL (phase locked loop) by fine stepping broadband PLL
CN115425968B (en) * 2022-09-05 2023-06-02 北京中科睿信科技有限公司 Optimization method for phase-locked loop frequency hopping time

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6463112B1 (en) * 2000-05-25 2002-10-08 Research In Motion Limited Phase locked-loop using sub-sampling
CN101330290A (en) * 2008-07-24 2008-12-24 上海杰盛无线通讯设备有限公司 Device for generating wideband microwave local oscillation signal
CN102062859A (en) * 2009-11-16 2011-05-18 西安费斯达自动化工程有限公司 Novel TCAS (Traffic Collision Avoidance System) local oscillator design method

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7501905B2 (en) * 2006-12-13 2009-03-10 Advantest Corporation Oscillator circuit, PLL circuit, semiconductor chip, and test apparatus

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6463112B1 (en) * 2000-05-25 2002-10-08 Research In Motion Limited Phase locked-loop using sub-sampling
CN101330290A (en) * 2008-07-24 2008-12-24 上海杰盛无线通讯设备有限公司 Device for generating wideband microwave local oscillation signal
CN102062859A (en) * 2009-11-16 2011-05-18 西安费斯达自动化工程有限公司 Novel TCAS (Traffic Collision Avoidance System) local oscillator design method

Also Published As

Publication number Publication date
CN102420606A (en) 2012-04-18

Similar Documents

Publication Publication Date Title
US9762251B2 (en) Ultra low phase noise frequency synthesizer
CN101179262B (en) Filter circuit device
US8193866B2 (en) All-digital phase-locked loop
EP2425533B1 (en) Supply-regulated phase-locked loop (pll) and method of using
US8019564B2 (en) Systems and methods for calibrating the loop bandwidth of a phase-locked loop (PLL)
US20090274255A1 (en) Method and apparatus for stabilizing clock
CN102412837B (en) Method for realizing low spurious small-step frequency synthesizer
US11996852B2 (en) Compensation technique for the nonlinear behavior of digitally-controlled oscillator (DCO) gain
JP4903969B2 (en) Rotational frequency synthesizer
JP2019504520A (en) Ultra-low phase noise frequency synthesizer
US8803574B2 (en) Generating a tuned frequency output from a signal generator
US7310021B2 (en) Phase-locked loop with tunable-transfer function
CN205356307U (en) Frequency synthesizer of short wave receiver
CN102420606B (en) Low phase-noise and small step-frequency synthesized realizing method
US7701298B2 (en) Frequency locking structure applied to phase-locked loops
RU172814U1 (en) HYBRID FREQUENCY SYNTHESIS WITH IMPROVED SPECTRAL CHARACTERISTICS
CN106656176A (en) Wide-frequency-band agile frequency synthesizer
CN103368568A (en) Method for improving output frequency accuracy of phase locked loop and phase locked loop frequency synthesizer
CN103501174A (en) Low-noise reference signal generator and signal generation method
CN103312324A (en) Method and system for generating short-waveband signal
Metange et al. Ultra-Low Power Hybrid PLL Frequency Synthesizer with Lock Check Provisioning Efficient Phase Noise.
Xu et al. Design of Ultra-broadband microwave sources based on ADF4350
Pilipenko Testing of Numerical Simulation Methods for Hybrid Frequency Synthesizers
CN101841331A (en) Method for designing passive filter of charge pump phase-locked loop (CPPLL)
Lenshin et al. Modernization of Frequency Synthesizers of the VHF Radios

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
C14 Grant of patent or utility model
GR01 Patent grant