CN103367266A - 具有应力缓冲体的半导体封装结构 - Google Patents

具有应力缓冲体的半导体封装结构 Download PDF

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CN103367266A
CN103367266A CN2012100999647A CN201210099964A CN103367266A CN 103367266 A CN103367266 A CN 103367266A CN 2012100999647 A CN2012100999647 A CN 2012100999647A CN 201210099964 A CN201210099964 A CN 201210099964A CN 103367266 A CN103367266 A CN 103367266A
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stress buffer
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CN103367266B (zh
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陈逸男
徐文吉
叶绍文
刘献文
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Nanya Technology Corp
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Abstract

本发明公开了一种半导体封装结构，其包含一周缘部位具有多个模流注入口的载板、一个以上的芯片设在所述载板顶面、一模封体覆盖在所述载板与所述芯片上、多个焊锡凸块设在所述载板底面上、以及多个应力缓冲体设在所述载板底面上。

Description

具有应力缓冲体的半导体封装结构
技术领域
本发明涉及半导体封装结构，特别是涉及一种具有应力缓冲体的半导体封装结构，可避免封装后封装结构因高低温循环而发生的翘曲现象。
背景技术
为了要在有限的面积中达到更高的存储容量，动态随机存取存储器(Dynamic Random Access Memory，DRAM)架构开始朝向立体的堆叠式封装技术(3D stacked package)发展，此封装技术的原理在于将多个互连的存取芯片(die)堆叠在一单一的封装载体上，如此将可在同样的面积范围内达到数倍的储存容量。
在封装结构中，芯片的输出入端(I/O)须与外部的封装体电性互连，其多是通过打线接合(wire bonding)方式将芯片上的接合垫(pad)与封装载板上的接合指(finger)电性连接。在打线接合后，封装结构中尚须进行一模封工艺以填入模封材料，使得内部的芯片与外部隔绝。上述模封材料会受到固化将封装结构的裸露部位(如芯片的有源区域、接合线等)全部密封，使其不受外界的影响。完成封装工序的整个封装结构之后则可透过其底面的焊锡凸块(或称为锡球)来与一外部装置(如一电路板)电性连接。
对封装工艺来说，信赖度测试(reliability test)是其中相当重要的一环。封装结构由于其所使用的模封材料与载板本身多为两种不同的材料，故容易受到冷热环境的影响。在高低温循环测试中，因为材料热膨胀系数(Coefficientof thermal expansion，简称CTE)的不同，封装结构的各部位会受到往复的拉伸与收缩应力影响，而使封装体产生翘曲(warpage)的现象。此翘曲现象易使封装结构上已与外部装置连结的焊锡凸块疲劳破裂，进而脱结导致电性失效。
目前业界对于上述翘曲问题有数种解法，如使用热膨胀系数与载板较为相近的模封材料、改变芯片厚度或载板的厚度、采用芯片贴装薄膜(die attachedfilm，DAF)工艺、或是在微型球栅列阵(Micro BGA)结构的场合中利用一弹性体作为缓冲材料等。
有别于上述背景技术的作法，本发明提供了一种新颖的半导体封装结构，其透过在模封工序中产生应力缓冲结构来有效减缓翘曲的问题。
发明内容
有鉴于背景技术中因高低温热循环所易引发的翘曲问题，本发明的主要目的在提供一种新颖的半导体封装结构，其通过在载板底面设置应力缓冲体来代替焊锡凸块承受应力，以避免焊锡凸块因疲劳破裂而导致连接失效问题。
根据本发明的优选实施例，本发明提供了一种半导体封装结构，其包含一周缘部位具有多个模流注入口的载板、一个以上的芯片设在所述载板顶面、一模封体覆盖在所述载板与所述芯片上、多个焊锡凸块设在所述载板底面上、以及多个应力缓冲体设在所述载板底面上。
本发明通过简单的结构改良以及既有的模封工序直接在载板底部形成应力缓冲体，分担封装结构在低温时所承受的压应力，可有效避免疲劳破坏等问题，并显着节省封装工序的时间与成本。
附图说明
图1绘示出依据本发明优选实施例中一封装载板的顶面示意图。
图2绘示出依据本发明优选实施例中一封装载板的底面示意图。
图3绘示出依据本发明另一优选实施例中一封装载板的顶面示意图。
图4绘示出依据本发明另一优选实施例中一封装载板的底面示意图。
图5绘示出依据本发明优选实施例中所欲进行封装的载板与芯片置于模具中的横断面示意图。
图6绘示出依据本发明优选实施例中一封装结构的横断面示意图。
其中，附图标记说明如下：
100             封装载板         110b    芯片
100a            内核层           111     胶材
100b            阻焊层           113     接合线
101a            接合指           115a    接合垫
101b            接合指           115b    接合垫
103             模流注入口       120     模套
105             焊锡凸块         121     开口
106             封装体           122     空间
107             应力缓冲体       124     空间
109             定位针脚         130     电路板
110a            芯片
具体实施方式
下文中将以图示来说明本发明的优选实施例。首先，请参照图1，其绘示出依据本发明优选实施例中一封装结构的顶面示意图。如图1所示，本发明的封装载板100可为树脂或陶瓷材质的载板，其正面设有多个接合指(bondfinger)101a，其用于在芯片黏合后通过打线接合(wire bonding)方式来与芯片上的接合垫(pad)电性连接。封装载板100的中间可为一预定的黏晶区域，周缘部位则形成有多个模流注入口103，如开口或缺口，其目的在于在后续模封工序中让模封材料得以经由该注入口流至底层的空间中，以形成本发明所欲的应力缓冲体结构。
接着请参照图2，其绘示出依据本发明优选实施例中一完成模封工序的封装结构的底面示意图。如图2所示，本发明的封装载板100是为一种球栅阵列(Ball Grid Array，BGA)封装载板，其底面会设置有多个焊锡凸块(solderbump，或称为锡球)105借以与一外部装置(如一电路板)电性连接，并借由一定位针脚109来协助封装结构正确地定位设置在外部装置预定的黏合位置上。完成模封工序后，封装载板100的底面周缘处会形成多个应力缓冲体107，如图中所示的条状结构。
接着请同时参照图3与图4，其分别绘示出依据本发明另一优选实施例中一封装载板的顶面示意图以及封装结构的底面示意图。图3及图4所示结构与图1及图2所示结构的差异处在于两者的模流注入口103位置不同。对本发明来说，模流注入口103的位置会决定后续所形成的应力缓冲体107位置，如图1中的模流注入口103位置是设在载板四个侧边的中间部位，其后所形成的应力缓冲体107也因此位在载板底面的四个侧边的中间部位；图3中封装载板100的两侧边分别有两个模流注入口103，故其后所形成的应力缓冲体107也因此会位在载板底面的两个侧边处且会具有较长的长度。本发明的应力缓冲体107并不局限于如图2或图4所示的态样，其形状将可由后续模封工序所用的模套(mold chase)来决定。
接着请参照图5，其绘示出依据本发明优选实施例中所欲进行模封工艺的封装载板与芯片置于模具中的横断面示意图。如图5所示，本发明的封装载板100可包含一内核层100a以及覆盖在内核层100a上下两面的阻焊层100b。内核层100a的材质可为塑料或陶瓷材料，阻焊层100b则可为阻焊绿漆(solder mask)等。阻焊层202上设有一预定的黏晶区域，如封装载板100的中间区域。在双层球栅阵列封装架构(D2-BGA)的架构中，封装载板100的黏晶区域上会以层叠方式依序黏上两芯片110a，110b，如动态随机存取存储器(Dynamic Random Access Memory，DRAM)、小外形双列内存模组(Small OutlineDual In-line Memory Module，SO-DIMM)、低电流负荷双列内存模组(LoadReduced Dual In-line Memory Module，LR-DIMM)等高速、高容量的内存模块所用的芯片。所述芯片110a，110b可于黏晶工艺中借由涂布一层胶材(如环氧树脂胶)111来加以黏结。前述的接合指101a是设在黏晶区域外侧的封装载板100上，其自阻焊层100b的开口裸露出来。封装载板100的底面也会设有接合指101b，其设置方式将会视发明所采用的封装架构而定，如双层球栅阵列封装架构(D2-BGA)、双层窗式球栅阵列封装架构(D2-wBGA)、封装体叠层架构(Package on Package，POP)、或是重布层(Redistribution Layer，RDL)封装架构等封装架构。以一般的双层球栅阵列封装架构(D2-BGA)为例，载板正面的接合指101a会经由接合线113来分别与芯片110a，110b的接合垫115a，115b打线接合，载板底面的接合指101b则于完成模封工序后会布设前述的焊锡凸块105，以与外部装置连结。
在本发明实施例中，模封工艺所使用的模套120会特别设计成其在欲进行封装的载板及芯片置于该模套中时，会与封装载板100在模流注入口103下方的对应位置界定出一空间122，以供应力缓冲体107的塑型。在模封工序期间，模封材料F会从模套120的开口121注入封装载板100正面以及芯片110a，110b与模套120所界定出的空间124，所述模封材料在填满空间124后会继续往下流经模流注入口103，填满封装载板100底面的空间122。在完成填模工序，模套120会连同至于其内的封装结构一起置入烤箱中进行烘烤，使模套120中的模封材料固化。如此，即可在封装载板100底面的周缘处形成特定的应力缓冲体。
接着请参照图6，其绘示出依据本发明优选实施例中一完成模封工序的封装结构的横断面示意图。如图6所示，将模套120脱除后，封装载板100的正面会形成一封装体106覆盖住上下层芯片110a，110b与接合线113，封装载板100的底面周缘处则会形成应力缓冲体107。在较佳的情况下，所述应力缓冲体107的厚度T会与底面所布上的焊锡凸块105的厚度一致。如此，当整个封装结构因冷热温度循环之故而产生翘曲时，位于载板周缘处的应力缓冲体107会较内侧的焊锡凸块105优先承受压应力，发挥应力缓冲的效果，使得焊锡凸块105不会因载板翘曲之故而疲劳破裂，以致于与下方连结的电路板130分离而导致电路失效。
综合上述本发明优选实施例的说明，本发明通过简单的改变模套设计以及使用既有的模封工序等作法，即可直接在封装载板的底面形成应力缓冲体来分担封装结构在低温时所承受的压应力，有效避免疲劳破坏等问题，不会增加封装工序的时间与成本，是为一具竞争力的新颖封装技术。
以上所述仅为本发明的优选实施例而已，并不用于限制本发明，对于本领域的技术人员来说，本发明可以有各种更改和变化。凡在本发明的精神和原则之内，所作的任何修改、等同替换、改进等，均应包含在本发明的保护范围之内。

Claims (7)

1.一种半导体封装结构，其特征在于，包含：
载板，其周缘部位具有多个模流注入口；
一个以上的芯片，设在所述载板的顶面上；
模封体，覆盖在所述载板与所述芯片上；
多个焊锡凸块，设在所述载板的底面上；以及
多个应力缓冲体，设在所述载板的底面上对应所述多个模流注入孔的位置处。
2.根据权利要求1所述的半导体封装结构，其特征在于，所述多个应力缓冲体设在所述载板的底面的周缘部位。
3.根据权利要求1所述的半导体封装结构，其特征在于，所述多个应力缓冲体与所述模封体为相同材质且一体成型。
4.根据权利要求3所述的半导体封装结构，其特征在于，所述多个应力缓冲体与所述模封体的材质包含环氧树脂。
5.根据权利要求1所述的半导体封装结构，其特征在于，所述多个应力缓冲体为条状结构。
6.根据权利要求1所述的半导体封装结构，其特征在于，所述多个应力缓冲体的厚度与所述焊锡凸块相同。
7.根据权利要求1所述的半导体封装结构，其特征在于，所述芯片包含动态随机存取存储器。
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