CN103346792B - Eliminate method, device and digital pre-distortion method that in analog to digital conversion, clock is shaken - Google Patents

Abstract

The present invention discloses method, device and the digital pre-distortion method of eliminating clock shake in analog to digital conversion, relate to the pre-distortion technology in communication field, it is intended to provide a kind of and can eliminate method, device and the digital pre-distortion method that in analog-digital conversion process, clock is shaken. The technology of the present invention main points comprise: step 1: receive simulating signal z (t); Step 2: provide clocksignal h (t) to analog to digital conversion module, obtains composite signal r (t) using the product of this clocksignal h (t) with single-tone signal m (t) as being added in simulating signal z (t) with reference to signal q (t) simultaneously; Step 3: composite signal r (t) is carried out analog to digital conversion and obtains the completely identical complex digital signal r of two-way by analog to digital conversion module_jit(n); Step 4: to described complex digital signal r_jitN a wherein road of () obtains clock jitter sequences after carrying out jitter sequences estimationStep 5: utilize clock jitter sequencesTo described complex digital signal r_jitN another road of () carries out clock jitter elimination, thus obtain the pure numerary signal y (n) eliminating clock shake.

Description

Eliminate method, device and digital pre-distortion method that in analog to digital conversion, clock is shaken

Technical field

The present invention relates to the pre-distortion technology in communication field, particularly relate to method and the device of a kind of sampling clock shaking interference eliminated in digital pre-distortion feedback path, and have employed the pre-distortion method eliminating clock shaking interference.

Background technology

Power amplifier (PowerAmplifierPA) is one of core component in Modern Mobile Communications Systems, and its performance directly affects the performance quality of radio communication system. For raising the efficiency, amplifier works in the high efficient area close to saturation point usually, and now amplifier exists non-linear character. Owing to current communications signal is non-constant envelope, by intermodulation distortion and spectral regrowth will be produced after Image magnify, cause monkey-chatter and worsen the receiving apparatus error rate. For head it off, digital pre-distortion (DigitalPre-DistortionDPD) technology occurs. Having had the auxiliary of pre-distortion technology, power amplifier just can be operated near saturation point, and keeps well linearly thus improving the efficiency of power amplifier.

Such as Fig. 5, traditional digital pre-distortion method, comprise direct learning-oriented structure and indirect learning-oriented structure, it is necessary to power amplifier output signal is coupled by one or more feedback path, down coversion and filtering process and be finally converted to numerary signal in order to carry out predistortion device or power amplifier parameter estirmation. But, traditional digital pre-distortion method is not considered to feed back the impact of the clock shake that in path, analog to digital converter is introduced. Especially, for the signal of broadband, the shake of this clock will worsen the signal to noise ratio of sampled digital signal and affect the performance of digital pre-distortion.

Summary of the invention

Conventional digital pre-distortion method needs that power amplifier output signal is coupled by one or more feedback path, down coversion and filtering process and be finally converted to numerary signal in order to carry out predistortion device or power amplifier parameter estirmation. But, the analog to digital conversion module in feedback path can introduce clock shake, and especially for the signal of broadband, the shake of this clock will worsen the signal to noise ratio of sampled digital signal and affect the performance of digital pre-distortion.

Technical problem to be solved by this invention is: provide a kind of method and the device that can eliminate clock shake in analog-digital conversion process for above-mentioned Problems existing.

The present invention provides a kind of method eliminating clock shake in analog-digital conversion process, comprising:

Step 1: receive simulating signal z (t);

Step 2: provide clocksignal h (t) to analog to digital conversion module, obtains composite signal r (t) using the product of this clocksignal h (t) with single-tone signal m (t) as being added in simulating signal z (t) with reference to signal q (t) simultaneously; Select single-tone signal m (t) that the spectral range of its spectral range and described simulating signal z (t) is separated from each other;

Step 3: analog to digital conversion module composite signal r (t) is carried out analog to digital conversion obtain two-way completely identical meet numerary signal r_jit(n);

Step 4: to described complex digital signal r_jitN a wherein road of () obtains clock jitter sequences after carrying out jitter sequences estimation

Step 5: utilize clock jitter sequencesTo described complex digital signal r_jitN another road of () carries out clock jitter elimination, thus obtain the pure numerary signal y (n) eliminating clock shake.

Preferably, described step 4 comprises:

Step 401: by complex digital signal r_jit(n) and sequenceProduct carry out filtering to filter out reference digital signal r_q(n); Wherein,WithIt is respectively the amplitude of single-tone signal m (t) and the estimated value of phase place; f_mFor the frequency of single-tone signal m (t); T_sFor sampling clock period, the i.e. cycle of clocksignal h (t);

Step 402: to reference digital signal r_q(n) and constant (2 �� f_m)^-1Product get imaginary part, obtain clock jitter sequences

Preferably, described step 5 comprises:

Step 501: by complex digital signal r_jit(n) with carry out filtering to filter out the numerary signal y being mixed into shake_jit(n);

Step 502: to the numerary signal y being mixed into shake_jitN () carries out fourier transformation;

Step 503: by the result of fourier transformation and sequence j2 �� f_lIt is multiplied, product is carried out Fourier's inverse transformation; L=0,1 ... N-1, N are the frequency division number in simulating signal z (t), f_lFor the frequency of each frequency division in simulating signal z (t);

Step 504: the result that Fourier's inverse transformation is obtained and clock jitter sequencesIt is multiplied;

Step 505: the numerary signal y of shake will be mixed into_jitN () subtracts the multiplied result in step 504, the pure numerary signal y (n) of the clock that has been eliminated shake.

The present invention also provide can a kind of new digital pre-distortion method, the method that this new true method of digital budget have employed clock shake in elimination analog-digital conversion process of the present invention carries out analog to digital conversion to through down coversion and filtered feedback analog signal.

Present invention also offers a kind of device eliminating clock shake in analog-digital conversion process, comprising:

Simulating signal receiver module, for receiving simulating signal z (t);

Reference signal injection module, for providing clocksignal h (t) to analog to digital conversion module, the product of this clocksignal h (t) with single-tone signal m (t) is obtained composite signal r (t) as being added in simulating signal z (t) with reference to signal q (t) simultaneously; Select single-tone signal m (t) that the spectral range of its spectral range and described simulating signal z (t) is separated from each other;

Analog to digital conversion module, for composite signal r (t) is carried out analog to digital conversion obtain two-way completely identical meet numerary signal r_jit(n);

Clock jitter sequences estimation module, for described complex digital signal r_jitN a wherein road of () obtains clock jitter sequences after carrying out jitter sequences estimation

Clock jitter elimination module, for utilizing clock jitter sequencesTo described complex digital signal r_jitN another road of () carries out clock jitter elimination, thus obtain the pure numerary signal y (n) eliminating clock shake.

Preferably, described clock jitter sequences estimation module comprises:

Reference digital signal screening module, for by complex digital signal r_jit(n) and sequenceProduct carry out filtering to filter out reference digital signal r_q(n); Wherein,WithIt is respectively the amplitude of single-tone signal m (t) and the estimated value of phase place; f_mFor the frequency of single-tone signal m (t); T_sFor sampling clock period, the i.e. cycle of clocksignal h (t);

Get imaginary-part operation module, for reference digital signal r_q(n) and constant (2 �� f_m)^-1Product get imaginary part, obtain clock jitter sequences

Preferably, described clock jitter elimination module comprises:

The numerary signal screening module being mixed into shake, for by complex digital signal r_jit(n) with carry out filtering to filter out the numerary signal y being mixed into shake_jit(n);

Fourier transformation module, for the numerary signal y being mixed into shake_jitN () carries out fourier transformation;

Compensate and Fourier's inverse transform block, for by the result of fourier transformation and sequence j2 �� f_lIt is multiplied, and product is carried out Fourier's inverse transformation; L=0,1 ... N-1, N are the frequency division number in simulating signal z (t), f_lFor the frequency of each frequency division in simulating signal z (t);

Multiplying module, for the result that Fourier's inverse transformation obtained and clock jitter sequencesIt is multiplied;

Subtraction computing module, for being mixed into the numerary signal y of shake_jitN () subtracts the multiplied result in step 504, the pure numerary signal y (n) of the clock that has been eliminated shake.

In sum, owing to have employed technique scheme, the invention has the beneficial effects as follows:

The method of clock shake in elimination analog-digital conversion process provided by the invention and device effectively eliminate in analog-digital conversion process the clock shake introduced, it is to increase analog to digital conversion precision.

New digital pre-distortion method provided by the invention, have employed the method eliminating clock shake in analog-digital conversion process, and then eliminates digital pre-distortion feedback path clock shake to the impact of signal. Specifically can improve the signal to noise ratio of sampled digital signal, it is to increase power amplifier modeling or power amplifier are inverted the precision of model, improve digital pre-distortion to the linearization performance of power amplifier.

Accompanying drawing explanation

Examples of the present invention will be described by way of reference to the accompanying drawings, wherein:

Fig. 1 eliminates clock dither method flow process signal in digital-to-analog conversion process in the present invention.

Fig. 2 is that in Fig. 1, reference signal injects flow process signal.

Fig. 3 is that in Fig. 1, clock jitter sequences estimates flow process signal.

Fig. 4 is clock jitter elimination flow process signal in Fig. 1.

Fig. 5 is the signal of conventional digital predistortion architecture.

Fig. 6 is digital pre-distortion structure signal in the present invention.

Embodiment

All features disclosed in this specification sheets, or the step in disclosed all methods or process, except mutually exclusive feature and/or step, all can combine by any way.

Any feature disclosed in this specification sheets, unless specifically stated otherwise, all can be replaced by other equivalences or the alternative features with similar object. Unless specifically stated otherwise, that is, each feature is an example in a series of equivalence or similar characteristics.

As shown in Figure 1, Figure 2, the embodiment eliminating the method for clock shake in analog-digital conversion process comprises:

Step 1: receive simulating signal z (t) 109.

Step 2: provide clocksignal h (t) 205, h (t)=cos (2 �� f to analog to digital conversion module_sT+ �� (t)), f_sThe clock requency (this value is given value) of the crystal oscillator selected by expression, �� (t) represents phase place noise. It is added in simulating signal z (t) 109 to obtain composite signal r (t) 204, r (t)=z (t)+q (t) as with reference to signal q (t) 305 using the product of this clocksignal h (t) 303 and single-tone signal m (t) 304 simultaneously.

Wherein, single-tone signal is a cosine wave signal, m (t)=A_mcos(2��f_mt+��_m), because its frequency composition is single, single-tone signal of gaining the name. A_mRepresent the amplitude of single-tone (cosine) signal, f_mThe clock requency (this value is given value) of the crystal oscillator selected by expression, ��_mRepresent initial phase place. A_mAnd ��_mCan using conventional cosine and sine signal method for parameter estimation accurate calculation, its calculation result is designated as respectivelyWith

It is noted that this step needs select single-tone signal m (t) meeting this condition: its spectral range, i.e. frequency, be separated from each other with the spectral range of described simulating signal z (t), can not have overlap. Perform this step to should also be noted that and must ensure that the clocksignal h (t) when being multiplied with single-tone signal m (t) is completely identical with the clocksignal h (t) when delivering to analog to digital conversion module, identical comprising phase place, namely this two sub-steps should carry out simultaneously, or say clocksignal h (t) reach multiplier, D/A converter module time delay identical. What those skilled in the art knew guarantees that the blanking method that time delay is identical is all applicable to this step. Such as, when Design PCB circuit card ensure clocksignal h (t) reach multiplier, D/A converter module length of arrangement wire equal, then can ensure clocksignal h (t) reach multiplier, D/A converter module time delay equal.

Above-mentioned various variable t is continuous real number.

Step 3: composite signal r (t) is carried out analog to digital conversion and obtains the completely identical complex digital signal r of two-way by analog to digital conversion module 201_jit(n), r_jitN ()=r (nTs), n are 0,1,2 ... integer, T_s=1/f_sRepresent the sampling clock period. Owing to analog to digital conversion module 201 can introduce clock shake in switching process, thus signal is caused interference.

Step 4: to described complex digital signal r_jitN a wherein road 206 of () obtains clock jitter sequences after carrying out jitter sequences estimation208;

Step 5: utilize clock jitter sequences208 couples of described complex digital signal r_jitN another road 207 of () carries out clock jitter elimination, thus obtain the pure numerary signal y (n) 110 eliminating clock shake.

Such as Fig. 3, in an alternative embodiment of the invention, described step 4 comprises further:

Step 401: by complex digital signal r_jit(n) 206 and sequenceThe product of 404 carries out filtering to filter out reference digital signal r_q(n) 405; Wherein,WithIt is respectively the amplitude of single-tone signal m (t) and the estimated value of phase place; f_mFor the frequency of single-tone signal m (t); T_sFor sampling clock period, the i.e. cycle of clocksignal h (t).

Complex digital signal r_jitN () 206 represents for r_jit(n)=z(nT_s+��_n)+q_jitN (), when during the frequency of single-tone signal is lower than simulating signal z (t) during minimum frequency division, adopting low-pass filtering to filter out reference digital signal r_q(n), it is possible to conveniently obtain clock jitter sequences

Step 402: to reference digital signal r_q(n) and constant (2 �� f_m)^-1Product get imaginary part, obtain clock jitter sequences

First the discrete signal h of the clocksignal h (t) 303 in composite signal r (t) 204 after analog to digital conversion module 201 is analyzed_jitN (), represents and is:

h_jit(n)=cos(2��f_snT_s+2��f_s��_n+��(nT_s+��_n))

Wherein, T_s=1/f_sRepresent the sampling clock period; ��_nFor clock jitter sequences. Under normal conditions, phase place noise �� (t) is the slowly varying function of time, therefore can do such as lower aprons:

${\mathrm{\δ}}_n\≈-\frac{\mathrm{\β}\left(n{T}_s\right)}{2\mathrm{\π}{f}_s}$

And can do such as lower aprons further: �� (nT_s+��_n)�֦�(nT_s). Therefore, discrete signal h_jitN () can approximate representation be after analog to digital conversion:

h_jit(n)=cos(2��f_s��_n+��(nT_s))��1��

Therefore, reference signal q (t) 305 can represent for discrete digital signal is as follows through analog to digital conversion module 201:

$q_{\mathrm{jit}}\left(n\right)={\hat{A}}_m\cos (2\mathrm{\π}{f}_{m}n{T}_s+2\mathrm{\π}{f}_m{\mathrm{\δ}}_n+{\widehat{\mathrm{\θ}}}_m).$

Namely through the filtered reference digital signal r of low-pass filter 401_qN () 405 can represent:

$r_q\left(n\right)=\mathrm{LPF}\left\{\frac{2}{{\hat{A}}_m}{r}_{\mathrm{jit}}\left(n\right)e^{-j(2\mathrm{\π}{f}_{m}n{T}_s+{\widehat{\mathrm{\θ}}}_m)}\right\}$

$=\mathrm{LPF}\{({\hat{A}}_m\cos (2\mathrm{\π}{f}_{m}n{T}_s+2\mathrm{\π}{f}_m{\mathrm{\δ}}_n+{\widehat{\mathrm{\θ}}}_m)+z(n{T}_s+{\mathrm{\δ}}_n))\×\frac{2}{{\hat{A}}_m}{e}^{-j(2\mathrm{\π}{f}_{m}n{T}_s+{\widehat{\mathrm{\θ}}}_m)}\}$

$=\mathrm{LPF}\{(\frac{{\hat{A}}_m}{2}(e^{j(2\mathrm{\π}{f}_{m}n{T}_s+2\mathrm{\π}{f}_m{\mathrm{\δ}}_n+{\widehat{\mathrm{\θ}}}_m)}+e^{-j(2\mathrm{\π}{f}_{m}n{T}_s+2\mathrm{\π}{f}_m{\mathrm{\δ}}_n+{\widehat{\mathrm{\θ}}}_m)})+z(n{T}_s+{\mathrm{\δ}}_n))\×\frac{2}{{\hat{A}}_m}{e}^{-j(2\mathrm{\π}{f}_{m}n{T}_s+{\widehat{\mathrm{\θ}}}_m)}$

$\≈e^{j2\mathrm{\π}{f}_m{\mathrm{\δ}}_n}$

$=\cos \left(2\mathrm{\π}{f}_m{\mathrm{\δ}}_n\right)+j\sin \left(2\mathrm{\π}{f}_m{\mathrm{\δ}}_n\right)$

Design LPF(low-pass filter) cut-off bandwidth be less than f_m, then by other frequency components after LPF by filtering, only retainConsider ��_nValue very little, close to 0, therefore 2 �� f_m��_nAlso very little, so further the result of upper formula is done rough handling and obtain:

cos(2��f_md_n)+jsin(2��f_m��_n)��1+j2��f_m��_n

Therefore, to reference digital signal r_q(n) and constant (2 �� f_m)^-1Product get imaginary part, just can obtain clock jitter sequencesCertainly, those skilled in the art can rationally suspect, this step can also first to reference digital signal r_qN () gets imaginary part, then by imaginary part and constant (2 �� f_m)^-1Product.

Such as Fig. 4, in another embodiment, described step 5 comprises:

Step 501: by another road complex digital signal r_jit(n) 207 with carry out filtering to filter out the numerary signal y being mixed into shake_jit(n) 506. When during the frequency of single-tone signal is lower than simulating signal z (t) during minimum frequency division, adopting high pass to filter out the numerary signal y being mixed into shake_jit(n)506��

Step 502: to the numerary signal y being mixed into shake_jitN () 506 carries out fourier transformation 501;

Step 503: by the result of fourier transformation 501 and sequence j2 �� f_l508 are multiplied 502, and product is carried out Fourier's inverse transformation; L=0,1 ... N-1, N are the frequency division number in simulating signal z (t);

Step 504: the result that Fourier's inverse transformation is obtained and clock jitter sequencesIt is multiplied;

Step 505: the numerary signal y of shake will be mixed into_jitN () 506 subtracts the multiplied result in step 504, the pure numerary signal y (n) 110 of the clock that has been eliminated shake.

Complex digital signal r_jitN () 207 be the remaining numerary signal y being mixed into shake after Hi-pass filter filtering reference signal_jitN () 506 can represent:

y_jit(n)=z(nT_s+��_n)

Consider clock jitter sequences ��_nRelative to sampling period T_sVery little, therefore it being carried out first order Taylor series expansion is:

$y_{\mathrm{jit}}\left(t\right)=z\left(n{T}_s\right)+{\mathrm{\δ}}_n\stackrel{\·}{z}\left(n{T}_s\right)=y\left(n\right)+{\mathrm{\δ}}_n\stackrel{\·}{z}\left(n{T}_s\right)$

Wherein, y (n)=z (nT_s), z represents that z (t) is at moment t=nT_sFirst order derivative. Considering that the multi-carrier signal adopted in existing communication system carries out communicate (e.g., ofdm signal), therefore simulating signal z (t) can represent and is:

$z\left(t\right)=\frac{1}{\sqrt{N}}\underset{l=0}{\overset{N-1}{\mathrm{\Σ}}}{S}_l{e}^{j2\mathrm{\π}{f}_{l}t};$

Wherein, N represents carrier number, S_lFor launching symbol, f_lIt it is the frequency of l carrier wave. " Signals & Systems " textbook is pointed out " any physically realizable signal all exists Fourier's change ", namely, can launch according to Fourier series, therefore those skilled in the art are not difficult to expect, when simulating signal z (t) is for also being carried out spectral decomposition during general simulating signal, obtain its each frequency division signal, and the quantity of frequency division signal, therefore general simulating signal z (t) can also represent by upper formula.

Therefore y_jitN () can represent:

$y_{\mathrm{jit}}\left(n\right)=y\left(n\right)+{\mathrm{\δ}}_n\frac{1}{\sqrt{N}}\underset{l=0}{\overset{N-1}{\mathrm{\Σ}}}j2\mathrm{\π}{f}_l{S}_l{e}^{j2\mathrm{\π}{f}_{l}t}$

Wherein, jitter sequences ��_nBeing calculated, calculated value isThe transmitting symbol sequence S of original signal_lCan by Received signal strength y_jitThe Fourier transform F of (n)_lEstimate. Therefore, pure signal 110 can be obtained by following formula:

$y\left(n\right)=y_{\mathrm{jit}}\left(n\right)+{\widehat{\mathrm{\δ}}}_n\frac{1}{\sqrt{N}}\underset{l=0}{\overset{N-1}{\mathrm{\Σ}}}j2\mathrm{\π}{f}_l{F}_l{e}^{j2\mathrm{\π}{f}_{l}t}$

Wherein, signalCan be j2 �� f by transmitting symbol_lF_lSequence obtained by N point Fourier's inverse transformation.

Such as Fig. 5, the present invention also provide can a kind of new digital pre-distortion method, this new true method of digital budget have employed the method for clock shake in elimination analog-digital conversion process of the present invention to through carrying out analog to digital conversion through down coversion and filtered feedback analog signal.

Concrete digital pre-distortion method provided by the invention all comprises the following steps:

Predistortion (conversion reciprocal with distortion) is added in base-band digital baseband signal 107 to be launched by digital predistorter 100;

The numerary signal 108 being mixed into predistortion is divided into completely identical two-way, and wherein pre-distortion parameters estimation module 106 is sent on a road, and another road carries out digital-to-analog conversion 101, up-conversion and filtering 102 successively;

Signal after after filtering sends into power amplifier 103, and signal is launched through radio frequency antenna on the one hand after power magnification, is coupled into feedback loop on the other hand;

In the feedback loop, the signal 111 being coupled into sends into pre-distortion parameters estimation module 106 after entering down coversion and filtering 104, analog to digital conversion successively; Described analog to digital conversion adopts the method 105 of clock shake in aforesaid elimination analog-digital conversion process to change;

Pre-distortion parameters estimation module 106 calculates pre-distortion parameters, and exports to digital predistorter 100, and predistortion is added in base-band digital signal to be sent by digital predistorter 100, so circulates.

The digital-analog convertion method eliminating clock shake is applied in digital pre-distortion process; very outstanding technique effect can be brought; such as improve the signal to noise ratio of sampled digital signal; improve power amplifier modeling or power amplifier to invert the precision of model, improve digital pre-distortion to the linearization performance of power amplifier.

The present invention is not limited to aforesaid embodiment. The present invention expands to any new feature of disclosing in this manual or any combination newly, and the step of the arbitrary new method disclosed or process or any combination newly.

Claims (3)

1. eliminate the method for clock shake in analog-digital conversion process for one kind, it is characterised in that, comprising:

Step 1: receive simulating signal z (t);

Step 2: provide clocksignal h (t) to analog to digital conversion module, obtains composite signal r (t) using the product of this clocksignal h (t) with single-tone signal m (t) as being added in simulating signal z (t) with reference to signal q (t) simultaneously; Select single-tone signal m (t) that the spectral range of its spectral range and described simulating signal z (t) is separated from each other;

Step 3: composite signal r (t) is carried out analog to digital conversion and obtains the completely identical complex digital signal r of two-way by analog to digital conversion module_jit(n);

Step 4: to described complex digital signal r_jitN a wherein road of () obtains clock jitter sequences after carrying out jitter sequences estimation

Step 5: utilize clock jitter sequencesTo described complex digital signal r_jitN another road of () carries out clock jitter elimination, thus obtain the pure numerary signal y (n) eliminating clock shake;

Described step 4 comprises:

Step 401: by complex digital signal r_jit(n) and sequenceProduct carry out filtering to filter out reference digital signal r_q(n); Wherein,WithIt is respectively the amplitude of single-tone signal m (t) and the estimated value of phase place; f_mFor the frequency of single-tone signal m (t); T_sFor sampling clock period, the i.e. cycle of clocksignal h (t);

Step 402: to reference digital signal r_q(n) and constant (2 �� f_m)^-1Product get imaginary part, obtain clock jitter sequences

Described step 5 comprises:

Step 501: by complex digital signal r_jitN () carries out filtering to filter out the numerary signal y being mixed into shake_jit(n);

Step 502: to the numerary signal y being mixed into shake_jitN () carries out fourier transformation;

Step 503: by the result of fourier transformation and sequence j2 �� f_lIt is multiplied, product is carried out Fourier's inverse transformation; L=0,1 ... N-1, N are the frequency division number in simulating signal z (t), f_lFor the frequency of each frequency division in simulating signal z (t);

Step 504: the result that Fourier's inverse transformation is obtained and clock jitter sequencesIt is multiplied;

Step 505: the numerary signal y of shake will be mixed into_jitN () subtracts the multiplied result in step 504, the pure numerary signal y (n) of the clock that has been eliminated shake.

2. a digital pre-distortion method, it is characterised in that, adopt the method for clock shake in elimination analog-digital conversion process according to claim 1 to carry out analog to digital conversion to through down coversion and filtered feedback analog signal.

3. eliminate the device of clock shake in analog-digital conversion process for one kind, it is characterised in that, comprising:

Simulating signal receiver module, for receiving simulating signal z (t);

Reference signal injection module, for providing clocksignal h (t) to analog to digital conversion module, the product of this clocksignal h (t) with single-tone signal m (t) is obtained composite signal r (t) as being added in simulating signal z (t) with reference to signal q (t) simultaneously; Select single-tone signal m (t) that the spectral range of its spectral range and described simulating signal z (t) is separated from each other;

Analog to digital conversion module, obtains the completely identical complex digital signal r of two-way for composite signal r (t) carries out analog to digital conversion_jit(n);

Clock jitter sequences estimation module, for described complex digital signal r_jitN a wherein road of () obtains clock jitter sequences after carrying out jitter sequences estimation

Clock jitter elimination module, for utilizing clock jitter sequencesTo described complex digital signal r_jitN another road of () carries out clock jitter elimination, thus obtain the pure numerary signal y (n) eliminating clock shake;

Described clock jitter sequences estimation module comprises:

Reference digital signal screening module, for by complex digital signal r_jit(n) and sequenceProduct carry out filtering to filter out reference digital signal r_q(n); Wherein,WithIt is respectively the amplitude of single-tone signal m (t) and the estimated value of phase place; f_mFor the frequency of single-tone signal m (t); T_sFor sampling clock period, the i.e. cycle of clocksignal h (t);

Get imaginary-part operation module, for reference digital signal r_q(n) and constant (2 �� f_m)^-1Product get imaginary part, obtain clock jitter sequences

Described clock jitter elimination module comprises:

The numerary signal screening module being mixed into shake, for by complex digital signal r_jitN () carries out filtering to filter out the numerary signal y being mixed into shake_jit(n);

Fourier transformation module, for the numerary signal y being mixed into shake_jitN () carries out fourier transformation;

Compensate and Fourier's inverse transform block, for by the result of fourier transformation and sequence j2 �� f_lIt is multiplied, and product is carried out Fourier's inverse transformation; L=0,1 ... N-1, N are the frequency division number in simulating signal z (t), f_lFor the frequency of each frequency division in simulating signal z (t);

Multiplying module, for the result that Fourier's inverse transformation obtained and clock jitter sequencesIt is multiplied;

Subtraction computing module, for being mixed into the numerary signal y of shake_jitN () subtracts the multiplied result of multiplying module, the pure numerary signal y (n) of the clock that has been eliminated shake.