CN103346792A - Method and device for eliminating clock jitter in analog-to-digital conversion and digital pre-distortion method - Google Patents

Abstract

The invention discloses the method, apparatus and digital pre-distortion method of eliminating clock jitter in analog-to-digital conversion, the pre-distortion technology being related in communication field, it is desirable to provide one kind can eliminate the method, apparatus and digital pre-distortion method of clock jitter in analog-digital conversion process. Technical key point includes: step 1: being received analog signal z (t); Step 2: providing clock signal h (t) to analog-to-digital conversion module, while the product of the clock signal h (t) and tone signal m (t) being added in analog signal z (t) as reference signal q (t) and obtains composite signal r (t); Step 3: analog-to-digital conversion module carries out analog-to-digital conversion to composite signal r (t) and obtains the identical complex digital signal rjit (n) of two-way; Step 4: to the complex digital signal rjit (n) wherein all the way carry out jitter sequences estimation after obtain clock jitter sequence

Step 5: utilizing clock jitter sequence

Clock jitter elimination is carried out to the another way of the complex digital signal rjit (n), to obtain the pure digital signal y (n) for eliminating clock jitter.

Description

Eliminate method, device and the digital pre-distortion method of clock jitter in the analog-to-digital conversion

Technical field

The present invention relates to the pre-distortion technology in the communication field, relate in particular to method and device that a kind of sampling clock shake of eliminating in the digital pre-distortion feedback network is disturbed, and adopted and eliminated the pre-distortion method that clock jitter disturbs.

Background technology

Power amplifier (Power Amplifier PA) is one of core component in the Modern Mobile Communications Systems, and its performance directly affects the performance quality of wireless communication system.For raising the efficiency, amplifier is usually in the high efficient area work near saturation point, and this moment, there was nonlinear characteristic in amplifier.Because existing signal of communication is non-constant envelope, by producing intermodulation distortion and frequency spectrum hyperplasia after the non-linear amplification, causes monkey chatter and worsens the receiver error rate.Be head it off, digital pre-distortion (Digital Pre-Distortion DPD) technology occurred.The auxiliary of pre-distortion technology arranged, and power amplifier just can be operated near the saturation point, and keeps well linear, improves the efficient of power amplifier thus.

As Fig. 5, traditional digital pre-distortion method, comprise direct learning-oriented structure and indirect learning type structure, need one or more feedback network come to power amplifier output signal be coupled, down-conversion and filtering handles and finally is converted to digital signal in order to carry out predistorter or power amplifier parameter Estimation.Yet, do not consider the influence of the clock jitter that analog to digital converter is introduced in the feedback network in traditional digital pre-distortion method.Especially for broadband signal, this clock jitter will worsen the signal to noise ratio of sampled digital signal and influence the performance of digital pre-distortion.

Summary of the invention

The conventional digital pre-distortion method need one or more feedback network come to power amplifier output signal be coupled, down-conversion and filtering handles and finally is converted to digital signal in order to carry out predistorter or power amplifier parameter Estimation.Yet the analog-to-digital conversion module in the feedback network can be introduced clock jitter, and especially for broadband signal, this clock jitter will worsen the signal to noise ratio of sampled digital signal and influence the performance of digital pre-distortion.

Technical problem to be solved by this invention is: the problem at above-mentioned existence provides a kind of method and the device that can eliminate clock jitter in the analog-digital conversion process.

The invention provides a kind of method of eliminating clock jitter in the analog-digital conversion process, comprising:

Step 1: receive analog signal z (t);

Step 2: provide clock signal h (t) to analog-to-digital conversion module, the product with this clock signal h (t) and a tone signal m (t) is added to acquisition composite signal r (t) among the analog signal z (t) as reference signal q (t) simultaneously; Select tone signal m (t) that the spectral range of its spectral range and described analog signal z (t) is separated from each other;

Step 3: analog-to-digital conversion module carries out analog-to-digital conversion to composite signal r (t) and obtains the identical digital signal r that meets of two-way _Jit(n);

Step 4: to described complex digital signal r _Jit(n) wherein one the tunnel carry out obtaining the clock jitter sequence after jitter sequences is estimated

Step 5: utilize the clock jitter sequence

To described complex digital signal r _Jit(n) the clock jitter elimination is carried out on another road, thereby obtains to have eliminated the pure digital signal y (n) of clock jitter.

Preferably, described step 4 comprises:

Step 401: with complex digital signal r _Jit(n) and sequence Product carry out filtering to filter out reference digital signal r _q(n); Wherein,

With

Be respectively the amplitude of tone signal m (t) and the estimated value of phase place; f _mFrequency for tone signal m (t); T _sBe the sampling clock cycle, i.e. the cycle of clock signal h (t);

Step 402: to reference digital signal r _q(n) with constant (2 π f _m) ^-1Product get imaginary part, obtain the clock jitter sequence

Preferably, described step 5 comprises:

Step 501: with complex digital signal r _Jit(n) with carry out filtering to filter out the digital signal y that sneaks into shake _Jit(n);

Step 502: to sneaking into the digital signal y of shake _Jit(n) carry out Fourier transform;

Step 503: with result and the sequence j2 π f of Fourier transform _lMultiply each other, product is carried out Fourier inversion; L=0,1 ... N-1, N are the frequency division number among the analog signal z (t), f _lFrequency for each frequency division among the analog signal z (t);

Step 504: result and clock jitter sequence that Fourier inversion is obtained

Multiply each other;

Step 505: the digital signal y that will sneak into shake _Jit(n) deduct multiplied result in the step 504, the pure digital signal y (n) of the clock jitter that has been eliminated.

The present invention also provides can a kind of new digital pre-distortion method, and this new true method of digital budget has adopted the method for clock jitter in the elimination analog-digital conversion process of the present invention to carrying out analog-to-digital conversion through down-conversion and filtered feedback analog signal.

The present invention also provides a kind of device of eliminating clock jitter in the analog-digital conversion process, comprising:

The analog signal receiver module is used for receiving analog signal z (t);

The reference signal injection module is used for providing clock signal h (t) to analog-to-digital conversion module, and the product with this clock signal h (t) and a tone signal m (t) is added to acquisition composite signal r (t) among the analog signal z (t) as reference signal q (t) simultaneously; Select tone signal m (t) that the spectral range of its spectral range and described analog signal z (t) is separated from each other;

Analog-to-digital conversion module is used for that composite signal r (t) is carried out analog-to-digital conversion and obtains the identical digital signal r that meets of two-way _Jit(n);

Clock jitter sequencal estimation module is used for described complex digital signal r _Jit(n) wherein one the tunnel carry out obtaining the clock jitter sequence after jitter sequences is estimated

The clock jitter cancellation module is used for utilizing the clock jitter sequence

To described complex digital signal r _Jit(n) the clock jitter elimination is carried out on another road, thereby obtains to have eliminated the pure digital signal y (n) of clock jitter.

Preferably, described clock jitter sequencal estimation module comprises:

Reference digital signal screening module is used for complex digital signal r _Jit(n) and sequence

Product carry out filtering to filter out reference digital signal r _q(n); Wherein,

With

Be respectively the amplitude of tone signal m (t) and the estimated value of phase place; f _mFrequency for tone signal m (t); T _sBe the sampling clock cycle, i.e. the cycle of clock signal h (t);

Get the imaginary-part operation module, be used for reference digital signal r _q(n) with constant (2 π f _m) ^-1Product get imaginary part, obtain the clock jitter sequence

Preferably, described clock jitter cancellation module comprises:

Sneak into the digital signal screening module of shake, be used for complex digital signal r _Jit(n) with carry out filtering to filter out the digital signal y that sneaks into shake _Jit(n);

The Fourier transform module is used for sneaking into the digital signal y of shake _Jit(n) carry out Fourier transform;

Compensation and Fourier inversion module are used for result and sequence j2 π f with Fourier transform _lMultiply each other, and product is carried out Fourier inversion; L=0,1 ... N-1, N are the frequency division number among the analog signal z (t), f _lFrequency for each frequency division among the analog signal z (t);

The multiplying module is used for result and clock jitter sequence that Fourier inversion is obtained Multiply each other;

The subtraction module is for the digital signal y that will sneak into shake _Jit(n) deduct multiplied result in the step 504, the pure digital signal y (n) of the clock jitter that has been eliminated.

In sum, owing to adopted technique scheme, the invention has the beneficial effects as follows:

The method of clock jitter and device have effectively been eliminated the clock jitter of introducing in the analog-digital conversion process in the elimination analog-digital conversion process provided by the invention, have improved A/D conversion accuracy.

New digital pre-distortion method provided by the invention has adopted and has eliminated the method for clock jitter in the analog-digital conversion process, and then eliminated the influence of digital pre-distortion feedback network clock jitter to signal.Specifically can improve the signal to noise ratio of sampled digital signal, improve the invert precision of model of power amplifier modeling or power amplifier, improve digital pre-distortion to the linearization performance of power amplifier.

Description of drawings

The present invention will illustrate by example and with reference to the mode of accompanying drawing, wherein:

Fig. 1 is for eliminating clock jitter method flow signal in the digital-to-analogue conversion process among the present invention.

Fig. 2 is that reference signal is injected the flow process signal among Fig. 1.

Fig. 3 is clock jitter sequencal estimation flow process signal among Fig. 1.

Fig. 4 is that clock jitter is eliminated the flow process signal among Fig. 1.

Fig. 5 is the structural representation of conventional digital predistortion.

Fig. 6 is digital pre-distortion structural representation among the present invention.

Embodiment

Disclosed all features in this specification, or the step in disclosed all methods or the process except mutually exclusive feature and/or step, all can make up by any way.

Disclosed arbitrary feature in this specification is unless special narration all can be replaced by other equivalences or the alternative features with similar purpose.That is, unless special narration, each feature is an example in a series of equivalences or the similar characteristics.

As Fig. 1, Fig. 2, an embodiment who eliminates the method for clock jitter in the analog-digital conversion process comprises:

Step 1: receive analog signal z (t) 109.

Step 2: provide clock signal h (t) 205 to analog-to-digital conversion module, h (t)=cos (2 π f _sT+ β (t)), f _sRepresent the clock frequency (this value is given value) of selected crystal oscillator, β (t) represents phase noise.Product with this clock signal h (t) 303 and a tone signal m (t) 304 is added to acquisition composite signal r (t) 204 among the analog signal z (t) 109, r (t)=z (t)+q (t) as reference signal q (t) 305 simultaneously.

Wherein, tone signal is a cosine wave signal, m (t)=A _mCos (2 π f _mT+ θ _m), because its frequency content is single, the tone signal of gaining the name.A _mThe amplitude of expression single-tone (cosine) signal, f _mThe clock frequency (this value is given value) of representing selected crystal oscillator, θ _mThe expression initial phase.A _mAnd θ _mCan be with conventional cosine and sine signal method for parameter estimation accurate Calculation, its result of calculation is designated as respectively

With

It should be noted that the tone signal m (t) that needs to select to satisfy this condition in this step: its spectral range, i.e. frequency is separated from each other with the spectral range of described analog signal z (t), can not have overlapping.Carry out this step should also be noted that must guarantee with the clock signal h (t) of the clock signal h (t) of tone signal m (t) when multiplying each other when delivering to analog-to-digital conversion module identical, identical comprising phase place, be that this two sub-steps should be carried out simultaneously, to reach the time delay of multiplier, D/A converter module identical for clock signal h (t) in other words.The identical blanking method of time delay of guaranteeing that those skilled in the art know all is applicable to this step.For example, guarantee that when design PCB circuit board the length of arrangement wire that clock signal h (t) reaches multiplier, D/A converter module equates, can guarantee that then the time-delay that clock signal h (t) reaches multiplier, D/A converter module equates.

Above-mentioned various variable t is continuous real number.

Step 3: 201 couples of composite signal r of analog-to-digital conversion module (t) carry out analog-to-digital conversion and obtain the identical complex digital signal r of two-way _Jit(n), r _Jit(n)=and r (nTs), n is 0,1,2 ... integer, T _s=1/f _sThe expression sampling clock cycle.Because analog-to-digital conversion module 201 can be introduced clock jitter in transfer process, thereby signal is caused interference.

Step 4: to described complex digital signal r _Jit(n) wherein one the tunnel 206 carry out obtaining the clock jitter sequence after jitter sequences is estimated

208;

Step 5: utilize the clock jitter sequence

208 couples of described complex digital signal r _Jit(n) the clock jitter elimination is carried out on another road 207, thereby obtains to have eliminated the pure digital signal y (n) 110 of clock jitter.

As Fig. 3, in another embodiment of the present invention, described step 4 further comprises:

Step 401: with complex digital signal r _Jit(n) 206 and sequence

404 product carries out filtering to filter out reference digital signal r _q(n) 405; Wherein,

With Be respectively the amplitude of tone signal m (t) and the estimated value of phase place; f _mFrequency for tone signal m (t); T _sBe the sampling clock cycle, i.e. the cycle of clock signal h (t).

Complex digital signal r _Jit(n) 206 be expressed as r _Jit(n)=z (nT _s+ δ _n)+q _Jit(n), when the frequency of tone signal is lower than among the analog signal z (t) minimum frequency division, adopt low-pass filtering to filter out reference digital signal r _q(n), can conveniently obtain the clock jitter sequence

Step 402: to reference digital signal r _q(n) with constant (2 π f _m) ^-1Product get imaginary part, obtain the clock jitter sequence

At first analyze clock signal h (t) the 303 process analog-to-digital conversion modules 201 discrete signal h afterwards among the composite signal r (t) 204 _Jit(n), be expressed as:

h _jit(n)=cos(2πf _snT _s+2πf _sδ _n+β(nT _s+δ _n))

Wherein, T _s=1/f _sThe expression sampling clock cycle; δ _nBe the clock jitter sequence.Under normal conditions, phase noise β (t) is the slowly varying function of time, therefore can do following approximate:

${\mathrm{\δ}}_n\≈-\frac{\mathrm{\β}\left(n{T}_s\right)}{2\mathrm{\π}{f}_s}$

And can further do following approximate: β (nT _s+ δ _n) ≈ β (nT _s).Therefore, discrete signal h _Jit(n) after analog-to-digital conversion can approximate representation be:

h _jit(n)=cos(2πf _sδ _n+β(nT _s))≈1。

Therefore, can be expressed as the discrete digital signal through analog-to-digital conversion modules 201 as follows for reference signal q (t) 305:

$q_{\mathrm{jit}}\left(n\right)={\hat{A}}_m\cos (2\mathrm{\π}{f}_{m}n{T}_s+2\mathrm{\π}{f}_m{\mathrm{\δ}}_n+{\widehat{\mathrm{\θ}}}_m).$

Namely pass through low pass filter 401 filtered reference digital signal r _q(n) 405 can be expressed as:

$r_q\left(n\right)=\mathrm{LPF}\left\{\frac{2}{{\hat{A}}_m}{r}_{\mathrm{jit}}\left(n\right)e^{-j(2\mathrm{\π}{f}_{m}n{T}_s+{\widehat{\mathrm{\θ}}}_m)}\right\}$

$=\mathrm{LPF}\{({\hat{A}}_m\cos (2\mathrm{\π}{f}_{m}n{T}_s+2\mathrm{\π}{f}_m{\mathrm{\δ}}_n+{\widehat{\mathrm{\θ}}}_m)+z(n{T}_s+{\mathrm{\δ}}_n))\×\frac{2}{{\hat{A}}_m}{e}^{-j(2\mathrm{\π}{f}_{m}n{T}_s+{\widehat{\mathrm{\θ}}}_m)}\}$

$=\mathrm{LPF}\{(\frac{{\hat{A}}_m}{2}(e^{j(2\mathrm{\π}{f}_{m}n{T}_s+2\mathrm{\π}{f}_m{\mathrm{\δ}}_n+{\widehat{\mathrm{\θ}}}_m)}+e^{-j(2\mathrm{\π}{f}_{m}n{T}_s+2\mathrm{\π}{f}_m{\mathrm{\δ}}_n+{\widehat{\mathrm{\θ}}}_m)})+z(n{T}_s+{\mathrm{\δ}}_n))\×\frac{2}{{\hat{A}}_m}{e}^{-j(2\mathrm{\π}{f}_{m}n{T}_s+{\widehat{\mathrm{\θ}}}_m)}$

$\&ap;{\mathrm{<figure-callout\; id="2"\; label="e\; j"\; filenames="HDA00003488734500021.png"\; state="\{\{state\}\}">e</figure-callout>}}^j$

$=\cos \left(2\mathrm{\&pi;}{f}_m{\mathrm{\&delta;}}_n\right)+j\sin \left(2\mathrm{\&pi;}{f}_m{\mathrm{\&delta;}}_n\right)$

Design LPF(low pass filter) cut off band width is less than f _m, then by other frequency components behind the LPF by filtering, only keep

Consider δ _nValue very little, near 0, therefore 2 π f _mδ _nAlso very little, so further the result of following formula is done approximate processing and obtain:

cos(2πf _md _n)+jsin(2πf _mδ _n)≈1+j2πf _mδ _n

Therefore, to reference digital signal r _q(n) with constant (2 π f _m) ^-1Product get imaginary part, just can obtain the clock jitter sequence

Certainly, those skilled in the art can suspect rationally that this step also can be earlier to reference digital signal r _q(n) get imaginary part, again with imaginary part and constant (2 π f _m) ^-1Product.

As Fig. 4, in another embodiment, described step 5 comprises:

Step 501: with another road complex digital signal r _Jit(n) 207 with carry out filtering to filter out the digital signal y that sneaks into shake _Jit(n) 506.When the frequency of tone signal is lower than among the analog signal z (t) minimum frequency division, adopt high-pass filtering to filter out the digital signal y that sneaks into shake _Jit(n) 506.

Step 502: to sneaking into the digital signal y of shake _Jit(n) 506 carry out Fourier transform 501;

Step 503: with result and the sequence j2 π f of Fourier transform 501 _l508 multiply each other 502, and product is carried out Fourier inversion; L=0,1 ... N-1, N are the frequency division number among the analog signal z (t);

Step 504: result and clock jitter sequence that Fourier inversion is obtained Multiply each other;

Step 505: the digital signal y that will sneak into shake _Jit(n) 506 multiplied result that deduct in the step 504, the pure digital signal y (n) 110 of the clock jitter that has been eliminated.

Complex digital signal r _Jit(n) 207 through the remaining digital signal y that sneaks into shake after the high pass filter filtering reference signal _Jit(n) 506 can be expressed as:

y _jit(n)=z(nT _s+δ _n)

Consider clock jitter sequence δ _nWith respect to sampling period T _sVery little, therefore it is carried out the single order Taylor series expansion and be:

$y_{\mathrm{jit}}\left(t\right)=z\left(n{T}_s\right)+{\mathrm{\&delta;}}_n\stackrel{\&CenterDot;}{z}\left(n{T}_s\right)=y\left(n\right)+{\mathrm{\&delta;}}_n\stackrel{\&CenterDot;}{z}\left(n{T}_s\right)$

Wherein, y (n)=z (nT _s), z represents that z (t) is at moment t=nT _sFirst derivative.Consider that the multi-carrier signal that adopts in the existing communication system communicates (as, ofdm signal), so analog signal z (t) can be expressed as:

$z\left(t\right)=\frac{1}{\sqrt{N}}\underset{l=0}{\overset{N-1}{\mathrm{\&Sigma;}}}{S}_l{e}^{\mathrm{<figure-callout\; id="2"\; label="j"\; filenames="HDA00003488734500021.png"\; state="\{\{state\}\}">j</figure-callout>}2\mathrm{\&pi;}{f}_{l}t};$

Wherein, N represents carrier number, S _lBe emission symbol, f _lIt is the frequency of l carrier wave.Point out " any physically realizable signal all exists Fourier to change " in " Signals ﹠ Systems " textbook, namely, can be according to Fourier expansion, therefore those skilled in the art are not difficult to expect, when being general analog signal, analog signal z (t) also it can be carried out spectrum analysis, obtain its each fractional frequency signal, and the quantity of fractional frequency signal, therefore general analog signal z (t) also can represent by following formula.

So y _Jit(n) can be expressed as:

$y_{\mathrm{jit}}\left(n\right)=y\left(n\right)+{\mathrm{\&delta;}}_n\frac{1}{\sqrt{N}}\underset{l=0}{\overset{N-1}{\mathrm{\&Sigma;}}}\mathrm{<figure-callout\; id="2"\; label="j"\; filenames="HDA00003488734500021.png"\; state="\{\{state\}\}">j</figure-callout>}2\mathrm{\&pi;}{f}_l{S}_l{e}^{\mathrm{<figure-callout\; id="2"\; label="j"\; filenames="HDA00003488734500021.png"\; state="\{\{state\}\}">j</figure-callout>}2\mathrm{\&pi;}{f}_{l}t}$

Wherein, jitter sequences δ _nCalculated, calculated value is The emission symbol sebolic addressing S of primary signal _lCan be by receiving signal y _Jit(n) Fourier transform F _lEstimate.Therefore, pure signal 110 can be obtained by following formula:

$y\left(n\right)=y_{\mathrm{jit}}\left(n\right)+{\widehat{\mathrm{\&delta;}}}_n\frac{1}{\sqrt{N}}\underset{l=0}{\overset{N-1}{\mathrm{\&Sigma;}}}\mathrm{<figure-callout\; id="2"\; label="j"\; filenames="HDA00003488734500021.png"\; state="\{\{state\}\}">j</figure-callout>}2\mathrm{\&pi;}{f}_l{F}_l{e}^{\mathrm{<figure-callout\; id="2"\; label="j"\; filenames="HDA00003488734500021.png"\; state="\{\{state\}\}">j</figure-callout>}2\mathrm{\&pi;}{f}_{l}t}$

Wherein, signal

Can be j2 π f by the emission symbol _lF _lSequence obtain by N point Fourier inversion.

As Fig. 5, the present invention also provides can a kind of new digital pre-distortion method, and the method that this new true method of digital budget has adopted clock jitter in the elimination analog-digital conversion process of the present invention is to through carrying out analog-to-digital conversion through down-conversion and filtered feedback analog signal.

Concrete digital pre-distortion method provided by the invention all may further comprise the steps:

Digital predistorter 100 adds predistortion (conversion reciprocal with distortion) in the armed base-band digital baseband signal 107 to;

The digital signal 108 of sneaking into predistortion is divided into identical two-way, wherein one the tunnel sends into pre-distortion parameters estimation module 106, another road is carried out digital-to-analogue conversion 101, up-conversion and filtering 102 successively;

Send into power amplifier 103 through filtered signal, signal is coupled into feedback loop on the other hand through launching through radio-frequency antenna on the one hand after the power amplification;

In feedback loop, the signal 111 that is coupled into is sent into pre-distortion parameters estimation module 106 after entering down-conversion and filtering 104, analog-to-digital conversion successively; Described analog-to-digital conversion adopts the method 105 of clock jitter in the aforesaid elimination analog-digital conversion process to change;

Pre-distortion parameters estimation module 106 calculates pre-distortion parameters, and exports to digital predistorter 100, and digital predistorter 100 adds predistortion in the baseband digital signal to be sent to, so circulation.

The digital-analog convertion method of eliminating clock jitter is applied in the digital pre-distortion process; can bring very outstanding technique effect; for example improve the signal to noise ratio of sampled digital signal; improve the invert precision of model of power amplifier modeling or power amplifier, improve digital pre-distortion to the linearization performance of power amplifier.

The present invention is not limited to aforesaid embodiment.The present invention expands to any new feature or any new combination that discloses in this manual, and the arbitrary new method that discloses or step or any new combination of process.

Claims (7)

1. a method of eliminating clock jitter in the analog-digital conversion process is characterized in that, comprising:

Step 1: receive analog signal z (t);

Step 2: provide clock signal h (t) to analog-to-digital conversion module, the product with this clock signal h (t) and a tone signal m (t) is added to acquisition composite signal r (t) among the analog signal z (t) as reference signal q (t) simultaneously; Select tone signal m (t) that the spectral range of its spectral range and described analog signal z (t) is separated from each other;

Step 3: analog-to-digital conversion module carries out analog-to-digital conversion to composite signal r (t) and obtains the identical complex digital signal r of two-way _Jit(n);

Step 4: to described complex digital signal r _Jit(n) wherein one the tunnel carry out obtaining the clock jitter sequence after jitter sequences is estimated

Step 5: utilize the clock jitter sequence To described complex digital signal r _Jit(n) the clock jitter elimination is carried out on another road, thereby obtains to have eliminated the pure digital signal y (n) of clock jitter.

2. the method for clock jitter in the elimination analog-digital conversion process according to claim 1 is characterized in that described step 4 comprises:

Step 401: with complex digital signal r _Jit(n) and sequence

Product carry out filtering to filter out reference digital signal r _q(n); Wherein,

With

Be respectively the amplitude of tone signal m (t) and the estimated value of phase place; f _mFrequency for tone signal m (t); T _sBe the sampling clock cycle, i.e. the cycle of clock signal h (t);

Step 402: to reference digital signal r _q(n) with constant (2 π f _m) ^-1Product get imaginary part, obtain the clock jitter sequence

3. the method for clock jitter in the elimination analog-digital conversion process according to claim 2 is characterized in that described step 5 comprises:

Step 501: with complex digital signal r _Jit(n) with carry out filtering to filter out the digital signal y that sneaks into shake _Jit(n);

Step 502: to sneaking into the digital signal y of shake _Jit(n) carry out Fourier transform;

Step 503: with result and the sequence j2 π f of Fourier transform _lMultiply each other, product is carried out Fourier inversion; L=0,1 ... N-1, N are the frequency division number among the analog signal z (t), f _lFrequency for each frequency division among the analog signal z (t);

Step 504: result and clock jitter sequence that Fourier inversion is obtained Multiply each other;

Step 505: the digital signal y that will sneak into shake _Jit(n) deduct multiplied result in the step 504, the pure digital signal y (n) of the clock jitter that has been eliminated.

4. a digital pre-distortion method is characterized in that, adopts the method for clock jitter in the described elimination analog-digital conversion process of claim 1～3 to carrying out analog-to-digital conversion through down-conversion and filtered feedback analog signal.

5. a device of eliminating clock jitter in the analog-digital conversion process is characterized in that, comprising:

The analog signal receiver module is used for receiving analog signal z (t);

The reference signal injection module is used for providing clock signal h (t) to analog-to-digital conversion module, and the product with this clock signal h (t) and a tone signal m (t) is added to acquisition composite signal r (t) among the analog signal z (t) as reference signal q (t) simultaneously; Select tone signal m (t) that the spectral range of its spectral range and described analog signal z (t) is separated from each other;

Analog-to-digital conversion module is used for that composite signal r (t) is carried out analog-to-digital conversion and obtains the identical digital signal r that meets of two-way _Jit(n);

Clock jitter sequencal estimation module is used for described complex digital signal r _Jit(n) wherein one the tunnel carry out obtaining the clock jitter sequence after jitter sequences is estimated

The clock jitter cancellation module is used for utilizing the clock jitter sequence

To described complex digital signal r _Jit(n) the clock jitter elimination is carried out on another road, thereby obtains to have eliminated the pure digital signal y (n) of clock jitter.

6. the device of clock jitter in the elimination analog-digital conversion process according to claim 5 is characterized in that the method for clock jitter is characterized in that in the elimination analog-digital conversion process according to claim 1, and described clock jitter sequencal estimation module comprises:

Reference digital signal screening module is used for complex digital signal r _Jit(n) and sequence

Product carry out filtering to filter out reference digital signal r _q(n); Wherein,

With

Be respectively the amplitude of tone signal m (t) and the estimated value of phase place; f _mFrequency for tone signal m (t); T _sBe the sampling clock cycle, i.e. the cycle of clock signal h (t);

Get the imaginary-part operation module, be used for reference digital signal r _q(n) with constant (2 π f _m) ^-1Product get imaginary part, obtain the clock jitter sequence

7. the device of clock jitter in the elimination analog-digital conversion process according to claim 6 is characterized in that described clock jitter cancellation module comprises:

Sneak into the digital signal screening module of shake, be used for complex digital signal r _Jit(n) with carry out filtering to filter out the digital signal y that sneaks into shake _Jit(n);

The Fourier transform module is used for sneaking into the digital signal y of shake _Jit(n) carry out Fourier transform;

Compensation and Fourier inversion module are used for result and sequence j2 π f with Fourier transform _lMultiply each other, and product is carried out Fourier inversion; L=0,1 ... N-1, N are the frequency division number among the analog signal z (t), f _lFrequency for each frequency division among the analog signal z (t);

The multiplying module is used for result and clock jitter sequence that Fourier inversion is obtained

Multiply each other;

The subtraction module is for the digital signal y that will sneak into shake _Jit(n) deduct multiplied result in the step 504, the pure digital signal y (n) of the clock jitter that has been eliminated.

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