CN105447218A - Elimination method of clock jitter in radio frequency direct band pass sampling digital receiving system - Google Patents

Elimination method of clock jitter in radio frequency direct band pass sampling digital receiving system Download PDF

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Publication number
CN105447218A
CN105447218A CN201410808895.1A CN201410808895A CN105447218A CN 105447218 A CN105447218 A CN 105447218A CN 201410808895 A CN201410808895 A CN 201410808895A CN 105447218 A CN105447218 A CN 105447218A
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radio frequency
zeta
bandpass sampling
clock jitter
digital received
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张晓宇
邹月娴
徐祥俊
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Peking University Shenzhen Graduate School
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Peking University Shenzhen Graduate School
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Abstract

The invention relates to an elimination method of clock jitter in a radio frequency direct band pass sampling digital receiving system. The method realizes elimination of the clock jitter in the radio frequency direct band pass sampling digital receiving system through adopting the non-uniform sampling output value of the radio frequency direct band pass sampling digital receiving system, the band pass sampling theory, the digital down-conversion theory and the feature of the radio frequency direct band pass sampling digital receiving system. The method can select different cascading series according to an actual radio frequency direct band pass sampling digital receiving demand so as to satisfy the demanded clock jitter elimination performance. The method of the invention is low in actual realization complexity and good in elimination effect, is easy for a hardware to realize, imposes no restriction on the type of the input signal of the radio frequency direct band pass sampling digital receiving system and is especially suitable for application of the radio frequency direct band pass sampling digital receiving system in modern communication, radar and high precision digital instrument.

Description

Clock jitter removing method in a kind of radio frequency direct bandpass sampling digital received system
Technical field
The present invention relates to clock jitter elimination algorithm in a kind of radio frequency direct bandpass sampling digital received system, belong to high-speed, high precision Analog-digital Converter technology and communication technical field.
Background technology
A/D converter with high speed and high precision is the vitals of the contemporary electronic systems such as radar, Medical Instruments, communication system, and clock jitter is the key factor affecting Signal-to-Noise in analog to digital conversion.Traditional superhet and intermediate-frequency receiver, due to the restriction of its framework itself, itself have volume heaviness, the shortcoming of poor expandability, can not adapt to the development need of digital received system gradually.A kind of new solution uses the direct bandpass sampling framework of radio frequency.This reception programme make use of the thought of software radio, by ADC as far as possible near antenna, use analog to digital converter Direct Sampling radiofrequency signal, between antenna and analog to digital converter, only have tracking filter and amplifier, if the sensitivity of ADC is enough high, then amplifier also can be cancelled.Therefore, the design proposal of the direct bandpass sampling of radio frequency, it is made to have extremely strong dirigibility and Reconfigurability, the requirement of the multiple communication standard of current hardware compatibility can be adapted to, there is volume little, the feature that cost is low, simultaneously owing to which employs bandpass sampling mode, makes the power consumption of ADC and system greatly reduce.Desirable ADC can realize the uniform sampling of simulating signal.But due to the restriction of side circuit manufacturing process, make ADC inevitably produce deviation at rising edge (negative edge) jumping moment of sampling, will the performance of receiving system be affected.Radiofrequency signal is down-converted to again to analog signal sampling after intermediate frequency or base band by traditional reception framework, and the sampling rate of ADC sampled signal is not high, makes the clock jitter effect of analog to digital converter relatively little.And in radio frequency Direct Sampling digital received system, analog to digital converter wants radio frequency signal to carry out Direct Sampling, therefore, higher requirement is proposed to the accuracy of analog to digital converter sampling clock.Therefore, under the direct bandpass sampling of radio frequency, the compensation of clock jitter is study hotspot is also technological difficulties.
Technically, the impact normally by adopting digital post-compensation technology to carry out compensating clock shake at the AfD converter output of radio frequency Direct Sampling system.Document tracing research shows, so far the clock jitter Compensation Research of digital received system carry out extensive, main because current communication reception technique mainly uses digital intermediate frequency and zero intermediate frequency technology.Existing clock jitter technology is OFDM or LTE signal based on input signal mostly, convert the signal into frequency domain conversion and eliminate clock jitter effect, this kind of algorithm becomes domestic and international study hotspot at present, also there is document to show and the shake estimated value of receiving end is fed back to input end, use digital pre-distortion technology to eliminate the impact of shake at transmitting terminal, but require that the transmitting terminal of system and receiving end can be synchronous very well.To sum up, there is following limitation in existing clock jitter elimination algorithm: (1) can only compensate (Rutten to narrow band signal, R., L.J.Breems, andR.H.M.vanVeldhoven.Digitaljitter-cancellationfornarro wbandsignals.inCircuitsandSystems, 2008.ISCAS2008.IEEEInternationalSymposiumon.2008.); (2) high (Weller of computation complexity, D.S.andV.K.Goyal, BayesianPost-ProcessingMethodsforJitterMitigationinSampl ing.SignalProcessing, IEEETransactionson, 2011.59 (5): p.2112-2123.); (3) the digital received system of specific input signal is only suitable for, as (Rabbi such as OFDM, M.F.andC.C.Ko.Modeling, estimationandmitigationofcoloredtimingjitterforOFDMAsyst em.inConsumerCommunicationsandNetworkingConference (CCNC)); Therefore, study a kind of newly applied widely, computation complexity is low, and clock jitter elimination algorithm analog input signal being limited to few radio frequency direct bandpass sampling digital received system has important practical significance.
Summary of the invention
The object of the invention is the clock jitter compensation method proposing a kind of radio frequency direct bandpass sampling digital received system, it is good that this compensation method has compensation effect, the feature that computation complexity is low, unrestricted to frequency input signal, unrestrictedly wait outstanding advantages to the Received signal strength type of digital receiving system, the clock jitter of energy radio frequency direct bandpass sampling digital received system compensates.
The clock jitter compensation method of a kind of radio frequency direct bandpass sampling digital received system.Its thought is, utilize the actual samples output valve of radio frequency direct bandpass sampling digital received system, utilize the principle such as bandpass sample theory and Digital Down Convert, derive containing the relation between the non-uniform discrete signal shaken and error signal, realize estimation and the elimination of the clock jitter error of radio frequency direct bandpass sampling digital received system, concrete principle is expressed as follows, for radio frequency direct bandpass sampling digital received system, without loss of generality, if its input signal is:
r ( t ) = Re { s I ( t ) + j s Q ( t ) ) e j 2 π f c t } = s I ( t ) cos [ 2 π f c t ] - s Q ( t ) sin [ 2 π f c t ] - - - ( 1 )
Wherein, s i(t)+js qt () is the baseband equivalent signal that the bandpass signal of reception is corresponding, f cfor carrier frequency.If sampling dithering RMS (root mean square) value of ADC is ζ n, radio frequency direct bandpass sampling digital received system adopts bandpass sampling, then ADC output signal can be expressed as:
r ( n T s ′ + ζ n ) = Re { ( s I ( n T s ′ + ζ n ) + js Q ( n T s ′ + ζ n ) ) e j 2 π f c ( n T s ′ + ζ n ) } = s I ( n T s ′ + ζ n ) cos [ 2 π f c n T s ′ + 2 π f c ζ n ] - s Q ( n T s ′ + ζ n ) sin [ 2 π f c n T s ′ + 2 π f c ζ n ] - - - ( 2 )
Wherein, T s' be the ADC sampling period.Utilize bandpass sample theory and Digital Down Convert principle to obtain, the approximate expression that sampled signal transforms to base band is:
z n ≈ s ( n T s ) e j 2 π f c ζ n - - - ( 3 )
Wherein, T sfor the baseband signal samples cycle, z nit is the baseband signal (the non-uniform discrete signal for containing shake) that radio frequency direct bandpass sampling digital received system obtains after bandpass sampling and Digital Down Convert.S (nT s) be desirable even baseband discrete signal, and defined by following formula
s(nT s)=s I(nT s)+js Q(nT s)(4)
By (3) Shi Ke get,
z n ≈ s ( n T s ) + s ( n T s ) ( Σ k = 1 ∞ ( j 2 π f c ) k ζ n k k ! ) - - - ( 5 )
By (5) Shi Ke get, clock jitter is eliminated and can be calculated by following formula:
s(nT s)=z n-e(n)(6)
E (n) is for reconstructing the error signal obtained, and e (n) is calculated by following formula:
e ( n ) = s ( n T s ) ( Σ k = 1 ∞ ( j 2 π f c ) k ζ n k k ! ) - - - ( 7 )
(6) formula of utilization, can try to achieve formula (5)
Clock jitter removing method in radio frequency direct bandpass sampling digital received system, the steps include:
A baseband signal that () radio frequency direct bandpass sampling digital received system obtains after bandpass sampling and Digital Down Convert, according to formula (6) and (7) and Taylor series expansion m item, obtains following relational expression
e ( n ) = z n × ( Σ k = 1 m r nk + Σ k = 1 m ( - j 2 π f c ) k ζ n k k ! Σ k = 1 m ( j 2 π f c ) k ζ n k k ! ) - - - ( 8 )
In formula, r nkdetermined by following formula
r nk = ( j 2 π f c ) k ζ n k k ! - - - ( 9 )
Wherein, f cfor carrier frequency, m is selected summation item number.
B () calculates the uniform sampling baseband signal s (nT eliminating shake according to formula (6) s).
Beneficial effect of the present invention is: the clock jitter error of method energy radio frequency of the present invention direct bandpass sampling digital received system is eliminated, the input signal types of receiving system is not limited, input signal frequency range is not limited, is applicable to the situation that sample mode is bandpass sampling.(this radio frequency direct bandpass sampling digital received systematic parameter is the simulated environment adopting MATLAB to build: adopt LTE uplink signal as the Received signal strength of digital received system, carrier frequency 2.6GHz, sampling rate 245.76MHz, SNR18dB, clock jitter 0-50ps), the radio frequency direct bandpass sampling digital received system clock jitter eliminating method that the present invention proposes is verified.According to the inventive method, sampled signal is compensated, result shows, for the shake in 0-50ps, the BER (bit error rate) of this radio frequency direct bandpass sampling digital received system has remarkable lifting relative to before compensation, demonstrates the validity of the inventive method
Accompanying drawing explanation
Fig. 1 is the structural representation of radio frequency direct bandpass sampling digital received system.
Fig. 2 is the relation curve of clock jitter and system BER (bit error rate), and clock jitter scope is 0-50ps.
Fig. 3 is system BER (bit error rate) curve after using this algorithm to carry out jitter compensation.
Fig. 4 is the cascade structure block diagram (one-level) of the method for the invention.
Embodiment
Below in conjunction with drawings and Examples, the present invention is further illustrated.
Case study on implementation 1: radio frequency direct bandpass sampling digital received system (shown in Fig. 1) simulated environment of building using MATLAB is carried out clock jitter and is compensated for as example and (adopts LTE uplink signal as the Received signal strength of digital received system in experiment, carrier frequency 2.6GHz, sampling rate is 245.76MHz, SNR18dB).
A baseband signal that () radio frequency direct bandpass sampling digital received system obtains after bandpass sampling and Digital Down Convert is according to formula (8), and (9) calculate, wherein, and m=3, fc=2.6GHz
B () calculates the uniform sampling baseband signal s (nT after eliminating shake according to formula (6) s);
System BER (bit error rate) curve after compensation as shown in Figure 3, compared with system BER (bit error rate) curve do not compensated containing clock jitter (shown in Fig. 2), BER (bit error rate) performance of this system has had remarkable lifting compared to before compensation.

Claims (5)

1. clock jitter removing method in a radio frequency direct bandpass sampling digital received system, it is characterized in that for radio frequency direct bandpass sampling digital received system (DirectRadioFrequencySamplingReceive, DRFSR), the clock circuit shake existed, realize estimation and the elimination of the clock jitter error of radio frequency direct bandpass sampling digital received system, concrete principle is expressed as follows, for radio frequency direct bandpass sampling digital received system, without loss of generality, if its input signal is:
r ( t ) = Re { ( s I ( t ) + j s Q ( t ) ) e j 2 π f c t } = s I ( t ) cos [ 2 π f c t ] - s Q ( t ) sin [ 2 π f c t ] - - - ( 1 )
Wherein, s i(t)+js qt () is the baseband equivalent signal that the bandpass signal of reception is corresponding, f cfor carrier frequency.If sampling dithering RMS (root mean square) value of ADC is ζ n, radio frequency direct bandpass sampling digital received system adopts bandpass sampling, then ADC output signal can be expressed as:
r ( n T s ′ + ζ n ) = Re { ( s I ( n T s ′ + ζ n ) + j s Q ( n T s ′ + ζ n ) ) e j 2 π f c ( n T s ′ + ζ n ) } = s I ( n T s ′ + ζ n ) cos [ 2 π f c n T s ′ + 2 π f c ζ n ] - s Q ( n T s ′ + ζ n ) sin [ 2 π f c n T s ′ + 2 π f c ζ n ] - - - ( 2 )
Wherein, T s' be the ADC sampling period, utilize bandpass sample theory and Digital Down Convert principle to obtain, the approximate expression that sampled signal transforms to base band is:
z n ≈ s ( n T s ) e j 2 π f c ζ n - - - ( 3 )
Wherein, T sfor the baseband signal samples cycle, z nthe baseband signal (the non-uniform discrete signal for containing shake) that radio frequency direct bandpass sampling digital received system obtains after bandpass sampling and Digital Down Convert, s (nT s) be desirable even baseband discrete signal, and defined by following formula
s(nT s)=s I(nT s)+js Q(nT s)(4)
By (3) Shi Ke get,
z n ≈ s ( n T s ) + s ( n T s ) ( Σ k = 1 ∞ ( j 2 π f c ) k ζ n k k ! ) - - - ( 5 )
By (5) Shi Ke get, clock jitter is eliminated and is calculated by following formula:
s(nT s)=z n-e(n)(6)
E (n) is for reconstructing the error signal obtained, and e (n) is calculated by following formula:
e ( n ) = s ( n T s ) ( Σ k = 1 ∞ ( j 2 π f c ) k ζ n k k ! ) - - - ( 7 )
(6) formula of utilization, can try to achieve formula (5); To sum up, the elimination of clock jitter in this algorithm realization radio frequency direct bandpass sampling digital received system.
2. clock jitter removing method in a kind of radio frequency according to claim 1 direct bandpass sampling digital received system, is characterized in that, the steps include:
A baseband signal that () radio frequency direct bandpass sampling digital received system obtains after bandpass sampling and Digital Down Convert, according to (6) and (7) and Taylor series expansion m item, obtains following relational expression
e ( n ) = z n × ( Σ k = 1 m r nk + Σ k = 1 m ( - j 2 π f c ) k ζ n k k ! Σ k = 1 m ( j 2 π f c ) k ζ n k k ! ) - - - ( 8 )
In formula, r nkdetermined by following formula
r nk = ( j 2 π f c ) k ζ n k k ! - - - ( 9 )
Wherein, f cfor carrier frequency, m is selected summation item number;
B () calculates the uniform sampling baseband signal s (nT eliminating shake according to formula (6) s).
3. clock jitter removing method in a kind of radio frequency according to claim 1 direct bandpass sampling digital received system, it is characterized in that, only there is multiplication and sum operation in the calculating of the e (n) of its step (a).
4. clock jitter removing method in a kind of radio frequency according to claim 1 direct bandpass sampling digital received system, it is characterized in that, its collocation structure is the collocation structure of cascade.
5. clock jitter removing method in a kind of radio frequency according to claim 1 direct bandpass sampling digital received system, it is characterized in that, the clock jitter of radio frequency direct bandpass sampling digital received service system compensates, only require that radio frequency direct bandpass sampling digital received systematic sampling type is bandpass sampling, the input signal types of radio frequency direct bandpass sampling digital received system does not limit, input signal frequency range is not limited, is applicable to the requirement of compatible multiple communication standard in same equipment.
CN201410808895.1A 2014-12-22 2014-12-22 Elimination method of clock jitter in radio frequency direct band pass sampling digital receiving system Pending CN105447218A (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN114690213A (en) * 2022-05-30 2022-07-01 长沙金维信息技术有限公司 Baseband clock jitter analysis method of satellite navigation receiver

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1433189A (en) * 2002-01-15 2003-07-30 矽统科技股份有限公司 D/A converter and conversion method with compensation to reduce clock jitter
US6680634B1 (en) * 2002-12-03 2004-01-20 Nokia Corporation Self calibrating digital delay-locked loop
CN103346792A (en) * 2013-07-10 2013-10-09 电子科技大学 Method and device for eliminating clock jitter in analog-to-digital conversion and digital pre-distortion method

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1433189A (en) * 2002-01-15 2003-07-30 矽统科技股份有限公司 D/A converter and conversion method with compensation to reduce clock jitter
US6680634B1 (en) * 2002-12-03 2004-01-20 Nokia Corporation Self calibrating digital delay-locked loop
CN103346792A (en) * 2013-07-10 2013-10-09 电子科技大学 Method and device for eliminating clock jitter in analog-to-digital conversion and digital pre-distortion method

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
朱志东等: "一种宽带高性能TIADC时钟发生器", 《数据采集与处理》 *

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN114690213A (en) * 2022-05-30 2022-07-01 长沙金维信息技术有限公司 Baseband clock jitter analysis method of satellite navigation receiver

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Application publication date: 20160330