CN202111690U

CN202111690U - Digital analog converter

Info

Publication number: CN202111690U
Application number: CN2011201852636U
Authority: CN
Inventors: 高博
Original assignee: Individual
Current assignee: Individual
Priority date: 2011-06-03
Filing date: 2011-06-03
Publication date: 2012-01-11
Anticipated expiration: 2021-06-03

Abstract

The utility model relates to a digital analog converter, comprising a digital signal processor, wherein a frequency division counter is connected with an input clock, a system clock, an interpolator, an extractor and a check apparatus, wherein a data input is connected with the extractor through the interpolator, the extractor and input data are connected with the check apparatus, the check apparatus is connected with a buffer area, the buffer area is connected with a clock synthesizer and a multiplier, the multiplier is connected with a DAC chip, the DAC chip is connected with a linear phase filter, a direct current bias device and a field effect transistor-to-ground switch. A signal is input into the digital signal processor; the sampling rate is detected; when the sampling rate is appropriate, data are input into the buffer area, the clock synthesizer tracks sampling, and input clock jitter is filtered; and when the sampling rate is too high or too low, the original signal is interpolated and extracted, and the data are amplified and output. The digital analog converter has the characteristics of decreasing input clock noise, total harmonic wave distortion and phase distortion, and increasing signal to noise ratio and dynamic scope.

Description

A kind of digital to analog converter

Technical field

The utility model belongs to digital signal processing technique field, particularly a kind of digital to analog converter.

Background technology

Traditional digital to analog converter DAC system is directly inputted into digital signal adopts the DAC chip or imports the DAC chip again through the appearance rate converter; Carry out Butterworth filtering again; Regulate output amplitude through potentiometer, programmable resistive network or analog multiplier then, at last output.The Direct Digital input can not be eliminated clocking noise, can produce distortion, noise and phase distortion through sample rate conversion.Butterworth filter can produce phase distortion, and potentiometer, programmable resistive network and analog multiplier can produce noise and total harmonic distortion.

Summary of the invention

In order to overcome the deficiency of above-mentioned prior art, the purpose that the utility model adopts is to provide a kind of digital to analog converter, has the digital input clock noise of reduction, reduces the characteristics of total harmonic distortion and phase distortion, raising signal to noise ratio and dynamic range.

To achieve these goals, the technical scheme of the utility model employing is: a kind of digital to analog converter includes digital signal processor 1; Digital signal processor 1 is provided with frequency counter 11, and the input of frequency counter 11 is connected with input clock 12 and system clock 19, and the output of n times of interpolation device 13 links to each other with the input of m/extraction 14; The output of m/withdrawal device 14 links to each other with 2 to 1 final election devices 15; 2 to 1 final election devices 15 also are connected with input data 16, and input data 16 also are connected with n times of interpolation device 13 simultaneously, and n times of interpolation device 13, m/

withdrawal device

14 and 2 to 1 final election devices 15 all receive frequency counter 11 controls; The output of 2 to 1 final election devices 15 links to each other with buffering area 2; The filling indication end of buffering area 2, input end of clock link to each other with clock synthetic 3, and the input of clock synthetic 3 links to each other with system clock 19, and the output terminal of clock of buffering area 2, data output end also link to each other with multiplier 4; Multiplier 4 links to each other with amplitude control 20; Modulator 18 is also controlled in amplitude control 20, and modulator 18 and FET switch 8 over the ground link to each other, and amplitude control 20 is controlled by output amplitude 17; The clock of multiplier 4, data output end link to each other with the input of DAC chip 5; The output of DAC chip 5 links to each other with the input of linear phase low pass filter 6, and the output of linear phase low pass filter 6 links to each other with the input of direct current biasing device 7, and the output of direct current biasing device 7 and FET an end of switch 8 over the ground link to each other; The FET output of switch 8 over the ground links to each other with the input of linear phase low pass filter 9, and the output of linear phase low pass filter 9 links to each other with linear phase high pass filter 10.

Described linear phase low pass filter 6 can be the Bei Saier low pass filter.

Described direct current biasing device 7 can be a biasing resistor.

Described linear phase low pass filter 9 can be the Bei Saier low pass filter.

Described linear phase high pass filter 10 can be a capacitance.

Described DAC chip 5, linear phase low pass filter 6, direct current biasing device 7, FET over the ground switch 8, linear phase low pass filter 9 and linear phase high pass filter 10 be arranged on transform with analog part 21 in.

The beneficial effect of the utility model is:

The signal of the utility model is adjusted by amplitude control after offering buffering area, multiplier by clock is synthetic again, does not have direct relation with input clock, so can reduce the influence of input signal shake to output; Owing to increased the signal decision and the treatment system that constitute by 2 to 1 multiplexers, n times interpolation device and m/withdrawal device; Switch control and linear phase low pass filter are adopted in amplitude control; So can reduce the total harmonic distortion and the phase distortion of system, and improve the signal to noise ratio and the dynamic range of system; The utility model reduces digital input clock noise as much as possible, and does not introduce distortion and noise, and simulation output has only very little phase nonlinear and frequency band inhomogeneous, and output amplitude is adjustable, and loses very little to signal quality; Have the digital input clock noise of reduction, reduce the characteristics of total harmonic distortion and phase distortion, raising signal to noise ratio and dynamic range.

Description of drawings

Accompanying drawing is the structural representation of the utility model.

Embodiment

Below in conjunction with accompanying drawing the structural principle and the operation principle of the utility model are done further explain.

Referring to accompanying drawing, a kind of digital to analog converter includes digital signal processor 1; Digital signal processor 1 is provided with frequency counter 11; The input of frequency counter 11 is connected with input clock 12 and system clock 19, and the output of n times of interpolation device 13 links to each other with the input of m/withdrawal device 14, and the output of m/withdrawal device 14 links to each other with 2 to 1 final election devices 15; 2 to 1 final election devices 15 also are connected with input data 16; Input data 16 also are connected with n times of interpolation device 13 simultaneously, and n times of interpolation device 13, m/

withdrawal device

14 and 2 to 1 final election devices 15 all receive frequency counter 11 controls, and the output of 2 to 1 final election devices 15 links to each other with buffering area 2; The filling indication end of buffering area 2, input end of clock link to each other with clock synthetic 3; The input of clock synthetic 3 links to each other with system clock 19, and the output terminal of clock of buffering area 2, data output end also link to each other with multiplier 4, and multiplier 4 links to each other with amplitude control 20; Modulator 18 is also controlled in amplitude control 20; Modulator 18 and FET switch 8 over the ground link to each other, and amplitude control 20 receives output amplitude 17 controls, and the clock of multiplier 4, data output end link to each other with the input of DAC chip 5; The output of DAC chip 5 links to each other with the input of linear phase low pass filter 6; The output of linear phase low pass filter 6 links to each other with the input of direct current biasing device 7, and the output of direct current biasing device 7 and FET an end of switch 8 over the ground link to each other, and the FET output of switch 8 over the ground links to each other with the input of linear phase low pass filter 9; The output of linear phase low pass filter 9 links to each other with linear phase high pass filter 10, and DAC chip 5, linear phase low pass filter 6, direct current biasing device 7, FET switch 8, linear phase low pass filter 9 and linear phase high pass filter 10 over the ground are arranged in conversion and the analog part 21.

Described linear phase low pass filter 6 can be the Bei Saier low pass filter.

Described direct current biasing device 7 can be a biasing resistor.

Described linear phase low pass filter 9 can be the Bei Saier low pass filter.

Described linear phase high pass filter 10 can be a capacitance.

The utility model most preferred embodiment is: use PFGA (field programmable gate array) receiving digital signals, accomplish Digital Signal Processing at PFGA, the digital stream after handling is inputed to the DAC chip, export the signal of PWM modulator to FET switch over the ground.Then the output signal of DAC chip through behind Bei Saier low pass filter and the direct current biasing device with FET switch in parallel over the ground, amplify behind switch, the capacitance over the ground through Bei Saier low pass filter, FET more at last and export.

The utility model reduces digital input clock noise as much as possible, and the least possible introducing distortion and noise, and simulation output has only very little phase nonlinear and frequency band inhomogeneous, and output amplitude is adjustable, and loses very little to signal quality.

The operation principle of the utility model is:

Signal supplied with digital signal processor carries out sample rate and judges, if sample rate is suitable; Then with data with former sample rate input buffering; With the sample rate of importing in the synthetic trace buffer of clock, and according to the packing ratio adjustment output clock that cushions, thereby the input clock shake filtered; If sample rate is too high or too low; Then doubly or extract and be m/one with original signal interpolation n; Data adapting DAC chip 5 after feasible the processing enters data into aforesaid buffering again, and data are input in the DAC chip 5 through multiplier; Switch 8 is parallelly connected over the ground with FET after satisfying linear phase low pass filter 6, direct current biasing device 7, and signal amplifies output through linear phase low pass filter 9 more then; FET switch 8 is over the ground modulated by PFM or PWM, and modulator frequency, duty ratio and multiplier coefficients receive external adjustment, thereby realizes output amplitude control.

Claims

1. digital to analog converter; Include digital signal processor (1), it is characterized in that, digital signal processor (1) is provided with frequency counter (11); The input of frequency counter (11) is connected with input clock (12) and system clock (19); The output of n times of interpolation device (13) links to each other with the input of m/withdrawal device (14), and the output of m/withdrawal device (14) links to each other with 2 to 1 final election devices (15), and 2 to 1 final election devices (15) also are connected with input data (16); Input data (16) also are connected with n times of interpolation device (13) simultaneously; N times of interpolation device (13), m/withdrawal device (14) and 2 to 1 final election devices (15) all receive frequency counter (11) control, and the output of 2 to 1 final election devices (15) links to each other with buffering area (2), and the filling rate indication end of buffering area (2), input end of clock link to each other with clock synthetic (3); The input of clock synthetic (3) links to each other with system clock (19); The output terminal of clock of buffering area (2), data output end also link to each other with multiplier (4), and multiplier (4) links to each other with amplitude control (20), and modulator (18) is also controlled in amplitude control (20); Modulator (18) and FET switch (8) over the ground link to each other; Amplitude control (20) receives output amplitude (17) control, and the clock of multiplier (4), data output end link to each other with the input of DAC chip (5), and the output of DAC chip (5) links to each other with the input of linear phase low pass filter (6); The output of linear phase low pass filter (6) links to each other with the input of direct current biasing device (7); The output of direct current biasing device (7) and FET an end of switch (8) over the ground link to each other, and the FET output of switch (8) over the ground links to each other with the input of linear phase low pass filter (9), and the output of linear phase low pass filter (9) links to each other with linear phase high pass filter (10).