CN103780228B - A kind of clock jitter improves circuit and method - Google Patents

Abstract

The present invention relates to circuit design field, open a kind of clock jitter improves circuit and method, and clock jitter improves circuit and includes that current mirror, voltage reference produce circuit, sawtooth waveforms produces and voltage comparator circuit, frequency dividing circuit and control circuit；Voltage reference produces the first input end of circuit and is connected with current mirror, and the second input is connected with the outfan of control circuit, and the first input end of outfan and sawtooth waveforms generation and voltage comparator circuit that voltage reference produces circuit is connected；Sawtooth waveforms produces and the second input of voltage comparator circuit is connected with current mirror, and the 3rd input is connected with the outfan of control circuit, and sawtooth waveforms produces and the outfan of voltage comparator circuit is connected with frequency dividing circuit.The clock jitter that the embodiment of the present invention provides improves circuit, compared to the phase-locked loop of existing PLL circuit, has circuit module few, the simple advantage of circuit, owing to circuit module is less, circuit is simple, components and parts used are less, so the area of circuit is less, power consumption is less.

Description

A kind of clock jitter improves circuit and method

Technical field

The present invention relates to circuit design field, a kind of clock jitter improves circuit and method.

Background technology

In a lot of Circuits System, such as analog-digital converter (ADC, Analog-to-Digital Converter), digital-to-analogue conversion In device (DAC, Digital-to-Analog Converter), use the clock jitter (clock jitter) of clock to circuit Clearly, big clock jitter can have a strong impact on the performance of analog-digital converter or digital to analog converter in the impact of performance, therefore, In the analog-digital converter of high-speed, high precision or digital to analog converter, the shake to sampling clock is proposed strict requirements.

The circuit of existing reduction clock jitter uses PLL (Phase-Locked Loop, phaselocked loop) circuit, and PLL circuit is solid Some low-frequency filter characteristicses can effectively filter the radio-frequency component in clock jitter, thus reduces total clock jitter.

Owing to PLL circuit is a phase-locked loop, structure is complicated, and the circuit module related to is more, so power consumption is bigger.

Summary of the invention

In view of this, the invention aims to solve existing reduction clock jitter circuit structure complexity, circuit area Relatively big and that power consumption is bigger problem, technical scheme is as follows:

The first aspect of the application provides a kind of clock jitter and improves circuit, produces electricity including current mirror, voltage reference Road, sawtooth waveforms produce and voltage comparator circuit, frequency dividing circuit and control circuit；

Described voltage reference produces the first input end of circuit and is connected with described current mirror, and described voltage reference produces circuit The second input be connected with the outfan of described control circuit, described voltage reference produces outfan and the described sawtooth of circuit Ripple produces and the first input end of voltage comparator circuit connects；

Described sawtooth waveforms produces and the second input of voltage comparator circuit is connected with described current mirror, and described sawtooth waveforms produces Raw and voltage comparator circuit the 3rd input is connected with the outfan of described control circuit, and described sawtooth waveforms produces and voltage ratio The outfan of relatively circuit is connected with frequency dividing circuit；

Wherein:

The input input clock signal of described control circuit, outfan output control signal；

Described voltage reference produces circuit and receives the first electric current of described current mirror according to described control signal, according to described First electric current produces for described sawtooth waveforms and voltage comparator circuit provides comparison reference level；

Described sawtooth waveforms produces and the 3rd input of voltage comparator circuit receives described control signal, according to described control Signal, described sawtooth waveforms produces and the first input end of voltage comparator circuit receives described comparison reference level, described sawtooth waveforms Produce the second input with voltage comparator circuit and receive the second electric current of described current mirror, described second electric current electric capacity is filled Electricity produces sawtooth signal, exports square wave according to the comparative result of described comparison reference level and described sawtooth signal；

Described square wave is divided by described frequency dividing circuit, the clock signal after output improvement.

In conjunction with first aspect, in the first possible implementation of first aspect,

Described circuit also includes reference current source；

Described current mirror, described voltage reference produce circuit, described sawtooth waveforms produce and voltage comparator circuit respectively with institute State reference current source to connect；

Described current mirror produces circuit to described voltage reference, described sawtooth waveforms produces and voltage comparator circuit exports and institute State the electric current that reference current source is proportional.

In conjunction with the first possible implementation of first aspect or first aspect, possible at the second of first aspect In implementation,

Described voltage reference produces circuit and includes the first charging paths, the second charging paths；

Wherein,

Described first charging paths is connected in parallel with described second charging paths；

The input of described first charging paths and the input of described second charging paths are respectively with described current mirror even Connect；

Described first charging paths is periodically charged by described second charging paths.

In conjunction with the possible implementation of the second of first aspect, in the third possible implementation of first aspect,

Described first charging paths includes the first electric capacity and the first switch, described first electric capacity and described first switch It is connected in series by the first common port；

Described second charging paths includes the second electric capacity and second switch, described second electric capacity and described second switch It is connected in series by the second common port；

Described voltage reference produces circuit and also includes the 3rd switch；

First end of described 3rd switch is connected with described first common port, the described 3rd the second end switched and described the Two common ports connect；

The outfan that described first common port produces circuit as described voltage reference produces and voltage with described sawtooth waveforms Comparison circuit connects.

In conjunction with the third possible implementation of first aspect, in the 4th kind of possible implementation of first aspect,

Described voltage reference produces circuit and also includes the 4th switch and the 5th switch；

Described 4th switch, for described second electric capacity voltage amplitude before charging；

Described 5th switch, in parallel with described first electric capacity, described 5th switch is for described first electric capacity before charging Voltage amplitude.

In conjunction with the 4th kind of possible implementation of first aspect, in the 5th kind of possible implementation of first aspect,

Described sawtooth waveforms produces and voltage comparator circuit includes comparator, the 3rd electric capacity, the 6th switch and the 7th switch；

First end of described 3rd electric capacity is connected with described current mirror, the second termination reference current source of described 3rd electric capacity Earth terminal；

The inverting input of described comparator is connected with described first common port, the positive input of described comparator and institute The first end stating the 3rd electric capacity connects, and described in the Automatic level control of the outfan output of described comparator, the 7th switch cut-offs；

Described 6th switch, described 7th switch are in parallel with described 3rd electric capacity respectively, wherein:

Described 6th switch is for described 3rd electric capacity voltage amplitude before charging, and described 7th switch is for described the When three electric capacity normally work, periodic voltage resets.

The second aspect of the application provides a kind of clock jitter ameliorative way, is applied to clock jitter and improves circuit, institute State circuit and include that current mirror, voltage reference produce circuit, sawtooth waveforms produces and voltage comparator circuit, frequency dividing circuit and control electricity Road, method includes:

Described control circuit receives clock signal, exports control signal；

Described voltage reference produces circuit and receives the first electric current of described current mirror according to described control signal, according to described First electric current produces for described sawtooth waveforms and voltage comparator circuit provides comparison reference level；

Described sawtooth waveforms produces and the 3rd input of voltage comparator circuit receives described control signal, according to described control Signal, described sawtooth waveforms produces and the first input end of voltage comparator circuit receives described comparison reference level, the second input Receive the second electric current of described current mirror, described second electric current electric capacity charging is produced sawtooth signal, according to described comparison The comparative result output square wave of datum and described sawtooth signal；

Described square wave is divided by described frequency dividing circuit, the clock signal after output improvement.

The clock that the embodiment of the present invention provides improves circuit, the input input clock signal of control circuit 500, outfan Output control signal, control signal is used for controlling voltage reference and produces circuit, sawtooth waveforms generation and voltage comparator circuit, so that Voltage reference produces circuit 200 can receive the first electric current of current mirror 100, is that sawtooth waveforms produces and voltage according to the first electric current Comparison circuit 300 provides comparison reference level, and so that sawtooth waveforms produces and the first input end of voltage comparator circuit 300 It is able to receive that comparison reference level, the second input are able to receive that the second electric current of current mirror, and generates saw according to the second electric current Tooth ripple signal, exports square wave according to the comparative result of comparison reference level and sawtooth signal.From the foregoing, clock signal Produce circuit 200 through voltage reference, sawtooth waveforms produces and after voltage comparator circuit 300, exports square wave, and frequency dividing circuit 400 will The square wave frequency dividing received, the clock signal after output improvement, the clock that therefore the bright embodiment of this law provides improves circuit, successively Through control circuit 500, voltage reference produces circuit 200, sawtooth waveforms produces and voltage comparator circuit 300, frequency dividing circuit 400 After, improve the shake of clock.

Further, the clock jitter that the embodiment of the present invention provides improves circuit and includes that current mirror 100, voltage reference produce Circuit 200, sawtooth waveforms produce and voltage comparator circuit 300, frequency dividing circuit 400 and control circuit 500, compared to existing PLL The phase-locked loop of circuit, has circuit module few, the simple advantage of circuit, and owing to circuit module is less, circuit is simple, unit used Device is less, so the area of circuit is less, power consumption is less.

Accompanying drawing explanation

In order to be illustrated more clearly that the embodiment of the present invention or technical scheme of the prior art, below will be to embodiment or existing In having technology to describe, the required accompanying drawing used is briefly described, it should be apparent that, the accompanying drawing in describing below is only this Some embodiments of invention, for those of ordinary skill in the art, on the premise of not paying creative work, it is also possible to Other accompanying drawing is obtained according to these accompanying drawings.

Fig. 1 improves a kind of structural representation of circuit for the clock jitter that the embodiment of the present invention provides；

Fig. 2 improves another structural representation of circuit for the clock jitter that the embodiment of the present invention provides；

Fig. 3 improves another structural representation of circuit for the clock jitter that the embodiment of the present invention provides；

Fig. 4 improves a kind of circuit diagram of circuit for the clock jitter that the embodiment of the present invention provides；

Fig. 5 improves a kind of schematic diagram of control circuit in circuit for the clock jitter that the embodiment of the present invention provides；

The control signal schematic diagram corresponding with Fig. 4 embodiment that Fig. 6 provides for the present invention；

The signal waveforms of the Sawtooth corresponding with Fig. 4 embodiment that Fig. 7 provides for the present invention；

The signal waveforms of the Vout_comp corresponding with Fig. 4 embodiment that Fig. 8 provides for the present invention；

The signal waveforms that export clock CLK_OUT corresponding with Fig. 4 embodiment that Fig. 9 provides for the present invention；

A kind of schematic flow sheet of the clock jitter ameliorative way that Figure 10 provides for the embodiment of the present invention.

Detailed description of the invention

Below in conjunction with the accompanying drawing in the embodiment of the present invention, the technical scheme in the embodiment of the present invention is carried out clear, complete Describe, it is clear that described embodiment is only a part of embodiment of the present invention rather than whole embodiments wholely.Based on Embodiment in the present invention, it is every other that those of ordinary skill in the art are obtained under not making creative work premise Embodiment, broadly falls into the scope of protection of the invention.

Seeing Fig. 1, Fig. 1 and illustrate that clock jitter improves a kind of structural representation of circuit, circuit includes current mirror 100, electricity Pressure reference generating circuit 200, sawtooth waveforms produce and voltage comparator circuit 300, frequency dividing circuit 400 and control circuit 500.

Voltage reference produces the first input end of circuit 200 and is connected with current mirror 100, and voltage reference produces circuit 200 Second input is connected with the outfan of control circuit 500, voltage reference produce outfan and the sawtooth waveforms of circuit 200 produce and The first input end of voltage comparator circuit 300 connects.

Sawtooth waveforms produces and the second input of voltage comparator circuit 300 is connected with current mirror 100, and sawtooth waveforms produces and electricity 3rd input of pressure comparison circuit 300 is connected with the outfan of control circuit 500, and sawtooth waveforms produces and voltage comparator circuit The outfan of 300 is connected with frequency dividing circuit 400.

Wherein:

The input input clock signal of control circuit 400, the outfan output control signal of control circuit 400；

Voltage reference produces circuit 200 and receives the first electric current of current mirror 100 according to control signal, and voltage reference produces electricity Road 200 provides comparison reference level according to the first electric current for sawtooth waveforms generation and voltage comparator circuit 300；

Sawtooth waveforms produces and the 3rd input of voltage comparator circuit 300 receives control signal, according to control signal, sawtooth Ripple produces and the first input end of voltage comparator circuit 300 receives comparison reference level, and the second input receives the of current mirror Two electric currents, are produced sawtooth signal, according to comparison reference level and the ratio of sawtooth signal by the second electric current to electric capacity charging Relatively result output square wave；

Square wave is divided by frequency dividing circuit 400, the clock signal after output improvement.

The clock that the embodiment of the present invention provides improves circuit, the input input clock signal of control circuit 500, outfan Output control signal, control signal is used for controlling voltage reference and produces circuit, sawtooth waveforms generation and voltage comparator circuit, so that Voltage reference produces circuit 200 can receive the first electric current of current mirror 100, is that sawtooth waveforms produces and voltage according to the first electric current Comparison circuit 300 provides comparison reference level, and so that sawtooth waveforms produces and the first input end of voltage comparator circuit 300 It is able to receive that comparison reference level, the second input are able to receive that the second electric current of current mirror, and generates saw according to the second electric current Tooth ripple signal, exports square wave according to the comparative result of comparison reference level and sawtooth signal.From the foregoing, clock signal Produce circuit 200 through voltage reference, sawtooth waveforms produces and after voltage comparator circuit 300, exports square wave, and frequency dividing circuit 400 will The square wave frequency dividing received, the clock signal after output improvement, the clock that therefore the bright embodiment of this law provides improves circuit, successively Through control circuit 500, voltage reference produces circuit 200, sawtooth waveforms produces and voltage comparator circuit 300, frequency dividing circuit 400 After, improve the shake of clock.

Further, the clock jitter that the embodiment of the present invention provides improves circuit and includes that current mirror 100, voltage reference produce Circuit 200, sawtooth waveforms produce and voltage comparator circuit 300, frequency dividing circuit 400 and control circuit 500, compared to existing PLL The phase-locked loop of circuit, has circuit module few, the simple advantage of circuit, and owing to circuit module is less, circuit is simple, unit used Device is less, so the area of circuit is less, power consumption is less.

Seeing Fig. 2, in other embodiments of the present invention, above-mentioned clock jitter improves circuit and also includes reference current source 600.

Wherein, current mirror 100, voltage reference produce circuit 200, sawtooth waveforms produce and voltage comparator circuit 300 respectively with Reference current source 600 connects, and current mirror 100 produces circuit 200 to voltage reference, sawtooth waveforms produces and voltage comparator circuit 300 Export the electric current proportional to reference current source 600.If it should be noted that current mismatch, then charging voltage can be caused Deviation, ultimately results in the deviation of output clock frequency and theoretical value, therefore, current mirror 100 to voltage reference produce circuit 200, The electric current that sawtooth waveforms produces and voltage comparator circuit 300 output is proportional to reference current source 600.

Seeing Fig. 3, in other embodiments of the invention, above-mentioned voltage reference produces circuit 200 can include first Charging paths the 201, second charging paths 202.

First charging paths 201 produces for sawtooth waveforms and voltage comparator circuit 300 provides comparison reference level, due to circuit Can there is leakage current, comparison reference level, after the charging of experience a period of time, will slowly decline, finally affect the normal of circuit Work, in order to solve this problem, arranges the second charging paths 202 in voltage reference produces circuit 200, and wherein, first fills Electricity branch road 201 is connected in parallel with the second charging paths 202, the input of the first charging paths 201 and the second charging paths 202 Input is connected with current mirror 100 respectively, and the first charging paths 201 is periodically charged by the second charging paths 202.

Further, between the second charging paths 202 and current mirror 100, switch can be set, by the Guan Bi of switch, make Obtaining current mirror 100 and second charging paths 202 is carried out periodic discharge and recharge, the Guan Bi of this switch can be exported by control circuit Control signal control.

It addition, switch can also be arranged between the first charging paths 201 and the second charging paths 202, in the second charging After each charging complete in road 202, turn on the switch between the first charging paths 201 and the second charging paths 202 so that second fills First charging paths 201 is periodically charged by electricity branch road 202, thus offsets and leak electricity on the impact comparing datum, And then make comparison reference level have a stable output valve.Wherein, the first charging paths 201 and the second charging paths 202 Between the control signal that can be exported by control circuit of the Guan Bi of switch control.

Also need to supplement, between the first charging paths 201 and current mirror 100, switch is equally set, by opening The Guan Bi closed so that current mirror 100 carries out periodic discharge and recharge to the first charging paths 201, the Guan Bi of this switch can be by The control signal of control circuit output controls.

Seeing Fig. 4, the embodiment of the present invention provides clock jitter to improve circuit one and implements circuit, including current mirror 100, voltage reference produces circuit 200, sawtooth waveforms produces and voltage comparator circuit 300, frequency dividing circuit 400 and reference current Source 600, is shown without control circuit in Fig. 4.

Voltage reference produces circuit 200 and includes the first charging paths and the second charging paths, and the first charging paths includes First electric capacity C1 and first switch S1, the first electric capacity C1 and first switch S1 is connected in series by the first common port.

Second charging paths includes that the second electric capacity C2 and second switch S2, the second electric capacity C2 and second switch S2 pass through Second common port is connected in series.

Voltage reference produces circuit 200 and also includes the 3rd switch S3.

First end and first common port of the 3rd switch S3 connect, and second end of the 3rd switch S3 and the second common port are even Connect；

The outfan that first common port produces circuit 200 as voltage reference produces and voltage comparator circuit with sawtooth waveforms 300 connect.

Further, voltage reference generation circuit 200 can also include the 4th switch S4 and the 5th switch S5.

Wherein, the 4th switch S4 is for the second electric capacity C2 voltage amplitude before charging；

5th switch S5 and the first electric capacity C1 is in parallel, and the 5th switch S5 is multiple for the first electric capacity C1 voltage before charging Position.

Referring further to Fig. 4, sawtooth waveforms produces and voltage comparator circuit 300 includes comparator the 301, the 3rd electric capacity C3, the 6th opens Close S6 and the 7th switch S7.

First end of the 3rd electric capacity C3 is connected with current mirror 100, connecing of the second termination reference current source of the 3rd electric capacity C3 Ground end；

The inverting input of comparator 301 is connected with the first above-mentioned common port, the positive input of comparator 301 and First end of three electric capacity C3 connects, and Automatic level control the 7th switch S7 of the outfan output of comparator 301 cut-offs；

6th switch S6, the 7th switch S7 are in parallel with the 3rd electric capacity C3 respectively,

Wherein:

6th switch S6 is for the 3rd electric capacity C3 voltage amplitude before charging, and the 7th switch S7 is for the 3rd electric capacity C3 just Often during work, periodic voltage resets.

Further, what the present invention illustrated circuit operation principle of the present invention as a example by Fig. 4, Fig. 5, Fig. 6 implements process, Wherein, Fig. 4 be core circuit, Fig. 5 be control circuit, Fig. 6 be the control signal sequential that control circuit produces.

Control circuit receives clock signal clk _ IN, exports 6 control signals, and control signal is respectively S1～S6, is used for The break-make of respective identification switch S1-S6 in control core circuit, that is, control signal controls the break-make of switch S1, control signal S2 controls the break-make of switch S2, and successively, control signal S6 controls the break-make of switch S6.

For convenience of analytic explanation, in figure, all switches close when control signal is high level, are low electricity in control signal Disconnect at ordinary times.

By reset signal Reset, circuit working state can be divided into reset state and normal operating conditions, reset state Time, reset signal Reset is high level, and during normal operating conditions, reset signal Reset becomes low level from high level.

Wherein, reset signal Reset input frequency dividing circuit 300.

When duty is reset state, reset signal Reset is high level, and now control signal S1, S2 are low electricity Flat, S3, S4, S5, S6 are high level, therefore switch S1, S2 and disconnect, switch S3, S4, S5, and S6 closes, now electric capacity C1, C2, C3 Both end voltage is by switch discharge to zero, i.e. voltage signal Vref, Sawtooth in Fig. 5 is zero.

Meanwhile, during reset state, frequency dividing circuit 300 is in reset state, is output as a fixing level value.

When duty is normal operating conditions, reset signal Reset becomes low level, control signal S1 from high level By first rising edge after reset signal is low level or trailing edge, begin to change into high level, and keep high level Time be th=N*T, wherein, T is the cycle of input clock CLK_IN, and N is the cycle of clock and the CLK_IN of S2, S3, S4 The half of ratio, N is the integer more than 0.After elapsed time th, S1 will become low level and keep constant, control signal S2, S3, S4 are by cyclically-varying, and period of change is 2*N*T, and the phase relation between each control signal is as shown in Figure 6.

Being the charging of th by current source I1 to the electric capacity C1 time of carrying out, reference voltage generating circuit obtains reference voltage Vref=I1*th/C1, wherein, I1 is the input current value of current source, and C1 is the capacitance of electric capacity C1.

C1 is through switch S1 charging, charging interval a length of th=N*T.Ideally, reference voltage V ref can keep Constant, but, after S1 disconnects, supplementing electric leakage electric charge without other current sources, the voltage on C1 can slowly decline, work as voltage When dropping to certain threshold value, the normal work of circuit can be affected, for solving this problem, introduce in circuit by electric capacity C2, Switch S2, the charging circuit of switch these devices of S3 composition, charging circuit, by C2 is carried out periodic discharge and recharge, obtains The charging voltage consistent with reference voltage V ref.After each C1 charging complete, switch S3 conducting, in ON time corresponding diagram 6 The t2 time so that C1 is charged by C2, offsets the electric leakage impact on Vref, thus keeps Vref to be basically unchanged.

Electric current I1, I2, the value of electric capacity C1, C2 have bigger motility, but they need to meet following relation, i.e. I1/ C1=I2/C2.Assume I1=I2, C1=C2, so after sufficiently long stabilization time, the magnitude of voltage of reference voltage V ref is Vref=I1*th/C1=I1*N*T/C1.

Further, circuit can also include switching S4, and switch S4 is for electric capacity C2 voltage amplitude before charging.

It should be noted that the selection of these 5 time parameters of t1～t5 the most strictly limits in Fig. 6, can be according to actual electricity Road is adjusted.

Sawtooth waveforms produces and voltage comparator circuit 300, is made up of switch S6, switch S7, electric capacity C3 and comparator 301. When the duty of sawtooth waveforms generation and voltage comparator circuit 300 is normal operating conditions, electric capacity C3 is filled by electric current I3 Electricity, when charging voltage is more than Vref, comparator 301 will be high level from low level upset, the outfan output of comparator 301 High level, this high level makes to switch S7 Guan Bi, the voltage of electric capacity C3 is discharged to zero again, and comparator 301 will be from high level Being flipped back to low level, switch S7 is again off, and current source I3 starts new charging once to electric capacity C3, and such cycle is carried out, Sawtooth node will obtain a sawtooth waveforms as shown in Figure 7, and the maximum of sawtooth waveforms is Vref, simultaneously at Vout_comp Node will obtain the square-wave signal shown in Fig. 8, and in side circuit, the dutycycle of square-wave signal is the least, i.e. tp ＜ ＜ tl, institute Cycle T saw ≈ tl=Vref*C3/I3 with sawtooth waveforms Sawtooth and square wave Vout_comp.

It should be noted that when side circuit realizes, the value of C3, I3 can select flexibly.

Further, switch S6 closed in the circuit starting stage, it is therefore an objective to put only by the electric charge on electric capacity C3.S3 disconnects Moment can not complete initial charge, to have ensured the reference voltage Vref of comparator negative input end early than electric capacity C1 by switch S1 Through stable.It addition, switch S5 is in the starting stage Guan Bi that circuit works, it is therefore an objective to the electric charge on electric capacity C1 is put only.

By frequency dividing circuit 400, can produce, from sawtooth waveforms, the Vout_ that the outfan with voltage comparator circuit 300 exports Comp recovers clock signal clk _ OUT, and CLK_OUT is shown in Figure 9, and meanwhile, frequency dividing circuit 400 ensures accounting for of output clock Empty ratio is 50%.

The divide ratio assuming frequency dividing circuit 400 is K, then the clock signal period after frequency dividing is T_out=T_saw*K。

Further, by circuit of the present invention, suitable circuit parameter is set, can recover at output terminal of clock and input Clock signal clk _ OUT that clock CLK_IN frequency is consistent.

Concrete process is:

T=T_out

$\⇒T=T_{saw}*K=\frac{Vref*C3}{I3}*K;$

$Vref=\frac{I1*N*T}{C1};$

$\⇒T=\frac{\frac{I1*N*T}{C1}*C3*K}{I3};$

$\⇒\frac{I1}{I3}*\frac{C3}{C1}*N*K=1;$

From being analyzed above, as long as circuit parameter meets formulaEstablishment condition, this circuit is with regard to energy The output clock CLK_OUT of same frequency is recovered by input clock CLK_IN.

Further, in most cases, clock jitter meets Gauss distribution, thus, it is supposed that clock jitter meets The characteristic of Gauss distribution.If the standard deviation of input clock shake is δ (T), input clock the voltage reference Vref indirectly controlled To produce the voltage noise of Gaussian distributed, C1 can be charged with each C2 and changes by noise average power, but passes through After sufficient number of charging, the average noise power of Vref will tend to a stationary value, it may be assumed that

$\stackrel{\‾}{V_{vref}^2}=(1+\frac{1}{4}+\frac{1}{4^2}+\frac{1}{4^3}+......)*\stackrel{\‾}{V_n^2}=\frac{4}{3}*\stackrel{\‾}{V_n^2};$

$\stackrel{\‾}{V_n^2}=N*\mathrm{\σ}{\left(T\right)}^2*{\left(\frac{I1}{C1}\right)}^2;$

$\⇒\stackrel{\‾}{V_{vref}^2}=\frac{4}{3}*N*\mathrm{\σ}{\left(T\right)}^2*{\left(\frac{I1}{C1}\right)}^2;$

In formula,Noise average power when stablizing for Vref,For noise electricity during Vref charging complete for the first time Pressure.This noise voltage will be produced by sawtooth waveforms and voltage comparator circuit is re-converted into the shake of Vout_comp, is then passed through The shake of output clock it is converted into after frequency dividing circuit 400.Produce and voltage comparator circuit through sawtooth waveforms analyzing noise voltage When being converted into the shake of Vout_comp, thus can analyze Vout_comp's by noise voltage equivalence to Sawtooth node Shake δ (T1), is specifically derived as:

$\stackrel{\‾}{V_{vref}^2}=\frac{4}{3}*N*\mathrm{\σ}{\left(T\right)}^2*{\left(\frac{I1}{C1}\right)}^2=\mathrm{\σ}{\left(T1\right)}^2*{\left(\frac{I3}{C3}\right)}^2;$

$\⇒\mathrm{\σ}{\left(T1\right)}^2=\frac{4}{3}*N*\mathrm{\σ}{\left(T\right)}^2*{\left(\frac{I1}{C1}\right)}^2*{\left(\frac{C3}{I3}\right)}^2;$

The shake δ (T1) of Vout_comp, after frequency dividing circuit, is dithered as δ (T2), tool what CLK_OUT port obtained Body is:

σ(T2)²=K σ (T1)²

$\⇒\mathrm{\σ}{\left(T2\right)}^2=K*\frac{4}{3}*N*\mathrm{\σ}{\left(T\right)}^2*{\left(\frac{I1}{C1}\right)}^2*{\left(\frac{C3}{I3}\right)}^2;$

$\frac{I1}{I3}*\frac{C3}{C1}*N*K=1;$

$\⇒\mathrm{\σ}{\left(T2\right)}^2=K*\frac{4}{3}*N*\mathrm{\σ}{\left(T\right)}^2*\frac{1}{{(N*K)}^2}=\frac{4}{3}*\frac{1}{N*K}*\mathrm{\σ}{\left(T\right)}^2;$

$\⇒\mathrm{\σ}\left(T2\right)=\sqrt{\frac{4}{3}*\frac{1}{N*K}}*\mathrm{\σ}\left(T\right);$

By formulaUnderstanding, the shake of output clock reduces with the increase of N, K product, when When product is bigger, the shake δ (T2) of output clock will be significantly less than the shake δ (T) of input clock, and therefore, the value increasing N, K can To effectively reduce the shake of input clock.

See Figure 10, Figure 10 and show a kind of schematic flow sheet of clock jitter ameliorative way, be applied to clock jitter and change Kind circuit, circuit includes that current mirror, voltage reference produce circuit, sawtooth waveforms produces and voltage comparator circuit, frequency dividing circuit and Control circuit, method includes:

Step 110: control circuit receives clock signal, exports control signal.

Step 120: voltage reference produces circuit and receives the first electric current of current mirror according to control signal, according to the first electric current Produce for sawtooth waveforms and voltage comparator circuit provides comparison reference level.

Step 130: sawtooth waveforms produces and the 3rd input of voltage comparator circuit receives control signal, according to controlling letter Number, sawtooth waveforms produces and the first input end of voltage comparator circuit receives comparison reference level, and the second input receives current mirror The second electric current, by the second electric current to electric capacity charging produce sawtooth signal, according to comparison reference level and sawtooth signal Comparative result output square wave.

Step 140: square wave is divided by frequency dividing circuit, the clock signal after output improvement.

The clock ameliorative way that the embodiment of the present invention provides, the input input clock signal of control circuit, outfan is defeated Going out control signal, control signal is used for controlling voltage reference and produces circuit, sawtooth waveforms generation and voltage comparator circuit, so that electric Pressure reference generating circuit can receive the first electric current of current mirror, is that sawtooth waveforms produces and voltage comparator circuit according to the first electric current Comparison reference level is provided, and so that the first input end of sawtooth waveforms generation and voltage comparator circuit is able to receive that and compares ginseng Examining level, the second input is able to receive that the second electric current of current mirror, and generates sawtooth signal according to the second electric current, according to than The comparative result output square wave of relatively datum and sawtooth signal.

From the foregoing, clock signal produces circuit through voltage reference, sawtooth waveforms produces and after voltage comparator circuit, defeated Going out square wave, the square wave frequency dividing that frequency dividing circuit will receive, the clock signal after output improvement, therefore the bright embodiment of this law provides Clock improves circuit, sequentially passes through control circuit, voltage reference generation circuit, sawtooth waveforms generation and voltage comparator circuit, frequency dividing After circuit, improve the shake of clock.

Further, the clock jitter ameliorative way that the embodiment of the present invention provides is applied to clock jitter and improves circuit, electricity Road includes that again current mirror, voltage reference produce circuit, sawtooth waveforms produces and voltage comparator circuit, frequency dividing circuit and control electricity Road, therefore, the clock jitter that clock jitter ameliorative way is applied to improves the circuit phase-locked loop compared to existing PLL circuit, There is circuit module few, the simple advantage of circuit, owing to circuit module is less, circuit is simple, and components and parts used are less, thus electric The area on road is less, power consumption is less.

It will be appreciated by those skilled in the art that accompanying drawing is the schematic diagram of a preferred embodiment, the module in accompanying drawing or stream Journey is not necessarily implemented necessary to the present invention.

It will be appreciated by those skilled in the art that the module in the device in embodiment can describe according to embodiment to be distributed in In the device of embodiment, it is also possible to carry out respective change and be disposed other than in one or more devices of the present embodiment.Above-mentioned reality The module executing example can merge into a module, it is also possible to is further split into multiple submodule.

Described above to the disclosed embodiments, makes professional and technical personnel in the field be capable of or uses the present invention. Multiple amendment to these embodiments will be apparent from for those skilled in the art, as defined herein General Principle can realize without departing from the spirit or scope of the present invention in other embodiments.Therefore, the present invention It is not intended to be limited to the embodiments shown herein, and is to fit to and principles disclosed herein and features of novelty phase one The widest scope caused.

Claims (7)

1. a clock jitter improves circuit, it is characterised in that include that current mirror, voltage reference produce circuit, sawtooth waveforms produces With voltage comparator circuit, frequency dividing circuit and control circuit；

Described voltage reference produces the first input end of circuit and is connected with described current mirror, the of described voltage reference generation circuit Two inputs are connected with the outfan of described control circuit, and described voltage reference produces the outfan of circuit and produces with described sawtooth waveforms Raw and voltage comparator circuit first input end connects；

Described sawtooth waveforms produces and the second input of voltage comparator circuit is connected with described current mirror, the generation of described sawtooth waveforms with 3rd input of voltage comparator circuit is connected with the outfan of described control circuit, and described sawtooth waveforms produces and voltage ratio is more electric The outfan on road is connected with frequency dividing circuit；

Wherein:

The input input clock signal of described control circuit, outfan output control signal；

Described voltage reference produces circuit and receives the first electric current of described current mirror according to described control signal, according to described first Electric current produces for described sawtooth waveforms and voltage comparator circuit provides comparison reference level；

Described sawtooth waveforms produces and the 3rd input of voltage comparator circuit receives described control signal, controls letter according to described Number, described sawtooth waveforms produces and the first input end of voltage comparator circuit receives described comparison reference level, and described sawtooth waveforms produces Raw and voltage comparator circuit the second input receives the second electric current of described current mirror, described second electric current charge electric capacity Produce sawtooth signal, export square wave according to the comparative result of described comparison reference level and described sawtooth signal；

Described square wave is divided by described frequency dividing circuit, the clock signal after output improvement.

Circuit the most according to claim 1, it is characterised in that described circuit also includes reference current source；

Described current mirror, described voltage reference produce circuit, described sawtooth waveforms produce and voltage comparator circuit respectively with described base Quasi-current source connects；

Described current mirror produces circuit to described voltage reference, described sawtooth waveforms produces and voltage comparator circuit exports and described base The electric current that quasi-current source is proportional.

3. according to the circuit described in claim 1-2 any one, it is characterised in that described voltage reference produces circuit and includes the One charging paths, the second charging paths；

Wherein,

Described first charging paths is connected in parallel with described second charging paths；

The input of described first charging paths and the input of described second charging paths are connected with described current mirror respectively；

Described first charging paths is periodically charged by described second charging paths.

Circuit the most according to claim 3, it is characterised in that described first charging paths includes the first electric capacity and first Switch, described first electric capacity and described first switch are connected in series by the first common port；

Described second charging paths includes that the second electric capacity and second switch, described second electric capacity and described second switch pass through Second common port is connected in series；

Described voltage reference produces circuit and also includes the 3rd switch；

First end of described 3rd switch is connected with described first common port, and the second end of described 3rd switch is public with described second Hold connection altogether；

Described first common port as described voltage reference produce outfan and the described sawtooth waveforms of circuit produce and voltage ratio relatively Circuit connects.

Circuit the most according to claim 4, it is characterised in that described voltage reference produce circuit also include the 4th switch with And the 5th switch；

Described 4th switch, for described second electric capacity voltage amplitude before charging；

Described 5th switch, in parallel with described first electric capacity, described 5th switch is for described first electric capacity electricity before charging Pressure resets.

Circuit the most according to claim 5, it is characterised in that described sawtooth waveforms produces and voltage comparator circuit includes comparing Device, the 3rd electric capacity, the 6th switch and the 7th switch；

First end of described 3rd electric capacity is connected with described current mirror, connecing of the second termination reference current source of described 3rd electric capacity Ground end；

The inverting input of described comparator is connected with described first common port, the positive input of described comparator and described the First end of three electric capacity connects, and described in the Automatic level control of the outfan output of described comparator, the 7th switch cut-offs；

Described 6th switch, described 7th switch are in parallel with described 3rd electric capacity respectively, wherein:

Described 6th switch is for described 3rd electric capacity voltage amplitude before charging, and described 7th switch is for described 3rd electricity When holding normal work, periodic voltage resets.

7. a clock jitter ameliorative way, it is characterised in that being applied to clock jitter and improve circuit, described circuit includes electric current Mirror, voltage reference produce circuit, sawtooth waveforms produces and voltage comparator circuit, frequency dividing circuit and control circuit, and method includes:

Described control circuit receives clock signal, exports control signal；

Described voltage reference produces circuit and receives the first electric current of described current mirror according to described control signal, according to described first Electric current produces for described sawtooth waveforms and voltage comparator circuit provides comparison reference level；

Described sawtooth waveforms produces and the 3rd input of voltage comparator circuit receives described control signal, controls letter according to described Number, described sawtooth waveforms produces and the first input end of voltage comparator circuit receives described comparison reference level, the second input termination Receive the second electric current of described current mirror, described second electric current electric capacity charging is produced sawtooth signal, compare ginseng according to described Examine the comparative result output square wave of level and described sawtooth signal；

Described square wave is divided by described frequency dividing circuit, the clock signal after output improvement.