CN116260454B - Jitter separation device and clock recovery instrument - Google Patents
Jitter separation device and clock recovery instrument Download PDFInfo
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- CN116260454B CN116260454B CN202310525757.1A CN202310525757A CN116260454B CN 116260454 B CN116260454 B CN 116260454B CN 202310525757 A CN202310525757 A CN 202310525757A CN 116260454 B CN116260454 B CN 116260454B
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
- H03K5/125—Discriminating pulses
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
- H03L7/093—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal using special filtering or amplification characteristics in the loop
Abstract
The invention provides a jitter separation device and a clock recovery instrument, and relates to the technical field of electronics. The jitter separation apparatus includes: the device comprises a phase discriminator, a jitter separation module, a voltage-controlled oscillator and a data processing module; the input end of the phase discriminator is used for receiving an input signal, and the output end of the phase discriminator is connected with the input end of the jitter separation module; the jitter separation module is used for extracting a clock signal corresponding to an output signal of the phase discriminator, and performing jitter separation on the clock signal to obtain a first jitter component and a second jitter component corresponding to an input signal; the data processing module is used for carrying out jitter analysis on the first jitter component and the second jitter component, and determining frequency characteristics corresponding to the first jitter component and frequency characteristics corresponding to the second jitter component. The jitter separation device and the clock recovery instrument provided by the invention can be used for performing jitter separation on the clock signal extracted from the output signal of the phase discriminator, and can be used for effectively performing jitter analysis on the obtained jitter component, so that the accuracy of the jitter analysis is improved.
Description
Technical Field
The present invention relates to the field of electronic technologies, and in particular, to a jitter separation device and a clock recovery apparatus.
Background
The traditional jitter separation needs to rely on the jitter analysis function of an oscilloscope, the analysis precision is lower, and when the input high-speed signal is subjected to jitter separation through the oscilloscope, a special measuring instrument and corresponding options are needed, the cost is high, the use is inconvenient, meanwhile, the high-speed oscilloscope often needs the support of a super-speed analog-digital converter (Analog to Digital Converter, ADC), the effective quantization bit number is low, small jitter cannot be resolved, and the amplitude resolution of large jitter is insufficient.
Disclosure of Invention
The invention provides a jitter separation device and a clock recovery instrument, which are used for solving the technical problem of lower jitter separation accuracy in the prior art.
The present invention provides a jitter separation apparatus, comprising:
the device comprises a phase discriminator, a jitter separation module, a voltage-controlled oscillator and a data processing module;
the input end of the phase discriminator is used for receiving an input signal, and the output end of the phase discriminator is connected with the input end of the jitter separation module;
the first output end of the jitter separation module is connected with the data processing module, and the second output end of the jitter separation module is connected with the input end of the voltage-controlled oscillator;
the jitter separation module is used for extracting a clock signal corresponding to an output signal of the phase discriminator, and performing jitter separation on the clock signal to obtain a first jitter component and a second jitter component corresponding to the clock signal;
the data processing module is used for carrying out jitter analysis on the first jitter component and the second jitter component, and determining frequency characteristics corresponding to the first jitter component and frequency characteristics corresponding to the second jitter component.
In some embodiments, the jitter separation module includes a first sub-module and a second sub-module; the first submodule is used for acquiring the first jitter component based on a fixed loop bandwidth; the second submodule is used for acquiring the second jitter component based on variable loop bandwidth;
the input end of the first sub-module is connected with the output end of the phase discriminator, the first output end of the first sub-module is connected with the data processing module, and the second output end of the first sub-module is connected with the input end of the second sub-module;
the first output end of the second sub-module is connected with the data processing module, and the second output end of the second sub-module is connected with the input end of the voltage-controlled oscillator.
In some embodiments, the first sub-module includes a first loop filter and a first emitter follower;
the input end of the first loop filter is connected with the output end of the phase discriminator, the first output end of the first loop filter is connected with the input end of the first radial follower, the output end of the first radial follower is connected with the data processing module, and the second output end of the first loop filter is connected with the input end of the second sub-module;
wherein the first loop filter has the fixed loop bandwidth.
In some embodiments, the second sub-module includes a second loop filter and a second emitter follower;
the input end of the second loop filter is connected with the second output end of the first submodule, the first output end of the second loop filter is connected with the input end of the second jet follower, the output end of the second jet follower is connected with the data processing module, and the second output end of the second loop filter is connected with the voltage-controlled oscillator;
wherein the second loop filter has the variable loop bandwidth.
In some embodiments, the first loop filter comprises: the first integrating filter, the first capacitor and the constant value resistor;
the input end of the first integrating filter is connected with the output end of the phase discriminator and the first end of the fixed value resistor respectively, the second end of the fixed value resistor is connected with the first end of the first capacitor, the second end of the first capacitor is connected with the output end of the first integrating filter and the input end of the first jet follower respectively, and the output end of the first integrating filter is connected with the input end of the second sub-module.
In some embodiments, the second loop filter comprises: the second integrating filter, the second capacitor and the adjustable resistor;
the input end of the second integrating filter is respectively connected with the second output end of the first submodule and the first end of the adjustable resistor, the second end of the adjustable resistor is connected with the first end of the second capacitor, the second end of the second capacitor is respectively connected with the output end of the second integrating filter and the input end of the second jet follower, and the output end of the second integrating filter is connected with the input end of the voltage-controlled oscillator.
In some embodiments, the data processing module comprises a first analog-to-digital converter, a second analog-to-digital converter, an FPGA, and an MCU;
the first output end of the first sub-module is connected with the input end of the first analog-to-digital converter, the output end of the first analog-to-digital converter is connected with the FPGA, and the output end of the FPGA is connected with the input end of the MCU;
the first output end of the second sub-module is connected with the input end of the second analog-to-digital converter, the output end of the second analog-to-digital converter is connected with the FPGA, and the output end of the FPGA is connected with the input end of the MCU.
The invention also provides a clock recovery instrument, comprising: the jitter separation apparatus as described above.
According to the jitter separation device and the clock recovery instrument, the clock signal corresponding to the output signal of the phase discriminator is extracted, the clock signal is subjected to jitter separation, the first jitter component and the second jitter component corresponding to the clock signal are obtained, the collected first jitter component and second jitter component can be subjected to effective jitter analysis, and the accuracy of jitter analysis is improved.
Drawings
In order to more clearly illustrate the invention or the technical solutions of the prior art, the following description will briefly explain the drawings used in the embodiments or the description of the prior art, and it is obvious that the drawings in the following description are some embodiments of the invention, and other drawings can be obtained according to the drawings without inventive effort for a person skilled in the art.
FIG. 1 is a schematic diagram of a jitter separation apparatus according to the present invention;
FIG. 2 is a schematic diagram of a jitter separation apparatus according to a second embodiment of the present invention;
fig. 3 is a schematic structural diagram of a clock recovery apparatus according to the present invention.
Detailed Description
For the purpose of making the objects, technical solutions and advantages of the present invention more apparent, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings, and it is apparent that the described embodiments are some embodiments of the present invention, not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
In the description of the present invention, it should be noted that, unless explicitly specified and limited otherwise, the terms "mounted," "connected," and "connected" are to be construed broadly, and may be either fixedly connected, detachably connected, or integrally connected, for example; can be mechanically or electrically connected; can be directly connected or indirectly connected through an intermediate medium, and can be communication between two elements. The specific meaning of the above terms in the present invention will be understood in specific cases by those of ordinary skill in the art.
The jitter separation apparatus and clock recovery apparatus of the present invention are described below with reference to fig. 1 to 3.
Fig. 1 is a schematic structural diagram of a jitter separation apparatus according to the present invention. Referring to fig. 1, the jitter separation apparatus provided by the present invention includes: a phase detector 110, a jitter separation module 120, a voltage controlled oscillator 130, and a data processing module 140.
The input end of the phase detector 110 is used for receiving an input signal, and the output end of the phase detector 110 is connected with the input end of the jitter separation module 120;
a first output end of the jitter separation module 120 is connected with the data processing module 140, and a second output end of the jitter separation module 120 is connected with an input end of the voltage-controlled oscillator 130;
the jitter separation module 120 is configured to extract a clock signal corresponding to the output signal of the phase detector 110, and perform jitter separation on the clock signal to obtain a first jitter component and a second jitter component corresponding to the clock signal;
the data processing module 140 is configured to perform jitter analysis on the first jitter component and the second jitter component, and determine a frequency characteristic corresponding to the first jitter component and a frequency characteristic corresponding to the second jitter component.
In actual implementation, the input signal received at the input of the phase detector 110 includes a pseudo-random data signal and a signal output by the voltage controlled oscillator 130 (Voltage Controlled Oscillator, VCO). The phase detector 110 is configured to perform phase comparison on the two signals, determine a phase difference value of the two signals, and convert the phase difference value into a corresponding voltage control signal. The voltage control signal is the output signal of the phase detector 110.
The voltage-controlled oscillator 130 is an oscillating circuit with output frequency corresponding to the input control voltage, i.e. the output frequency of the voltage-controlled oscillator 130 is controlled by the input voltage.
After the output terminal of the phase detector 110 outputs the voltage control signal, the voltage control signal is input to the jitter separation module 120.
The output of the jitter separation module 120 is split into two paths, one path is input to the data processing module 140 for jitter analysis, and the other path is input to the voltage controlled oscillator 130 for locking with the input high-speed data.
The jitter separation module 120 may perform jitter separation on a periodic clock signal corresponding to the voltage control signal based on different loop bandwidths, so as to obtain a first jitter component and a second jitter component corresponding to the clock signal.
The data processing module 140 may perform jitter analysis on the first jitter component and the second jitter component, calculate a frequency characteristic corresponding to the first jitter component and a frequency characteristic corresponding to the second jitter component, and calculate the relative power.
In actual implementation, the data processing module 140 may include an analog-to-digital converter (Analog to Digital Converter, ADC), a field programmable gate array (Field Programmable Gate Array, FPGA), and a micro control unit (Microcontroller Unit, MCU).
The first output end of the jitter separation module 120 is connected with the input end of the analog-to-digital converter, the output end of the analog-to-digital converter is connected with the FPGA, and the output end of the FPGA is connected with the input end of the MCU.
The ADC is configured to collect an analog signal output by the jitter separation module 120, and convert the collected analog signal into a discrete digital signal, that is, the first jitter component and the second jitter component can be converted into corresponding digital signals.
After obtaining the digital signal corresponding to the first jitter component and the digital signal corresponding to the second jitter component, the FPGA respectively performs Fourier decomposition on the digital signals and converts the time domain signals into frequency domain signals.
The MCU analyzes the frequency domain signal corresponding to the first jitter component and the frequency domain signal corresponding to the second jitter component, so that the frequency characteristic and the relative power corresponding to the first jitter component and the frequency characteristic and the relative power corresponding to the second jitter component can be obtained.
According to the jitter separation device provided by the invention, the clock signal corresponding to the output signal of the phase discriminator is extracted, and the clock signal is subjected to jitter separation, so that the first jitter component and the second jitter component corresponding to the clock signal are obtained, and the collected first jitter component and second jitter component can be effectively subjected to jitter analysis, so that the accuracy of jitter analysis is improved.
Fig. 2 is a schematic diagram of a jitter separation device according to a second embodiment of the present invention. With reference to figure 2 of the drawings,
in some embodiments, the jitter separation module 120 includes a first sub-module 210 and a second sub-module 220.
The first sub-module 210 is configured to obtain a first jitter component based on a fixed loop bandwidth; the second sub-module 220 is configured to obtain a second jitter component based on the variable loop bandwidth;
an input end of the first sub-module 210 is connected with an output end of the phase detector 110, a first output end of the first sub-module 210 is connected with the data processing module 140, and a second output end of the first sub-module 210 is connected with an input end of the second sub-module 220;
the first output of the second sub-module 220 is connected to the data processing module 140, and the second output of the second sub-module 220 is connected to the input of the voltage controlled oscillator 130.
In actual implementation, the first sub-module 210 has a fixed loop bandwidth for analyzing the original jitter component of the input signal, i.e. the first jitter component.
The second sub-module 220 has a variable loop bandwidth. Since the loop bandwidths of the different devices under test (Device Under Test, DUT) are different, the second sub-module 220 sets the variable loop bandwidth to simulate the loop bandwidth of the device under test.
The second sub-module 220 is configured to analyze a true jitter component, i.e., a second jitter component, of the output signal of the phase detector after passing through the loop with a fixed bandwidth and the device under test. The loop bandwidth of the second sub-module 220 may be set according to the actual detection requirement, which is not specifically limited herein.
According to the jitter separation device provided by the invention, the jitter components separated by the first submodule and the second submodule are collected, so that the analog bandwidth requirement of the sampler and the signal processing capability requirement are greatly reduced compared with the case that the input high-speed signals are directly collected.
As shown in fig. 2, in some embodiments, the first sub-module 210 includes a first loop filter 2100 and a first stage follower 2101;
an input end of the first loop filter 2100 is connected with an output end of the phase detector 110, a first output end of the first loop filter 2100 is connected with an input end of the first emitter follower 2101, an output end of the first emitter follower 2101 is connected with the data processing module 140, and a second output end of the first loop filter 2100 is connected with an input end of the second sub-module 220;
wherein the first loop filter 2100 has a fixed loop bandwidth.
In actual implementation, the first loop filter 2100 is a fixed loop filter, i.e., does not change the loop bandwidth. The first loop filter 2100 may filter out high frequency components including the frequency of the input signal in the output signal of the phase detector 110, so as to improve the anti-interference capability of the loop.
The first emitter follower 2101 is a common collector amplifying circuit, and is mainly used for amplifying alternating current so as to improve the load carrying capacity of the whole amplifying circuit. In practical circuits, it is typically used as an output stage or isolation stage. The characteristics are high input impedance and low output impedance, so that the current required from the signal source is small and the load capacity is strong.
In the present invention, the first emitter follower 2101 is used to connect the first loop filter 2100 and the analog-to-digital converter in the data processing module 140, so as to reduce the influence caused by direct connection between circuits and play a role of buffering.
As shown in fig. 2, in some embodiments, the second sub-module 220 includes a second loop filter 2200 and a second emitter follower 2201;
an input terminal of the second loop filter 2200 is connected to the second output terminal of the first sub-module 210, a first output terminal of the second loop filter 2200 is connected to an input terminal of the second emitter follower 2201, an output terminal of the second emitter follower 2201 is connected to the data processing module 140, and a second output terminal of the second loop filter 2200 is connected to the voltage controlled oscillator 130;
wherein the second loop filter 2200 has a variable loop bandwidth.
In actual implementation, the second loop filter 2200 is a variable loop filter, i.e., the loop bandwidth can be changed. The loop bandwidth of the second loop filter 2200 may be varied according to user detection requirements to obtain a desired loop bandwidth and gain to accommodate the needs of a variety of applications.
The second emitter follower 2201 is a common collector amplifying circuit, and is mainly used for amplifying alternating current so as to improve the load carrying capacity of the whole amplifying circuit. In practical circuits, it is typically used as an output stage or isolation stage. The characteristics are high input impedance and low output impedance, so that the current required from the signal source is small and the load capacity is strong.
In the present invention, the second emitter follower 2201 is used to connect the second loop filter 2200 and the analog-to-digital converter in the data processing module 140, so as to reduce the influence caused by direct connection between circuits, and play a role of buffering.
As shown in fig. 2, in some embodiments, the first loop filter 2100 includes: first integrating filter 2102, first capacitor C 1 And a constant resistor R 1 ；
The input end of the first integrating filter 2102 is respectively connected with the output end of the phase detector 110 and the fixed resistor R 1 Is connected with the first end of the fixed value resistor R 1 And the second end of the capacitor (C) 1 A first capacitor C connected to the first end of 1 Is connected to the output of the first integrating filter 2102 and the input of the first emitter follower 2101, respectively, and the output of the first integrating filter 2102 is connected to the input of the second sub-module 220.
In actual implementation, the first integrating filter 2102 has the characteristics of a low-pass filter, and the contemporaneous phase frequency characteristic also has the effect of lead correction. The first integrating filter 2102 may be an active proportional-integral filter.
First capacitor C 1 The capacitance value of (C) is a fixed value, the first capacitance C 1 Capacitance value of (d) and fixed-value resistor R 1 The resistance value of (c) may be set according to the actual detection requirement, and is not particularly limited herein.
The first loop filter 2100 does not change the loop bandwidth and can be used to analyze the original jitter component of the input signal.
As shown in fig. 2, in some embodiments, the second loop filter 2200 includes: second integrating filter 2202, second capacitor C 2 And an adjustable resistor R 2 ；
The input end of the second integrating filter 2202 is respectively connected with the second output end of the first submodule 210 and the adjustable resistor R 2 Is connected with the first end of the adjustable resistor R 2 And a second capacitor C 2 A second capacitor C connected to the first end of 2 Is connected to the output of the second integrating filter 2202 and the input of the second emitter follower 2201, respectively, and the output of the second integrating filter 2202 is connected to the input of the voltage controlled oscillator 130.
In practical implementation, the second integrating filter 2202 has the characteristics of a low-pass filter, and the contemporaneous phase-frequency characteristics also have the effect of lead correction. The second integrating filter 2202 may be an active proportional-integral filter.
In the second loop filter 2200, the adjustable resistor R is adjusted 2 The loop gain and thus the loop bandwidth of the second loop filter 2200 may be changed. Changing the loop bandwidth can simulate the loop bandwidth of the device under test, and further can analyze the real jitter component of the output signal of the phase detector 110 after passing through the fixed loop filter and the device under test.
Second capacitor C 2 The capacitance value of (C) is a fixed value, the second capacitance C 2 The capacitance value of (2) can be set according to the actual detection requirement, and is not specifically described hereinAnd (3) limiting.
As shown in fig. 2, in some embodiments, data processing module 140 includes a first analog-to-digital converter 1401, a second analog-to-digital converter 1402, a FPGA1403, and an MCU1404;
a first output end of the first sub-module 210 is connected with an input end of a first analog-to-digital converter 1401, an output end of the first analog-to-digital converter 1401 is connected with an FPGA1403, and an output end of the FPGA1403 is connected with an input end of an MCU1404;
the first output end of the second sub-module 220 is connected to the input end of the second analog-to-digital converter 1402, the output end of the second analog-to-digital converter 1402 is connected to the FPGA1403, and the output end of the FPGA1403 is connected to the input end of the MCU 1404.
The first analog-to-digital converter 1401 is configured to convert the acquired analog signal into a discrete digital signal, i.e. to acquire the first jitter component output by the first sub-module 210, and to convert the first jitter component into a corresponding digital signal.
The second analog-to-digital converter 1402 is configured to convert the collected analog signal into a discrete digital signal, i.e. to collect the first jitter component output by the second sub-module 220, and to convert the second jitter component into a corresponding digital signal.
After obtaining the digital signal corresponding to the first jitter component and the digital signal corresponding to the second jitter component, FPGA1403 performs fourier decomposition on the digital signals, and converts the time-domain signal into a frequency-domain signal. FPGA1403 sends frequency domain signals into MCU1404 through a high-level extensible interface protocol (Advanced eXtensible Interface, AXI) bus interface.
The MCU1404 analyzes the sum of the frequency domain signal corresponding to the first jitter component and the frequency domain signal corresponding to the second jitter component, so as to obtain a frequency characteristic and a relative power corresponding to the first jitter component, and a frequency characteristic and a relative power corresponding to the second jitter component.
The following describes the working principle of the shake separator according to the present invention in its entirety with reference to fig. 2:
the output signal of the phase discriminator 110 first passes through a fixed loop filter, the output of the stage is divided into two paths, one path of signal is buffered by a first emitter follower 2101 and then is sent to a first analog-digital converter 1401 to collect data, and after the data is obtained by the FPGA1403, the data is subjected to Fourier decomposition, and the time domain signal is converted into a frequency domain signal. The other path of signals are sent to a variable loop filter, the output of the variable loop filter is divided into two paths, one path of signals is buffered by a second emitter follower 2201 and then sent to a second analog-to-digital converter 1402 to collect data, and after obtaining the data, an FPGA1403 carries out Fourier decomposition and converts a time domain signal into a frequency domain signal; the other path is provided to the voltage controlled oscillator 130 for locking with the incoming high speed data.
According to the jitter separation device provided by the invention, jitter components are collected on the fixed loop filter and the variable loop filter, so that compared with the situation that input high-speed signals are directly collected, the requirements on analog bandwidth and signal processing capacity of a sampler are greatly reduced. Therefore, the acquisition can be performed by adopting a relatively low-speed analog-to-digital converter, and compared with an analog-to-digital converter sampled by tens of G, the effective bit number of the low-speed analog-to-digital converter can be expanded from 6 bits to 14 bits or higher, so that the jitter resolution is greatly enhanced.
Fig. 3 is a schematic structural diagram of a clock recovery apparatus according to the present invention. Referring to fig. 3, the clock recovery apparatus 300 includes the jitter separation means 310 in the above-described embodiment. For example, may include the jitter separation apparatus shown in fig. 1-2.
The jitter separation device shown in fig. 1 to 2 is described in the above embodiments, and will not be described herein.
In the related art, the existing clock recovery instrument cannot analyze the jitter of an input signal, and the jitter source cannot be effectively judged after the signal subjected to clock recovery is given to the sampling oscilloscope.
According to the clock recovery instrument provided by the invention, the periodic clock signal is extracted from the complex pseudo-random data signal, and the clock signal is subjected to jitter separation, so that the frequency and the relative power after jitter separation can be calculated more accurately, and the jitter analysis of the input signal is realized.
The apparatus embodiments described above are merely illustrative, wherein the elements illustrated as separate elements may or may not be physically separate, and the elements shown as elements may or may not be physical elements, may be located in one place, or may be distributed over a plurality of network elements. Some or all of the modules may be selected according to actual needs to achieve the purpose of the solution of this embodiment. Those of ordinary skill in the art will understand and implement the present invention without undue burden.
From the above description of the embodiments, it will be apparent to those skilled in the art that the embodiments may be implemented by means of software plus necessary general hardware platforms, or of course may be implemented by means of hardware. Based on this understanding, the foregoing technical solution may be embodied essentially or in a part contributing to the prior art in the form of a software product, which may be stored in a computer readable storage medium, such as ROM/RAM, a magnetic disk, an optical disk, etc., including several instructions for causing a computer device (which may be a personal computer, a server, or a network device, etc.) to execute the method described in the respective embodiments or some parts of the embodiments.
Finally, it should be noted that: the above embodiments are only for illustrating the technical solution of the present invention, and are not limiting; although the invention has been described in detail with reference to the foregoing embodiments, it will be understood by those of ordinary skill in the art that: the technical scheme described in the foregoing embodiments can be modified or some technical features thereof can be replaced by equivalents; such modifications and substitutions do not depart from the spirit and scope of the technical solutions of the embodiments of the present invention.
Claims (8)
1. A jitter separation apparatus, comprising:
the device comprises a phase discriminator, a jitter separation module, a voltage-controlled oscillator and a data processing module;
the input end of the phase discriminator is used for receiving an input signal, and the output end of the phase discriminator is connected with the input end of the jitter separation module;
the first output end of the jitter separation module is connected with the data processing module, and the second output end of the jitter separation module is connected with the input end of the voltage-controlled oscillator;
the jitter separation module is used for extracting clock signals corresponding to output signals of the phase discriminator based on different loop bandwidths, and performing jitter separation on the clock signals to obtain a first jitter component and a second jitter component corresponding to the clock signals;
the data processing module is used for carrying out jitter analysis on the first jitter component and the second jitter component, and determining frequency characteristics corresponding to the first jitter component and frequency characteristics corresponding to the second jitter component;
the jitter separation module comprises a first sub-module and a second sub-module; the first submodule is used for acquiring the first jitter component based on a fixed loop bandwidth; the second submodule is used for acquiring the second jitter component based on variable loop bandwidth;
the first submodule comprises a first loop filter and a first jet follower; wherein the first loop filter has the fixed loop bandwidth;
the second submodule comprises a second loop filter and a second jet follower; wherein the second loop filter has the variable loop bandwidth.
2. The jitter separation device of claim 1 wherein the input of the first sub-module is connected to the output of the phase detector, the first output of the first sub-module is connected to the data processing module, and the second output of the first sub-module is connected to the input of the second sub-module;
the first output end of the second sub-module is connected with the data processing module, and the second output end of the second sub-module is connected with the input end of the voltage-controlled oscillator.
3. A jitter separation device as claimed in claim 2 wherein the input of the first loop filter is connected to the output of the phase detector, the first output of the first loop filter is connected to the input of the first emitter follower, the output of the first emitter follower is connected to the data processing module, and the second output of the first loop filter is connected to the input of the second sub-module.
4. A jitter separation device as claimed in claim 2 wherein the input of the second loop filter is connected to the second output of the first sub-module, the first output of the second loop filter is connected to the input of the second emitter follower, the output of the second emitter follower is connected to the data processing module, and the second output of the second loop filter is connected to the voltage controlled oscillator.
5. A jitter separation apparatus as claimed in claim 3 wherein said first loop filter comprises: the first integrating filter, the first capacitor and the constant value resistor;
the input end of the first integrating filter is connected with the output end of the phase discriminator and the first end of the fixed value resistor respectively, the second end of the fixed value resistor is connected with the first end of the first capacitor, the second end of the first capacitor is connected with the output end of the first integrating filter and the input end of the first jet follower respectively, and the output end of the first integrating filter is connected with the input end of the second sub-module.
6. A jitter separation apparatus as claimed in claim 4 wherein said second loop filter comprises: the second integrating filter, the second capacitor and the adjustable resistor;
the input end of the second integrating filter is respectively connected with the second output end of the first submodule and the first end of the adjustable resistor, the second end of the adjustable resistor is connected with the first end of the second capacitor, the second end of the second capacitor is respectively connected with the output end of the second integrating filter and the input end of the second jet follower, and the output end of the second integrating filter is connected with the input end of the voltage-controlled oscillator.
7. The jitter separation apparatus of any one of claims 2-6 wherein the data processing module comprises a first analog-to-digital converter, a second analog-to-digital converter, an FPGA, and an MCU;
the first output end of the first sub-module is connected with the input end of the first analog-to-digital converter, the output end of the first analog-to-digital converter is connected with the FPGA, and the output end of the FPGA is connected with the input end of the MCU;
the first output end of the second sub-module is connected with the input end of the second analog-to-digital converter, the output end of the second analog-to-digital converter is connected with the FPGA, and the output end of the FPGA is connected with the input end of the MCU.
8. A clock recovery apparatus, comprising: a jitter separation apparatus as claimed in any one of claims 1 to 7.
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| CN202310525757.1A CN116260454B (en) | 2023-05-11 | 2023-05-11 | Jitter separation device and clock recovery instrument |
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| KR100960118B1 (en) * | 2007-12-17 | 2010-05-27 | 한국전자통신연구원 | Device for generating a clock signal with jitter and testing device therein |
| US8368435B2 (en) * | 2010-08-13 | 2013-02-05 | Mindspeed Technologies, Inc. | Method and apparatus for jitter reduction |
| CN103346792B (en) * | 2013-07-10 | 2016-06-01 | 电子科技大学 | Eliminate method, device and digital pre-distortion method that in analog to digital conversion, clock is shaken |
| CN107094016A (en) * | 2017-04-17 | 2017-08-25 | 中国电子科技集团公司第五十四研究所 | A kind of clock generation circuit for realizing low jitter |
| CN207869088U (en) * | 2018-05-15 | 2018-09-14 | 原时（荆门）电子科技有限公司 | A kind of low noise low jitter multi-frequency clock-generating device |
| CN111416618A (en) * | 2020-03-24 | 2020-07-14 | 中星联华科技（北京）有限公司 | Clock data recovery method and circuit |
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