CN103337475B - The synchronous etching technics of double structure contact hole - Google Patents
The synchronous etching technics of double structure contact hole Download PDFInfo
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- CN103337475B CN103337475B CN201310264711.5A CN201310264711A CN103337475B CN 103337475 B CN103337475 B CN 103337475B CN 201310264711 A CN201310264711 A CN 201310264711A CN 103337475 B CN103337475 B CN 103337475B
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Abstract
The present invention relates to the manufacturing process field of semiconductor MOS device, particularly relate to the synchronous etching technics of a kind of double structure contact hole, behind deposited silicon nitride barrier layer, remove immediately and be arranged in photosensitive area silicon nitride barrier, and then change the Structure of the deposits of double structure contact hole of CIS product, and in follow-up etching technics, increase the etching selection ratio of the relative barrier layer of interlayer dielectric layer (insulation dielectric layer) and silicon base, and then decrease separately for the etch step on bottom oxide silicon barrier layer, photosensitive area, reach while formation double structure contact hole, reduce the silicon oxide loss of logic area non-boundary contact hole on STI, while enhancing reliability of technology and stability, improve the yield of product.
Description
Technical field
The present invention relates to the manufacturing process field of semiconductor MOS device, particularly relate to the synchronous etching technics of a kind of double structure contact hole.
Background technology
At present, the etching of silica contact hole is the critical process in etching technics, one of its critical technological point is that aperture is little, etching depth dark (namely there is the characteristic of high-aspect-ratio), and etching depth is large with pattern (device) modification of surface morphology, especially CIS(CMOSImageSensor) product, its high aspect ratio features is more special.
CIS product has simultaneously photosensitive area (Pixel) and logic area (Logic), this just makes its contact hole manufacturing process and traditional logic or memory chip have a lot of difference; When preparing CIS product, the synchronous etching technics of general employing double structure contact hole, its concrete technological process is as follows:
Fig. 1 is the device architecture schematic diagram of traditional preparation CIS product, as shown in Figure 1, the substrate 1 of the device of preparation CIS product is provided with logic area (logic) 11 and photosensitive area (pixel) 12, and the substrate 1 being arranged in logic area 11 is also provided with shallow ditch non-intercommunicating cells (STI) 111, nickel silicide layer 112 and first grid structure 113, the substrate 1 being positioned at photosensitive area 12 is provided with barrier layer (SOR) 121 and second grid structure 122, etching stop layer (CESL) 13 covers nickel silicide layer 112, first grid structure 113, shallow ditch non-intercommunicating cells 111, the surface of silica barrier layer 121 and second grid structure 122, high-aspect-ratio dielectric layer (HARP) 14 covers the surface of etching stop layer 13, teos layer (TEOS) 15 covers the surface of high-aspect-ratio dielectric layer (HARP) 14, top layer silica (capoxide) 16 covers the surface of teos layer (TEOS) 15, bottom anti-reflection layer (BARC) 17 covers the surface of top layer silica (capoxide) 16, and form photoresistance pattern 18 in the surface of bottom anti-reflection layer (BARC) 17.
Because photosensitive area 12 is compared with logic area 11, there is following difference: the active area (AA) in (1) photosensitive area 12 and second grid structure (Gate) do not have metal silicide (i.e. nickel silicide layer 112), but cover one deck silica barrier layer 121, the silicon nitride etch barrier layer 13 that what silica barrier layer 121 covered above is then logic area 11 is identical, and identical at the Structure of the deposits on silicon nitride etch barrier layer more than 13, (2) in logic area 11 owing to being provided with fleet plough groove isolation structure 111, make its figure comparatively intensive, and area is less, the static random access memory district (SRAM) that figure integrated level particularly in logic area 11 is the highest, technology difficulty is reduced again for keeping higher pattern density, need to be set to non-boundary contact hole (borderlesscontact), namely bottom contact hole, major part will contact active area, remainder then can contact on fleet plough groove isolation structure 111, and because its pattern density is lower in photosensitive area 12, the general design not needing non-boundary contact hole.
Traditional synchronous etching technics of double structure contact hole generally comprises step: (1) each insulating layer deposition and photoresist are coated with and development; (2) BARC etching; (3) dielectric insulation layer silica main etching; (4) dielectric insulation layer silica over etching; (5) photoresist ashing is removed; (6) silicon nitride etch barrier etch; (7) photosensitive area bottom silica barrier layer etching.Fig. 2 is the structural representation of traditional synchronous etching technics design of double structure contact hole, according to technological design, on the basis of structure shown in Fig. 1, successively through above-mentioned processing step, can obtain structure as shown in Figure 2.Although above-mentioned processing step (1)-(6) can utilize same light shield, complete the contact hole etching of the different structure in two regions simultaneously, but, when carrying out step (7) photosensitive area bottom silica barrier layer etching technics, synchronously can etch logic area, and then bring defective workmanship.
Fig. 3 is the structural representation in traditional synchronous etching technics actual production of double structure contact hole; In the explained hereafter of reality, the thickness of photosensitive area bottom silica reaches 600A, and be the silica removing this 600A, this etch step must have total oxide etch removal amount of 900A, to ensure enough technique over etching windows, synchronously will etch the silicon oxide layer at the silica in the STI bottom the non-boundary contact hole of logic area and contact hole top like this; Namely as shown in Figure 3, to the synchronous etching that the silica in the STI bottom the non-boundary contact hole of logic area carries out, the deep hole 19 deeply reaching 700A ~ 800A can be formed on STI, and the degree of depth of this deep hole 19 substantially exceeds the well depth (about 500 ~ 600A) of active area (AA) ion implantation, the land (junction) making contact hole can cross ion implantation at the after-current of tungsten plug filling forms path with substrate silicon and causes leak electricity (leakage), makes component failure; Synchronous etching is carried out to the silicon oxide layer at the contact hole top of logic area and then can form the excessive ring-type scarf 191 in contact hole top, this excessive ring-type scarf 191 can when follow-up Ti/TiN barrier deposition, become larger due to the bombardment of Ar sputtering (sputter), easily cause to be improperly communicated with (contactbridge) between contact hole after tungsten plug deposition with grinding, thus make component failure.
Current, the defect brought in order to avoid the synchronous etching because the silica in the STI bottom the non-boundary contact hole of logic area carries out, general way is made an amendment from figure typesetting (layout), avoid using non-boundary contact hole, and make the size of logic area contact hole (CD) much less than the size of active area (AA), to ensure enough pattern alignment (overlay) process windows, as passed through active area pattern visual evoked potentials, to avoid using non-boundary contact hole, but device integration can be made to reduce; Or contact hole size is reduced, to avoid using non-boundary contact hole, so then can greatly increase contact hole technology difficulty.Such as, on the logic chip of 55nm, the size of its active area (AA) is generally 86nm, and normal contact hole is of a size of 85 ~ 90nm, its contact hole etching technique adopts photoresist masking process, but on 55nmCIS chip, if the size constancy of AA, that is for ensureing enough process windows, logic area contact hole size needs to narrow down to about 70nm, this size just can not have been come by simple photoresist mask etching technique, then need non-setting carbon hardmask etching technics, its process complexity and cost increase all greatly.
In addition, in order to avoid the silicon oxide layer at the contact hole top of logic area synchronously etches the defect brought, existing technique mainly increases the thickness of the silicon oxide layer as interlayer dielectric layer (ILD), and the cmp time increased after the filling of tungsten plug, to cause the excessive loss of ILD silicon oxide layer, thus reduce the contact hole top ring-type scarf degree of depth, reduce the impact on subsequent handling, avoid causing the improper connection of contact hole; But this method technology difficulty is comparatively large, and technological effect neither be very desirable, easily causes other technological problems.
Summary of the invention
The invention discloses the synchronous etching technics of a kind of double structure contact hole, be applied to the Semiconductor substrate with logic area and photosensitive area, wherein, comprise the following steps:
Preparation silicon nitride barrier covers the surface of described Semiconductor substrate;
Remove the silicon nitride barrier be positioned at above described photosensitive area;
Deposition high-aspect-ratio dielectric layer covers the surface of remaining silicon nitride barrier and Semiconductor substrate exposure;
Continue to deposit teos layer, protective layer and bottom anti-reflection layer successively;
Spin coating photoresist covers the surface of described bottom anti-reflection layer, after exposure, development, removes unnecessary photoresist, forms photoresistance;
With described photoresistance for after mask carries out etching technics, remove described photoresistance;
Continue logic area silicon nitride barrier etching technics, form double structure contact hole device.
The above-mentioned synchronous etching technics of double structure contact hole, wherein, described semiconductor device substrate comprises a silicon base, and the silicon base being positioned at described logic area is provided with shallow ditch non-intercommunicating cells;
Wherein, the surface being positioned at the silicon base of described logic area is provided with first grid structure and nickel silicide layer, the surface being positioned at the silicon base of described photosensitive area is provided with second grid structure and silica barrier layer, and described silica barrier layer covers the surface of described second grid structure and described silicon base is positioned at the surface that described photosensitive area exposes.
The above-mentioned synchronous etching technics of double structure contact hole, wherein, described photoresistance has double structure contact hole pattern.
The above-mentioned synchronous etching technics of double structure contact hole, wherein, forms a dielectric insulation layer by high-aspect-ratio dielectric layer and teos layer;
Wherein, carry out etching technics with described photoresistance for mask, comprising:
Carry out bottom anti-reflection layer etching technics;
Dielectric insulation layer main etching technique;
Dielectric insulation layer over etching technique.
The above-mentioned synchronous etching technics of double structure contact hole, wherein, adopts and carries out described dielectric insulation layer main etching technique to silica and the not high gas of silicon nitride Selection radio.
The above-mentioned synchronous etching technics of double structure contact hole, wherein, described is primarily of CF to silica and the not high gas of silicon nitride Selection radio
4, C
4f
8, Ar and O
2the mist of composition.
The above-mentioned synchronous etching technics of double structure contact hole, wherein, adopts and carries out described dielectric insulation layer over etching technique to silica and the high gas of silicon nitride, silica and silicon nitride selection and comparison.
The above-mentioned synchronous etching technics of double structure contact hole, wherein, described is primarily of C to silica and the high gas of silicon nitride selection and comparison
4f
6, Ar and O
2the mist of composition.
The above-mentioned synchronous etching technics of double structure contact hole, wherein, adopts the mist be made up of CH3F6, Ar and O2 to carry out described logic area silicon nitride barrier etching technics.
The above-mentioned synchronous etching technics of double structure contact hole, wherein, the material of high-aspect-ratio dielectric layer and teos layer is silica.
In sum, owing to have employed technique scheme, the synchronous etching technics of a kind of double structure contact hole of the present invention, behind deposited silicon nitride barrier layer, remove immediately and be arranged in photosensitive area silicon nitride barrier, and then change the Structure of the deposits of double structure contact hole of CIS product, and in follow-up etching technics, increase the etching selection ratio of the relative barrier layer of interlayer dielectric layer (insulation dielectric layer) and silicon base, and then decrease separately for the etch step on bottom oxide silicon barrier layer, photosensitive area, reach while formation double structure contact hole, reduce the silicon oxide loss of logic area non-boundary contact hole on STI, effectively prevent because logic area non-boundary contact hole is at the excessively dark silicon oxide loss of STI, cause the problem of crossing the electric leakage that the land of ion implantation and substrate silicon form path and cause at tungsten plug fill process after-current, simultaneously, effectively can also avoid the problem that contact hole top ring-type scarf is excessive, and then reduce due to the excessive process risk causing the improper connection of contact hole of the oblique facet of top ring-type, increase process window, improve the yield of reliability of technology and stability and product.
Accompanying drawing explanation
Fig. 1 is the device architecture schematic diagram of traditional preparation CIS product;
Fig. 2 is the structural representation of traditional synchronous etching technics design of double structure contact hole;
Fig. 3 is the structural representation in traditional synchronous etching technics actual production of double structure contact hole;
Fig. 4-11 is flowage structure schematic diagrames of the synchronous etching technics of a kind of double structure contact hole in embodiment.
Embodiment
Below in conjunction with accompanying drawing, the specific embodiment of the present invention is further described:
The synchronous etching technics of double structure contact hole of the application, first, after a Semiconductor substrate with logic area and photosensitive area carries out the depositing operation of silicon nitride barrier, photoresist coating, developing process is carried out, form photoresistance, expose to the open air out to make the silicon nitride barrier being positioned at photosensitive area; Secondly, with above-mentioned photoresistance for mask carries out etching technics, to remove the silicon nitride barrier exposed, the silica be arranged in below the silicon nitride barrier of photosensitive area can be caused to have certain etching loss simultaneously, after photoresistance is removed in ashing, carry out the deposition of silicon oxide layer, photoresist coating and developing process thereof, form first photoresistance with double structure contact hole pattern; Wherein, above-mentioned silicon oxide layer from bottom to up order comprises HARP layer, TEOS layer, top layer silica (Capoxide) and BARC layer successively.
Then, carry out BARC and be etched to top layer silica (preferred, the material of this top layer silica is silicon oxynitride), the etching loss that top layer silica can be caused in this process certain; Continue dielectric insulation layer silica main etching technique, namely utilize CF
4/ C
4f
8/ Ar/O
2etc. combination of gases, etch top layer silica, TEOS layer and/or HARP layer successively, because above-mentioned combination of gases is not high to silica/silicon nitride etch Selection radio, and etching speed is fast, and etching homogeneity is good; In addition, when carrying out etching technics, make have 200 ~ 300A(as equivalent in 200A, 230A, 260A, 290A or 300A from the silicon nitride barrier of logic area top portions of gates bottom contact hole) silica exist.
Afterwards, C is adopted
4f
6/ Ar/O
2combination of gases, carry out dielectric insulation layer silica over etching technique, to complete the over etching of photosensitive area silica, and due to C
4f
6/ Ar/O
2the etch rate Selection radio of combination of gases to silica and silicon nitride/substrate silicon high (preferred, be respectively 12:1 and 20 ~ 30:1), make the etching speed of silicon nitride/substrate silicon slower, so just can make logic area grid and active area, and the silica on photosensitive area grid and active area (AA) is all etched totally, and be parked in silicon nitride barrier (corresponding bottom the contact hole of logic area, have certain silicon nitride barrier loss), and be parked in substrate silicon bottom the contact hole of photosensitive area; Wherein, because the Selection radio of etching is high, the loss of substrate silicon is made to be less than 50A.
Finally, the first above-mentioned photoresistance ashing is removed (preferred, and in same etching reaction chamber, utilize O
2the ashing carrying out photoresist is removed, and removes the etching residue polymer in contact hole simultaneously) after, adopt CH
3f/O
2the combination of gases such as/Ar, carry out logic area silicon nitride barrier etching technics, and due at CH
3f/O
2in the environment of the combination of gases such as/Ar, the etch rate Selection radio of silicon nitride to silica high (as 15:1), have the silicon nitride over etching amount of certain (being generally greater than 30%), and then it is clean to make the silicon nitride in the grid of logic area and AA district remove, and the metal silicide brought loss formation can be less than 100A, and the loss of substrate silicon in photosensitive area contact hole, grid and active area is less than 120A.
Through double structure contact hole prepared by above-mentioned processing step, by omitting the step removing photosensitive area bottom silica barrier layer, avoid the STI silicon oxide loss of non-boundary contact hole too much, the problem such as contact hole top ring-type scarf is excessive, i.e. under contact hole substrate silicon loss in photosensitive area increases little condition (substrate silicon loss is increased to about 100A from 70A), the STI silicon oxide loss of the non-boundary contact hole on active area, logic area (AA) can be made to be reduced to from about 700A and to be less than 100A; Simultaneously, the contact hole ring-type scarf degree of depth can be made by 400 ~ 500A, narrow down to and be less than 300A, make the semiconductor structure prepared meet the depth requirements (200 ~ 300A) of the contact hole top ring-type scarf of logic chip, and then expand process window, add technology stability.
Embodiment:
Fig. 4-11 is flowage structure schematic diagrames of the synchronous etching technics of a kind of double structure contact hole in embodiment; As shown in Fig. 4-11, the synchronous etching technics of a kind of double structure contact hole of the present invention:
First, provide the substrate 2 that has logic area (logic) 21 and photosensitive area (pixel) 22, this substrate 2 is for the preparation of CIS product; The substrate 2 being arranged in logic area 21 is also provided with shallow ditch non-intercommunicating cells (STI) 211, nickel silicide layer 212 and first grid structure 213, and this nickel silicide layer 212 to be covered in logic area the upper surface of grid in the surface of the substrate 2 do not covered by first grid structure 213 and first grid structure 213; The substrate 2 being arranged in photosensitive area 22 is provided with barrier layer (SOR) 221(preferred, the material on this barrier layer 221 is silica) and second grid structure 222, and this barrier layer 221 covers the surface of second grid structure 222 and is arranged in the surface of the substrate 2 that photosensitive area 12 is not covered by second grid structure 222; Continue Deposited Etch Stop (CESL) 23(preferred, the material of this etching stop layer 23 is silicon nitride) cover the surface of nickel silicide layer 212, first grid structure 213, shallow ditch non-intercommunicating cells 211 and silica barrier layer 221, form structure as shown in Figure 4.
Secondly, spin coating photoresist covers the surface of etching stop layer 23, after exposure, development, remove unnecessary photoresist, to form the second photoresistance top of covering logic district 21 (this second photoresistance only), and with this second photoresistance for mask (not indicating in figure), etching removes the etching stop layer being arranged in photosensitive area 22, after adopting cineration technics to remove the second photoresist, and then form the residue etching stop layer 231 above only covering logic district 21 as shown in Figure 5; Wherein, in the production technology of reality, when etching forms residue etching stop layer 231, the silica barrier layer 221 in photosensitive area has certain etching loss.
Then, the surface of deposition high-aspect-ratio dielectric layer (HARP) 24 capping oxidation silicon barrier layer 221 and residue etching stop layer 231, and continue the depositing operation carrying out teos layer (TEOS) 25, top layer silica (capoxide) 26 and bottom anti-reflection layer (BARC) 27 successively, after spin coating photoresist covers the surface of bottom anti-reflection layer 27, after exposure, developing process, remove unnecessary photoresist and form the 3rd photoresistance 28 with doubled via structure plan 29, wherein, in this processing step, in logic area 21, the thickness of metal silicide (nickel silicide layer 212) is that 200-300A(is as 200A, 220A, 240A, 260A, 280A or 300A is equivalent), the thickness of silicon nitride barrier (residue etching stop layer 231) is 600A, the thickness of silicon oxide layer (high-aspect-ratio dielectric layer 24 and bottom anti-reflection layer 27 form this silicon oxide layer jointly) is 2700A, and in photosensitive area 22, silica barrier layer 221, high-aspect-ratio dielectric layer 24 and bottom anti-reflection layer 27 three thickness sum are 3300A, the thickness of top layer silica (capoxide) 26 is 600A, the thickness of bottom anti-reflection layer (BARC) 27 is 900A, the thickness of the 3rd photoresistance 28 is 2000A.
Afterwards, adopt 130 ~ 170mT(as equivalent in 130mT, 150mT or 170mT) pressure, utilize 1000 ~ 1700W(as equivalent in 1000W, 1200W, 1500W or 1700W) source radio-frequency power, 300 ~ 500W(is as equivalent in 300W, 400W or 500W) bias voltage radio-frequency power, in reaction chamber, pass into 4 ~ 10sccm(as equivalent in 4sccm, 6sccm, 8sccm or 10sccm) C
4f
8, 200 ~ 400sccm(is as equivalent in 200sccm, 280sccm, 360sccm or 400sccm) CF
4, being under the condition of 20 DEG C in ESC temperature, is the surface of etching technics to top layer silica (capoxide) 26 that mask bottom anti-reflection layer 27 carries out 50s with the 3rd photoresistance 28, forms the structure as shown in Figure 7 with residue bottom anti-reflection layer 271; Wherein, in the etching technics of reality, this etching technics stops at the position in top layer silica (capoxide) 26.
Carry out silica main etching technique, namely be 20 ~ 50mT(as 20mT, 30mT, 40mT or 50mT are equivalent at pressure), source radio-frequency power is that 300 ~ 700W(is as equivalent in 300W, 350W, 450W, 550W or 700W), bias voltage radio-frequency power is 1300 ~ 1700W(as 1300W, 1400W, 1600W or 1700W are equivalent) condition under, in reaction chamber, pass into 18 ~ 24sccm(as equivalent in 18sccm, 20sccm, 22sccm or 24sccm) C
4f
8, 20 ~ 24sccm(is as equivalent in 20sccm, 23sccm or 24sccm) O
2, 40 ~ 60sccm(is as equivalent in 40sccm, 50sccm or 60sccm) CF
4600 ~ 800sccm(is as equivalent in 600sccm, 650sccm, 700sccm, 750sccm or 800sccm) Ar, and ESC temperature 20 DEG C is set, continue with the 3rd photoresistance 28 as mask, etching top layer silica (capoxide) 26, high-aspect-ratio dielectric layer (HARP) 24 and/or teos layer (TEOS) 25, and that this etching technics is 45s, wherein, in this processing step, the via etch be arranged in above grid structure stops at high-aspect-ratio dielectric layer (HARP) 24, the via etch of side then stops in teos layer (TEOS) 25 on the active area, and the distance H between the surface of the bottom of through hole in logic area above first grid structure 213 and residue etching stop layer 231 is that 200-300A(is as 200A, 240A, 260A, 280A or 300A is equivalent), to etch away most of ILD silicon oxide layer, formed and there is residue top layer silica (capoxide) 261 as shown in Figure 8, the structure of residue teos layer (TEOS) 251 and residue high-aspect-ratio dielectric layer (HARP) 241.
Proceed silica over etching technique, namely be 20 ~ 40mT(as 20mT, 30mT or 40mT are equivalent at pressure), source radio-frequency power is that 300 ~ 800W(is as equivalent in 300W, 450W, 550W, 750W or 800W), bias voltage radio-frequency power is 300 ~ 700W(as 300W, 400W, 500W or 700W are equivalent) condition under, in reaction chamber, pass into 10 ~ 14sccm(as equivalent in 10sccm, 11sccm, 12sccm or 14sccm) C
4f
6, 10 ~ 15sccm(is as equivalent in 10sccm, 13sccm or 15sccm) O
2, 400 ~ 600sccm(is as 400sccm, 450sccm, 500sccm, 550sccm or 600sccm is equivalent) Ar, and ESC temperature 20 DEG C is set, and continue with the 3rd photoresistance 28 as mask, carry out the etching technics of 90s, to remove silicon oxide layer (residue high-aspect-ratio dielectric layer 241 and barrier layer 221) residual on the active area of logic area 21 and photosensitive area 22, and to utilize in above-mentioned mist silica to the etching high selectivity of silicon nitride, the through hole 33 above the first grid structure 213 of logic area 21 and the contact hole 32 on active area is made to rest on residue etching stop layer 231, equally, utilize silica to the etching high selectivity of substrate silicon, through hole 32 above the second grid structure 222 of photosensitive area 22 and the contact hole 30 on active area are rested in substrate silicon 2, and then forms the structure as shown in Figure 9 again with etching residue high-aspect-ratio dielectric layer (HARP) 242 and residue barrier layer 223.
Cineration technics is carried out to the 3rd photoresistance 28, namely be 40 ~ 60mT(as 40mT, 50mT or 60mT are equivalent at pressure), source radio-frequency power is that 300 ~ 500W(is as equivalent in 300W, 350W, 400W, 450W or 500W), bias voltage radio-frequency power is 200 ~ 600W(as 200W, 300W, 500W or 600W are equivalent) condition under, in reaction chamber, pass into 200 ~ 600sccm(as equivalent in 200sccm, 400sccm or 600sccm) O
2400 ~ 600sccm(is as equivalent in 400sccm, 450sccm, 500sccm, 550sccm or 600sccm) Ar, and ESC temperature 20 DEG C is set, carry out the etching technics of 60s, to remove all photoresists and BARC layer, and the etch polymers etc. in contact hole, form the structure shown in Figure 10.
Finally, be 20 ~ 30mT(as 20mT, 25mT or 30mT are equivalent at pressure), source radio-frequency power is that 300 ~ 700W(is as equivalent in 300W, 350W, 450W, 650W or 700W), bias voltage radio-frequency power is 100 ~ 300W(as 100W, 150W, 200W or 300W are equivalent) condition under, in reaction chamber, pass into 18 ~ 24sccm(as equivalent in 18sccm, 20sccm, 22sccm or 24sccm) CH
3f, 6 ~ 8sccm(are as equivalent in 6sccm, 7sccm or 8sccm) O
2200 ~ 400sccm(is as equivalent in 200sccm, 250sccm, 300sccm, 350sccm or 400sccm) Ar, and ESC temperature 20 DEG C is set, carry out the etching technics of 45s, to remove in logic area 21 silicon nitride barrier on first grid structure 213 grid in through hole 33 and active region contact hole 32; Due in the production technology of reality, at CH
3f/O
2in the environment of the combination of gases such as/Ar, the etch rate Selection radio of silicon nitride to silica high (as 15:1), have the silicon nitride over etching amount of certain (being generally greater than 30%), and then it is clean to make the silicon nitride in the grid of logic area and AA district remove, but the metal silicide that simultaneously can bring loss (being less than 100A), and the substrate silicon in photosensitive area contact hole, grid and active area also has loss (being less than 120A), and make the top of contact hole form ring-type scarf (degree of depth is less than 300A), i.e. structure as shown in figure 11.
Preferably, the synchronous etching technics of a kind of double structure contact hole of the present embodiment, on the technology nodes such as 65/55nm or 90nm, can be applicable to the technology platforms such as Dryetch.
In sum, owing to have employed technique scheme, the present invention proposes the synchronous etching technics of a kind of double structure contact hole, behind deposited silicon nitride barrier layer, remove immediately and be arranged in photosensitive area silicon nitride barrier, and then change the Structure of the deposits of double structure contact hole of CIS product, and in follow-up etching technics, increase the etching selection ratio of the relative barrier layer of interlayer dielectric layer (insulation dielectric layer) and silicon base, and then decrease separately for the etch step on bottom oxide silicon barrier layer, photosensitive area, reach while formation double structure contact hole, reduce the silicon oxide loss of logic area non-boundary contact hole on STI, effectively prevent because logic area non-boundary contact hole is at the excessively dark silicon oxide loss of STI, cause the problem of crossing the electric leakage that the land of ion implantation and substrate silicon form path and cause at tungsten plug fill process after-current, simultaneously, effectively can also avoid the problem that contact hole top ring-type scarf is excessive, and then reduce due to the excessive process risk causing the improper connection of contact hole of the oblique facet of top ring-type, increase process window, improve the yield of reliability of technology and stability and product.
By illustrating and accompanying drawing, giving the exemplary embodiments of the ad hoc structure of embodiment, based on the present invention's spirit, also can do other conversion.Although foregoing invention proposes existing preferred embodiment, but these contents are not as limitation.
For a person skilled in the art, after reading above-mentioned explanation, various changes and modifications undoubtedly will be apparent.Therefore, appending claims should regard the whole change and correction of containing true intention of the present invention and scope as.In Claims scope, the scope of any and all equivalences and content, all should think and still belong to the intent and scope of the invention.
Claims (7)
1. the synchronous etching technics of double structure contact hole, is applied to the Semiconductor substrate with logic area and photosensitive area, it is characterized in that, comprise the following steps:
Preparation silicon nitride barrier covers the surface of described Semiconductor substrate;
Remove the silicon nitride barrier be positioned at above described photosensitive area;
Deposition high-aspect-ratio dielectric layer covers the surface of remaining silicon nitride barrier and Semiconductor substrate exposure;
Continue to deposit teos layer, protective layer and bottom anti-reflection layer successively;
Spin coating photoresist covers the surface of described bottom anti-reflection layer, after exposure, development, removes unnecessary photoresist, forms photoresistance;
With described photoresistance for after mask carries out etching technics, remove described photoresistance;
Continue logic area silicon nitride barrier etching technics, form double structure contact hole device;
Wherein, described photoresistance has double structure contact hole pattern;
A dielectric insulation layer is formed by described high-aspect-ratio dielectric layer and described teos layer;
Wherein, carry out etching technics with described photoresistance for mask, comprising:
Bottom anti-reflection layer etching technics;
Dielectric insulation layer main etching technique;
Dielectric insulation layer over etching technique;
Adopt and described dielectric insulation layer main etching technique is carried out to silica and the not high gas of silicon nitride Selection radio.
2. the synchronous etching technics of double structure contact hole according to claim 1, it is characterized in that, described Semiconductor substrate comprises a silicon base, and the silicon base being positioned at described logic area is provided with shallow ditch non-intercommunicating cells;
Wherein, the surface being positioned at the silicon base of described logic area is provided with first grid structure and nickel silicide layer, the surface being positioned at the silicon base of described photosensitive area is provided with second grid structure and silica barrier layer, and described silica barrier layer covers the surface of described second grid structure and described silicon base is positioned at the surface that described photosensitive area exposes.
3. the synchronous etching technics of double structure contact hole according to claim 1, is characterized in that, described is primarily of CF to silica and the not high gas of silicon nitride Selection radio
4, C
4f
8, Ar and 0
2the mist of composition.
4. the synchronous etching technics of double structure contact hole according to claim 1, is characterized in that, adopts and carries out described dielectric insulation layer over etching technique to silica and the high gas of silicon nitride selection and comparison.
5. the synchronous etching technics of double structure contact hole according to claim 4, is characterized in that, described is primarily of C to silica and the high gas of silicon nitride selection and comparison
4f
6, Ar and 0
2the mist of composition.
6. the synchronous etching technics of double structure contact hole according to claim 1, is characterized in that, adopt by CH
3f, Ar and 0
2the mist of composition carries out described logic area silicon nitride barrier etching technics.
7. the synchronous etching technics of double structure contact hole according to claim 1, it is characterized in that, the material of high-aspect-ratio dielectric layer and teos layer is silica.
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| CN103560082A (en) * | 2013-11-13 | 2014-02-05 | 上海华力微电子有限公司 | CMOS complementary metal oxide semiconductor contact hole etching method and CMOS complementary metal oxide semiconductor manufacturing method |
| CN103560137A (en) * | 2013-11-13 | 2014-02-05 | 上海华力微电子有限公司 | CMOS complementary metal oxide semiconductor contact hole etching method and CMOS complementary metal oxide semiconductor manufacturing method |
| CN103633106B (en) * | 2013-11-28 | 2016-06-29 | 上海华力微电子有限公司 | CMOS contact hole etching method and CMOS manufacture method |
| CN105742237B (en) * | 2016-02-26 | 2019-01-18 | 上海华力微电子有限公司 | Double structure contact hole synchronizes etching technics |
| CN105789115A (en) * | 2016-04-26 | 2016-07-20 | 京东方科技集团股份有限公司 | Via hole manufacturing method, array substrate and manufacturing method thereof and display device |
| CN107546118B (en) * | 2016-06-29 | 2020-05-22 | 中芯国际集成电路制造(北京)有限公司 | CMOS image sensor, preparation method thereof and electronic device |
| CN107665856B (en) * | 2016-07-29 | 2020-04-03 | 中微半导体设备(上海)股份有限公司 | Method for forming contact hole and plasma etching method |
| CN108511342B (en) * | 2017-02-24 | 2021-05-14 | 中芯国际集成电路制造(上海)有限公司 | Method for manufacturing semiconductor device |
| CN109904072B (en) * | 2017-12-07 | 2022-04-15 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor device and method of forming the same |
| CN108538871A (en) * | 2018-03-16 | 2018-09-14 | 德淮半导体有限公司 | The forming method and imaging sensor of contact hole |
| CN111261636B (en) * | 2020-01-21 | 2021-07-20 | 长江存储科技有限责任公司 | Contact groove forming method and semiconductor |
| CN111653476A (en) * | 2020-05-13 | 2020-09-11 | 上海华虹宏力半导体制造有限公司 | Etching method and structure of contact hole |
| CN113284808B (en) * | 2021-07-22 | 2021-10-15 | 江苏茂硕新材料科技有限公司 | Preparation method of semiconductor structure |
| CN113838881B (en) * | 2021-11-26 | 2022-02-08 | 晶芯成(北京)科技有限公司 | Image sensor and method for manufacturing the same |
| CN115148666B (en) * | 2022-09-02 | 2022-12-02 | 合肥晶合集成电路股份有限公司 | Method for manufacturing semiconductor device |
| CN116936469A (en) * | 2023-09-14 | 2023-10-24 | 深圳基本半导体有限公司 | Method for manufacturing semiconductor device |
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| US7098114B1 (en) * | 2004-06-22 | 2006-08-29 | Integrated Device Technology, Inc. | Method for forming cmos device with self-aligned contacts and region formed using salicide process |
| TWI302754B (en) * | 2005-02-28 | 2008-11-01 | Magnachip Semiconductor Ltd | Complementary metal-oxide-semiconductor image sensor and method for fabricating the same |
| KR100859481B1 (en) * | 2006-12-29 | 2008-09-23 | 동부일렉트로닉스 주식회사 | CMOS Image Sensor and Method of Manufaturing Thereof |
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