CN103456615B - Improve the method for metal silicide mask layer defect - Google Patents
Improve the method for metal silicide mask layer defect Download PDFInfo
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- CN103456615B CN103456615B CN201310393694.5A CN201310393694A CN103456615B CN 103456615 B CN103456615 B CN 103456615B CN 201310393694 A CN201310393694 A CN 201310393694A CN 103456615 B CN103456615 B CN 103456615B
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Abstract
The present invention relates to and improve metal silicide grinding layer technical field, particularly relate to a kind of method improving metal silicide mask layer defect.The invention discloses a kind of method improving metal silicide mask layer defect; by after preparing metal silicide mask layer; one deck oxide film is covered on this metal silicide mask layer; using as its protective layer; in follow-up photoetching process; contact with photoresist with isolated metal silicide mask layer, and then effectively avoid forming defect because metal silicide mask layer and photoresist react, enhance product performance and the yield of product.
Description
Technical field
The present invention relates to and improve metal silicide grinding layer technical field, particularly relate to a kind of method improving metal silicide mask layer defect.
Background technology
In semiconductor processing and manufacturing process, how effectively solving the defect produced in single technique and integrated technique is improve the reliability of product and the key of yield.
At present; in semiconductor fabrication process; metal silicide mask layer (SalicideBlock; be called for short SAB) mainly play the effect of the reaction blocking Si and NiPt on the subregion of device, protection device not to need the part of metal silicide line can not grown silicon compound (Salicide).
Fig. 1-6 is traditional metal silicide masking layer process flowage structure schematic diagrames; As shown in figures 1 to 6, the surface of semi-conductive substrate 11 is provided with etching barrier layer 111, depositing metal suicide mask layers 12 on the surface of this etching barrier layer 11, adopt photoetching process on this metal silicide mask layer 12, form the figuratum photoresistance 13 of tool, and with the surface of this photoresistance 13 for Mask portion etching metal silicide mask layer 12 to metal barrier 111, remove photoresistance 13; Continue to prepare W metal Pt layer 14 and cover the surface of remaining metal silicide mask layer 121 and the surface of Semiconductor substrate 11 expose portion, and after annealing process, remove this W metal Pt layer 14.
Because photoresistance is made up of sensitising agent, resin, solvent and additive, and sensitising agent (PAG) can produce H after illumination
+the insured's base R in resin can be replaced in follow-up bake process, thus be dissolved in developer solution, accordingly with PECVD growth metal silicide mask layer 12 surface containing H composition will with exposure after photoresist react, and then disturb the molecular balance of photoresist inside, cause the generation of defect; Namely in above-mentioned processing step, nitride (nitride) deposit is used to form metal silicide mask layer 12, when subsequent metal suicide mask layers 12 spin coating photoresist carries out photoetching process formation photoresistance 13 to carry out selective etch to metal silicide mask layer 12, metal silicide mask layer 12 contacts with PR and after too high Taoist scripture cavity, can form special defect again after SAB illumination operation as ball defects (balldefect), ring defect (ringmap) etc., and then the performance of product can be affected, reduce the yield of product.
Summary of the invention
The invention discloses a kind of method improving metal silicide mask layer defect, be applied in the photoetching process of Semiconductor substrate, described Semiconductor substrate comprises silicon base, be positioned at grid structure on this silicon substrate surface and an etching barrier layer, described etching barrier layer covers on the surface of described grid structure and the surface of described silicon base exposure, wherein, said method comprising the steps of:
A metal silicide mask layer is prepared in the surface of described etching barrier layer;
Prepare the surface that oxide skin(coating) covers described metal silicide mask layer;
Coating photoresist covers described oxide layer surface, after exposure, development, removes unnecessary photoresist, forms photoresistance pattern in described oxide layer;
With described photoresistance pattern for mask, the oxide skin(coating) that etching exposes is to the surface of described silicon base and described grid structure;
Remove described photoresistance pattern and remaining oxide layer;
Prepare the surface that metal level covers the Semiconductor substrate of remaining metal silicide mask layer and exposure;
Continue annealing process.
The method of above-mentioned improvement metal silicide mask layer defect, adopts chemical vapor deposition method to prepare described oxide skin(coating).
The method of above-mentioned improvement metal silicide mask layer defect, wherein, the thickness of described oxide skin(coating) is
.
The method of above-mentioned improvement metal silicide mask layer defect, wherein, removes described metal level after described annealing process.
The method of above-mentioned improvement metal silicide mask layer defect, wherein, the material of described metal level is NiPt.
The method of above-mentioned improvement metal silicide mask layer defect, wherein, the material of metal silicide mask layer is nitride.
The method of above-mentioned improvement metal silicide mask layer defect, wherein, using plasma strengthens chemical vapor deposition method and prepares described metal silicide mask layer.
The method of above-mentioned improvement metal silicide mask layer defect, wherein, is formed with non-self-aligned polycrystalline silicon district, P type trap, N-type trap and shallow channel isolation area in described silicon base.
The method of above-mentioned improvement metal silicide mask layer defect, wherein, described photoresistance pattern lid covers the oxide skin(coating) being positioned at the top in described non-self-aligned polycrystalline silicon district.
The method of above-mentioned improvement metal silicide mask layer defect, wherein, adopts sputtering process to prepare described metal level.
In sum; owing to have employed technique scheme; the present invention proposes a kind of method improving metal silicide mask layer defect; by after preparing metal silicide mask layer, on this metal silicide mask layer, cover one deck oxide film, using as its protective layer; in follow-up photoetching process; contact with photoresist with isolated metal silicide mask layer, and then effectively avoid forming defect because metal silicide mask layer and photoresist react, enhance product performance and the yield of product.
Accompanying drawing explanation
Fig. 1-6 is traditional metal silicide masking layer process flowage structure schematic diagrames;
Fig. 7-13 improves the Structure and Process schematic diagram of an embodiment in the method for metal silicide mask layer defect for the present invention.
Embodiment
Below in conjunction with accompanying drawing, the specific embodiment of the present invention is further described:
Fig. 7-13 improves the Structure and Process schematic diagram of an embodiment in the method for metal silicide mask layer defect for the present invention; As illustrated in figures 7 to 13, a kind of method improving metal silicide mask layer defect, is applied in photolithography process:
First, as shown in Figure 7, there is provided semi-conductive substrate 1, and Semiconductor substrate comprises silicon base 101, is arranged on the grid structure 102 of this silicon substrate surface and etching barrier layer 103, the surface that the surface of etching barrier layer 103 overlies gate structure 102 and silicon base 101 expose; Wherein, non-self-aligned polycrystalline silicon district (non-salicidepoly), P type trap (PW), N-type trap (NW) and shallow channel isolation area (STI) is provided with in silicon base 101.
Secondly, using plasma strengthens the surface (SABNitrideDeposition) that chemical vapor deposition method (PECVD) plated metal suicide mask layers 2 covers above-mentioned etching barrier layer 102, forms structure as shown in Figure 8.
Afterwards, employing chemical vapor deposition method (CVD) deposit thickness is
(preferably
or
deng) oxide skin(coating) 3 cover the surface (OxideCapforProtection) of metal silicide mask layer 2, using the inertia protective layer as metal silicide mask layer 2, namely form structure as shown in Figure 9.
Then, as shown in Figure 10, the surface of coating photoresist capping oxidation nitride layer 3, after exposure, developing process, remove unnecessary photoresist, photoresistance pattern 4(SABPhoto is formed on the surface of above-mentioned oxide layer 3), and this photoresistance pattern 4 covers the oxide skin(coating) covering and be positioned at the top in above-mentioned non-self-aligned polycrystalline silicon district; Continue with this photoresistance pattern 4 as mask, the oxide skin(coating) that etching exposes is to (the metal silicide mask layer below the oxide skin(coating) being positioned at exposure and etching barrier layer are also removed) in the silicon base of Semiconductor substrate 1 and the surface of grid structure, after removing photoresistance pattern 4, form structure (SABEtch) as shown in figure 11.
Wherein, as shown in figure 11, remaining etching barrier layer 1031 is positioned at the top in non-self-aligned polycrystalline silicon district, and namely remaining etching barrier layer 1031 covers the surface of the silicon base of the top exposure being positioned at non-self-aligned polycrystalline silicon district and is positioned on the surface of upper gate structure in non-self-aligned polycrystalline silicon district.
Finally, as shown in figure 12, sputtering process is adopted to prepare metal level 4(metalsputter) surface of silicon base 101 that covers remaining metal silicide mask layer 31 and expose, and after annealing process (RTAanneal), remove this metal level 4(SalicideMetalStrip).
Further, the material of described metal level can be NiPt, and the material of metal silicide mask layer 2 is nitride.
Preferably, the method of the improvement metal silicide mask layer defect in above-described embodiment is applied to 90nm, 65/55nm, 45/40nm, 32/28nm or is less than or equal on the technology nodes such as 22nm, and the technology platform of its application is Logic, Memory, RF, HV, Analog/Power, Flash, eFlash etc.
In sum; owing to have employed technique scheme; the present invention proposes a kind of method improving metal silicide mask layer defect; by after preparing metal silicide mask layer, on this metal silicide mask layer, cover one deck oxide film, using as its protective layer; in follow-up photoetching process; contact with photoresist with isolated metal silicide mask layer, and then effectively avoid forming defect because metal silicide mask layer and photoresist react, enhance product performance and the yield of product.
By illustrating and accompanying drawing, giving the exemplary embodiments of the ad hoc structure of embodiment, based on the present invention's spirit, also can do other conversion.Although foregoing invention proposes existing preferred embodiment, but these contents are not as limitation.
For a person skilled in the art, after reading above-mentioned explanation, various changes and modifications undoubtedly will be apparent.Therefore, appending claims should regard the whole change and correction of containing true intention of the present invention and scope as.In Claims scope, the scope of any and all equivalences and content, all should think and still belong to the intent and scope of the invention.
Claims (10)
1. one kind is improved the method for metal silicide mask layer defect, be applied in the photoetching process of Semiconductor substrate, described Semiconductor substrate comprises silicon base, be positioned at grid structure on this silicon substrate surface and an etching barrier layer, described etching barrier layer covers on the surface of described grid structure and the surface of described silicon base exposure, it is characterized in that, said method comprising the steps of:
A metal silicide mask layer is prepared in the surface of described etching barrier layer;
Prepare the surface that oxide skin(coating) covers described metal silicide mask layer, using the inertia protective layer as described metal silicide mask layer;
Coating photoresist covers described oxide layer surface, after exposure, development, removes unnecessary photoresist, forms photoresistance pattern in described oxide layer;
With described photoresistance pattern for mask, the oxide skin(coating) that etching exposes is to the surface of described silicon base and described grid structure;
Remove described photoresistance pattern and remaining oxide layer;
Prepare the surface that metal level covers the Semiconductor substrate of remaining metal silicide mask layer and exposure;
Continue annealing process.
2. improve the method for metal silicide mask layer defect as claimed in claim 1, adopt chemical vapor deposition method to prepare described oxide skin(coating).
3. improve the method for metal silicide mask layer defect as claimed in claim 1, it is characterized in that, the thickness of described oxide skin(coating) is
4. improve the method for metal silicide mask layer defect as claimed in claim 1, it is characterized in that, after described annealing process, remove described metal level.
5. improve the method for metal silicide mask layer defect as claimed in claim 1, it is characterized in that, the material of described metal level is NiPt.
6. improve the method for metal silicide mask layer defect as claimed in claim 1, it is characterized in that, the material of metal silicide mask layer is nitride.
7. improve the method for metal silicide mask layer defect as claimed in claim 1, it is characterized in that, using plasma strengthens chemical vapor deposition method and prepares described metal silicide mask layer.
8. improve the method for metal silicide mask layer defect as claimed in claim 1, it is characterized in that, in described silicon base, be formed with non-self-aligned polycrystalline silicon district, P type trap, N-type trap and shallow channel isolation area.
9. improve the method for metal silicide mask layer defect as claimed in claim 8, it is characterized in that, described photoresistance pattern lid covers the oxide skin(coating) being positioned at the top in described non-self-aligned polycrystalline silicon district.
10. improve the method for metal silicide mask layer defect as claimed in claim 1, it is characterized in that, adopt sputtering process to prepare described metal level.
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN1881565A (en) * | 2005-06-17 | 2006-12-20 | 东部电子株式会社 | CMOS image sensor and manufacturing method thereof |
| CN101123271A (en) * | 2006-08-11 | 2008-02-13 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor device and its making method |
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| US20080258188A1 (en) * | 2007-04-23 | 2008-10-23 | United Microelectronics Corp. | Metal oxide semiconductor device and method of fabricating the same |
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Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1881565A (en) * | 2005-06-17 | 2006-12-20 | 东部电子株式会社 | CMOS image sensor and manufacturing method thereof |
| CN101123271A (en) * | 2006-08-11 | 2008-02-13 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor device and its making method |
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