CN103560082A - CMOS complementary metal oxide semiconductor contact hole etching method and CMOS complementary metal oxide semiconductor manufacturing method - Google Patents
CMOS complementary metal oxide semiconductor contact hole etching method and CMOS complementary metal oxide semiconductor manufacturing method Download PDFInfo
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- CN103560082A CN103560082A CN201310566516.8A CN201310566516A CN103560082A CN 103560082 A CN103560082 A CN 103560082A CN 201310566516 A CN201310566516 A CN 201310566516A CN 103560082 A CN103560082 A CN 103560082A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
- H01L21/76805—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics the opening being a via or contact hole penetrating the underlying conductor
Abstract
The invention provides a CMOS complementary metal oxide semiconductor contact hole etching method and a CMOS complementary metal oxide semiconductor manufacturing method. The CMOS complementary metal oxide semiconductor contact hole etching method comprises the first step of using a photomask corresponding to a logic circuit are to carry out first photoetching technological operation, the second step of carrying out first dry etching technological operation on a stack structure corresponding to the logic circuit area, the third step of cleaning a wafer at the first time to remove etching byproducts, the fourth step of using a photomask corresponding to a pixel circuit area to carry out second photoetching technological operation, the fifth step of carrying out second dry etching technological operation on a stack structure corresponding to the pixel circuit area, and the sixth step of cleaning the wafer at the second time to remove etching byproducts.
Description
Technical field
The present invention relates to field of semiconductor manufacture, the present invention relates to a kind of CMOS(complementary metal oxide semiconductors (CMOS) more body) sensor devices contact hole etching method, more specifically the present invention relates to use two light shields to distinguish step by step the contact hole etching solution of counterlogic region and pixel region in a kind of CMOS of relating to sensor devices manufacturing process.。
Background technology
Fig. 1 schematically shows according to the step of the standard logic device contacts hole etching technics of prior art.As shown in Figure 1, standard logic device contacts hole etching technics is generally in five steps:
S10. interlayer dielectric layer main etching: for etching ILD(Interlayer dielectric, inter-level dielectric) layer, silica/silicon nitride etch speed is fast, selects than low, for the load effect between balance different pattern size.
S20. interlayer dielectric layer over etching: for etching ILD layer, silica etch rate is general, and silicon nitride etch speed is extremely slow, for overcoming the spatial distribution load effect of etch rate and the etching inhomogeneities that pattern density load effect causes.
S30. remove photoresist: for photoresist ashing, remove.
S40. etching barrier layer etching: for opening the etching barrier layer of interlayer dielectric layer etch stages, main component is silicon nitride, makes contact hole arrive the nickel silicide layer of bottom.Conventionally need silicon nitride etch speed fast, the process conditions that silica etch rate is extremely slow.
S50. etching reprocessing (this step is optional step): remove or etching injury reparation for polymer.
Wherein the 4th step is committed step, and in the etching technics of standard logic device contacts hole, meeting employing is very fast and slower to silica etch rate to silicon nitride etch speed conventionally, that is silicon nitride is selected higher process conditions to silica.This is due to during this step, and interlayer dielectric layer top lacks photoresist protection, can cause certain damage to interlayer dielectric layer.Thus, select the slower process conditions of silica etch rate, can reduce as far as possible the loss of inter-level dielectric layer thickness, and then reduce the layer capacitance loss bringing due to its thickness attenuation; In addition, this step can cause certain loss to the nickel silicide layer of contact hole bottom, and has certain probability that the nickel silicide in " contact of tungsten-nickel silicide-silicon " structure has been consumed, thereby it is abnormal that contact resistance is occurred.Therefore accurately control the process window of this step, when enabling to meet the needs of etching barrier layer, also have too much of a good thing, can not be too much for nickel silicide layer loss.
For example, the Chinese patent CN103066096A(list of references 2 that the Chinese patent CN101211952A(list of references 1 that is entitled as " cmos image sensor and manufacture method thereof "), is entitled as " manufacture method of back-illuminated type CMOS image sensor ") and the Chinese patent application CN200810205394.9(list of references 3 that is entitled as " a kind of lithographic method and method for manufacturing contact hole ") technology relevant to the preparation technology of cmos image sensor part and contact hole all proposed.
Summary of the invention
Technical problem to be solved by this invention is for there being above-mentioned defect in prior art, and a kind of CMOS sensor devices contact hole etching method that can make critical dimension of contact hole, pattern and electrical parameter all meet designing requirement is provided.
In order to realize above-mentioned technical purpose, according to a first aspect of the invention, provide a kind of CMOS sensor devices contact hole etching method, it comprises:
First step, is used the light shield of counterlogic circuit region to carry out photoetching process operation for the first time;
Second step, the layer pile structure of counterlogic circuit region carries out dry carving technology operation for the first time;
Third step, cleans for the first time to wafer, to remove etch by-products;
The 4th step, is used the light shield of respective pixel circuit region to carry out photoetching process operation for the second time;
The 5th step, respective pixel circuit region layer pile structure carries out dry carving technology operation for the second time;
The 6th step, cleans for the second time to wafer, to remove etch by-products.
Preferably, wherein using in the 4th step the light shield of respective pixel circuit region to carry out photoetching process operation for the second time comprises:
Step 1: the interlayer dielectric layer that comprises silica and silicon nitride is carried out to main etching, with etching interlayer dielectric layer;
Step 2: carry out interlayer dielectric layer over etching, with further etching interlayer dielectric layer, wherein, the etch rate of silica and silicon nitride is less than respectively silica in step 1 and the etch rate of silicon nitride, and wherein silica etch rate is greater than silica etch rate;
Step 3: carry out and remove photoresist;
Step 4: carry out etching barrier layer etching, for opening the etching barrier layer of interlayer dielectric layer etch stages, make contact hole arrive the nickel silicide layer of bottom;
Step 5: carry out polymer and remove, in order to remove the polymer of the rich carbon fluorine of etching barrier layer etching process applying plasma and silicon nitride formation;
Step 6: carry out silica and remove step, for the silicon oxide layer of etching pixel region Si-gate and active region top.
Preferably, in the 4th step, use the light shield of respective pixel circuit region to carry out photoetching process operation for the second time and also comprise: step 7, carry out etching reprocessing, for polymer, remove or etching injury reparation.
Preferably, in second step, a layer pile structure for counterlogic circuit region carries out for the first time dry carving technology operation and comprises:
Step 1: the interlayer dielectric layer that comprises silica and silicon nitride is carried out to main etching, with etching interlayer dielectric layer;
Step 2: carry out interlayer dielectric layer over etching, with further etching interlayer dielectric layer, wherein, the etch rate of silica and silicon nitride is less than respectively silica in step 1 and the etch rate of silicon nitride, and wherein silica etch rate is greater than silica etch rate;
Step 3: carry out and remove photoresist;
Step 4: carry out etching barrier layer etching, for opening the etching barrier layer of interlayer dielectric layer etch stages, make contact hole arrive the nickel silicide layer of bottom.
Preferably, in second step, a layer pile structure for counterlogic circuit region carries out for the first time dry carving technology operation and also comprises: step 7, carry out etching reprocessing, and for polymer, remove or etching injury reparation.
Preferably, described CMOS sensor devices contact hole etching method is implemented in the cmos image sensor technique of 55nm.
According to a second aspect of the invention, provide a kind of CMOS sensor devices manufacture method, it has adopted described according to a first aspect of the invention CMOS sensor devices contact hole etching method.
The present invention is optimized traditional logical circuit contact hole etching method, to adapt to CMOS sensor devices zones of different and different layers pile structure; Thus, the present invention adopts two light shield methods to carry out step by step dry etching to the contact hole in CMOS sensor devices logical circuit region and image element circuit region, and the critical dimension of contact hole of acquisition, pattern and electrical parameter meet designing requirement.
Accompanying drawing explanation
By reference to the accompanying drawings, and by reference to detailed description below, will more easily to the present invention, there is more complete understanding and more easily understand its advantage of following and feature, wherein:
Fig. 1 schematically shows according to the flow chart of the standard logic device contacts hole etching technics step of prior art.
Fig. 2 schematically shows according to the flow chart of the CMOS sensor devices contact hole etching method of the embodiment of the present invention.
Fig. 3 is according to the schematic diagram of the CMOS sensor devices contact hole etching method of the embodiment of the present invention.
The layer pile structure that Fig. 4 schematically shows the counterlogic circuit region of second step S2 carries out the flow chart of an example of the operation of dry carving technology for the first time.
The light shield that Fig. 5 schematically shows the use respective pixel circuit region of the 4th step S4 carries out the flow chart of an example of photoetching process operation for the second time.
It should be noted that, accompanying drawing is used for illustrating the present invention, and unrestricted the present invention.Note, the accompanying drawing that represents structure may not be to draw in proportion.And in accompanying drawing, identical or similar element indicates identical or similar label.
Embodiment
In order to make content of the present invention more clear and understandable, below in conjunction with specific embodiments and the drawings, content of the present invention is described in detail.
Cmos image sensor part is divided into pixel and two regions of logic by device area, and the former is responsible for receiving optical signal (pattern) and it is converted into current signal; The processing that the current signal that latter is collected pixel region is correlated with, to realize high frame rate, the correlation function of wide dynamic range and low noise and so on.
For the logic region of cmos image sensor part, this logic region is consistent with the layer pile structure of standard logic processing procedure contact hole etching; For the pixel region of cmos image sensor part, this pixel region and standard logic region layer pile structure difference have two, one, and this region silicon gate and active area cover without nickel silicide; Its two, between this pixel region silicon gate and active area and contact hole etching barrier layer (CESL), be covered with the residual silicon dioxide separator of the first side wall (Spacer1) processing procedure and silicide barrier layer processing procedure (SAB).For pixel region, there is no nickel silicide, there is no conversion layer between tungsten bolt and silicon, make tungsten-silicon structure contact hole resistance can be higher than the resistance value of the tungsten-nickel silicide-silicon structure of standard contact hole etching, and then how by controlling silicon depth of groove (silicon recess) and plasma damage (the Plasma induce damage in contact hole etching process, PID) reduce tungsten-silicon structure contact resistance, become the main target that etching technics is adjusted; And the silicon dioxide separator covering on Si-gate and active region, need to guarantee that contact hole can arrive on the Si-gate and active region of bottom smoothly for etching technics adjustment on the one hand, need on the other hand strictly to control its process window, to guarantee that the layer capacitance that top inter-level dielectric can excessive loss cause diminishes, and makes device performance impaired.
The present invention, on the basis of standard logic contact hole etching technique, adopts the method for the corresponding zones of different of different light shields, and dry etching is step by step carried out in the logical circuit region of CMOS sensor devices and image element circuit region.
Fig. 2 schematically shows according to the flow chart of the CMOS sensor devices contact hole etching method of the embodiment of the present invention.Fig. 3 is according to the schematic diagram of the CMOS sensor devices contact hole etching method of the embodiment of the present invention.
Specifically, as shown in Figures 2 and 3, according to the CMOS sensor devices contact hole etching method of the embodiment of the present invention, comprise:
First step S1: use the light shield of counterlogic circuit region to carry out photoetching process operation for the first time.
Second step S2: the layer pile structure of counterlogic circuit region carries out dry carving technology operation for the first time.
Third step S3: wafer is cleaned for the first time, to remove etch by-products.
The 4th step S4: use the light shield of respective pixel circuit region to carry out photoetching process operation for the second time.
The 5th step S5: respective pixel circuit region layer pile structure carries out dry carving technology operation for the second time.
The 6th step S6: wafer is cleaned for the second time, to remove etch by-products.
Thus, CMOS sensor devices contact hole etching technique completes.
Wherein, the dry carving technology condition in counterlogic circuit region and image element circuit region is optimized to some extent because of the difference of corresponding region layer pile structure, and related content is discussed to some extent in patent " a kind of step etching solution for CMOS sensor devices contact hole etching ".
Preferably, the layer pile structure that Fig. 4 schematically shows the counterlogic circuit region of second step S2 carries out the flow chart of an example of the operation of dry carving technology for the first time.
Specifically, as shown in Figure 4, the layer pile structure of the counterlogic circuit region of second step S2 carries out dry carving technology operation for the first time and can specifically comprise:
Step 1 S100: the interlayer dielectric layer that comprises silica and silicon nitride is carried out to main etching, with etching interlayer dielectric layer, wherein the etch rate of silica and silicon nitride is fast, and the etching selection ratio of silica and silicon nitride is low, for the load effect between balance different pattern size.
Step 2 S200: carry out interlayer dielectric layer over etching, with further etching interlayer dielectric layer, wherein, the etch rate of silica and silicon nitride is less than respectively silica in step 1 S100 and the etch rate of silicon nitride, and wherein silica etch rate is greater than silica etch rate; Silica etch rate is general, and silicon nitride etch speed is extremely slow, for overcoming the spatial distribution load effect of etch rate and the etching inhomogeneities that pattern density load effect causes.
Step 3 S300: carry out and remove photoresist, wherein photoresist ashing is removed.
Step 4 S400: carry out etching barrier layer etching, for opening the etching barrier layer (main component of etching barrier layer is generally silicon nitride) of interlayer dielectric layer etch stages, make contact hole arrive the nickel silicide layer of bottom.Conventionally need silicon nitride etch speed fast, the process conditions that silica etch rate is extremely slow.Preferably, wherein silicon nitride etch speed is greater than silica etch rate, and further preferably, silicon nitride etch speed is at least 2 times of silica etch rate; Still more preferably, silicon nitride etch speed is at least 5 times of silica etch rate.
After this, alternatively, can also carry out etching reprocessing (this step is optional step), for polymer, remove or etching injury reparation.
Preferably, the light shield that Fig. 5 schematically shows the use respective pixel circuit region of the 4th step S4 carries out the flow chart of an example of photoetching process operation for the second time.
Specifically, as shown in Figure 5, the light shield of the use respective pixel circuit region of the 4th step S4 carries out photoetching process operation for the second time and can specifically comprise:
Step 1 S100: the interlayer dielectric layer that comprises silica and silicon nitride is carried out to main etching, with etching interlayer dielectric layer, wherein the etch rate of silica and silicon nitride is fast, and the etching selection ratio of silica and silicon nitride is low, for the load effect between balance different pattern size.
Step 2 S200: carry out interlayer dielectric layer over etching, with further etching interlayer dielectric layer, wherein, the etch rate of silica and silicon nitride is less than respectively silica in step 1 S100 and the etch rate of silicon nitride, and wherein silica etch rate is greater than silica etch rate; Silica etch rate is general, and silicon nitride etch speed is extremely slow, for overcoming the spatial distribution load effect of etch rate and the etching inhomogeneities that pattern density load effect causes.
Step 3 S300: carry out and remove photoresist, wherein photoresist ashing is removed.
Step 4 S400: carry out etching barrier layer etching, for opening the etching barrier layer (main component of etching barrier layer is generally silicon nitride) of interlayer dielectric layer etch stages, make contact hole arrive the nickel silicide layer of bottom.Conventionally need silicon nitride etch speed fast, the process conditions that silica etch rate is extremely slow.Preferably, wherein silicon nitride etch speed is greater than silica etch rate, and further preferably, silicon nitride etch speed is at least 2 times of silica etch rate; Still more preferably, silicon nitride etch speed is at least 5 times of silica etch rate.
Step 5 S500: carry out polymer and remove, in order to remove the polymer of the rich carbon fluorine of etching barrier layer etching process applying plasma and silicon nitride formation;
Step 7 S700: carry out etching reprocessing (this step is optional step), remove or etching injury reparation for polymer.
Can find out, the embodiment of the present invention CMOS sensor devices contact hole etching method in, use two light shields to carry out Twi-lithography in order to operation to logical circuit region and image element circuit region, the different layer pile structures of corresponding zones of different carries out the dry carving technology operation of differentiation therebetween, after wet method is removed etch by-products, whole technique finishes.
The present invention can be implemented in 55nm and more advanced cmos image sensor technique.
The present invention, on the basis of traditional logical circuit contact hole etching method, uses the zones of different of the corresponding CMOS sensor devices of two light shields, to tackle the different layers pile structure in logical circuit region and photosensitive circuit region.
Adopt after contact hole etching method of the present invention, the electrical performance of CMOS sensor devices is qualified, show as: the contact resistance of tungsten-nisiloy-silicon structure reaches 50ohm/count, and the contact resistance of tungsten-silicon structure reaches respectively 1000ohm/count(Si-gate) and 400ohm/count(active area).
And say further, the list of references 1,2 of mentioning in background technology does not all relate to concrete contact hole preparation technology, only with " insulating interlayer; be formed on the epitaxial loayer top that comprises gate electrode, gate spacer part and gate metal layer; insulating interlayer comprises: the first contact hole, through insulating interlayer and expose source region; The second contact hole, through insulating interlayer and exposure gate metal; The first contact plug, is formed in the first contact hole and is connected to source region; The second contact plug, is formed in the second contact hole and is connected to gate metal; And metal wire, be formed on the first contact plug and the second contact plug top, source region is electrically connected to gate metal " general description the formation of contact hole.
3 of lists of references have been sketched the contact hole preparation technology (preparation technology is the same with standard logic processing procedure contact hole) of CIS processing procedure, but because its emphasis is not contact hole preparation technology, and CIS processing procedure and film layer structure described in it, all from of the present invention different.
And according to another preferred embodiment of the invention, the present invention also provides a kind of CMOS sensor devices manufacture method, it has adopted according to the CMOS sensor devices contact hole etching method described in the above embodiment of the present invention.
Be understandable that, although the present invention with preferred embodiment disclosure as above, yet above-described embodiment is not in order to limit the present invention.For any those of ordinary skill in the art, do not departing from technical solution of the present invention scope situation, all can utilize the technology contents of above-mentioned announcement to make many possible changes and modification to technical solution of the present invention, or be revised as the equivalent embodiment of equivalent variations.Therefore, every content that does not depart from technical solution of the present invention,, all still belongs in the scope of technical solution of the present invention protection any simple modification made for any of the above embodiments, equivalent variations and modification according to technical spirit of the present invention.
Claims (7)
1. a CMOS sensor devices contact hole etching method, is characterized in that comprising:
First step, is used the light shield of counterlogic circuit region to carry out photoetching process operation for the first time;
Second step, the layer pile structure of counterlogic circuit region carries out dry carving technology operation for the first time;
Third step, cleans for the first time to wafer, to remove etch by-products;
The 4th step, is used the light shield of respective pixel circuit region to carry out photoetching process operation for the second time;
The 5th step, respective pixel circuit region layer pile structure carries out dry carving technology operation for the second time;
The 6th step, cleans for the second time to wafer, to remove etch by-products.
2. CMOS sensor devices contact hole etching method according to claim 1, is characterized in that, wherein in the 4th step, uses the light shield of respective pixel circuit region to carry out photoetching process operation for the second time and comprises:
Step 1: the interlayer dielectric layer that comprises silica and silicon nitride is carried out to main etching, with etching interlayer dielectric layer;
Step 2: carry out interlayer dielectric layer over etching, with further etching interlayer dielectric layer, wherein, the etch rate of silica and silicon nitride is less than respectively silica in step 1 and the etch rate of silicon nitride, and wherein silica etch rate is greater than silica etch rate;
Step 3: carry out and remove photoresist;
Step 4: carry out etching barrier layer etching, for opening the etching barrier layer of interlayer dielectric layer etch stages, make contact hole arrive the nickel silicide layer of bottom;
Step 5: carry out polymer and remove, in order to remove the polymer of the rich carbon fluorine of etching barrier layer etching process applying plasma and silicon nitride formation;
Step 6: carry out silica and remove step, for the silicon oxide layer of etching pixel region Si-gate and active region top.
3. CMOS sensor devices contact hole etching method according to claim 2, it is characterized in that, in the 4th step, using the light shield of respective pixel circuit region to carry out photoetching process operation for the second time also comprises: step 7, carry out etching reprocessing, and for polymer, remove or etching injury reparation.
4. CMOS sensor devices contact hole etching method according to claim 1 and 2, is characterized in that, in second step, a layer pile structure for counterlogic circuit region carries out for the first time dry carving technology operation and comprise:
Step 1: the interlayer dielectric layer that comprises silica and silicon nitride is carried out to main etching, with etching interlayer dielectric layer;
Step 2: carry out interlayer dielectric layer over etching, with further etching interlayer dielectric layer, wherein, the etch rate of silica and silicon nitride is less than respectively silica in step 1 and the etch rate of silicon nitride, and wherein silica etch rate is greater than silica etch rate;
Step 3: carry out and remove photoresist;
Step 4: carry out etching barrier layer etching, for opening the etching barrier layer of interlayer dielectric layer etch stages, make contact hole arrive the nickel silicide layer of bottom.
5. CMOS sensor devices contact hole etching method according to claim 4, it is characterized in that, in second step, a layer pile structure for counterlogic circuit region carries out for the first time dry carving technology operation and also comprises: step 7, carry out etching reprocessing, and for polymer, remove or etching injury reparation.
6. CMOS sensor devices contact hole etching method according to claim 1 and 2, is characterized in that, described CMOS sensor devices contact hole etching method is implemented in the cmos image sensor technique of 55nm.
7. a CMOS sensor devices manufacture method, it has adopted according to the CMOS sensor devices contact hole etching method one of claim 1 to 6 Suo Shu.
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Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20080164499A1 (en) * | 2006-12-29 | 2008-07-10 | Ki-Sik Im | Method of manufacturing cmos image sensor |
| CN103337475A (en) * | 2013-06-27 | 2013-10-02 | 上海华力微电子有限公司 | Double-structure contact hole synchronous-etching technology |
| CN103367235A (en) * | 2012-03-29 | 2013-10-23 | 中芯国际集成电路制造(上海)有限公司 | Contact hole forming method |
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- 2013-11-13 CN CN201310566516.8A patent/CN103560082A/en active Pending
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20080164499A1 (en) * | 2006-12-29 | 2008-07-10 | Ki-Sik Im | Method of manufacturing cmos image sensor |
| CN103367235A (en) * | 2012-03-29 | 2013-10-23 | 中芯国际集成电路制造(上海)有限公司 | Contact hole forming method |
| CN103337475A (en) * | 2013-06-27 | 2013-10-02 | 上海华力微电子有限公司 | Double-structure contact hole synchronous-etching technology |
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