CN103337475A - Double-structure contact hole synchronous-etching technology - Google Patents
Double-structure contact hole synchronous-etching technology Download PDFInfo
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- CN103337475A CN103337475A CN2013102647115A CN201310264711A CN103337475A CN 103337475 A CN103337475 A CN 103337475A CN 2013102647115 A CN2013102647115 A CN 2013102647115A CN 201310264711 A CN201310264711 A CN 201310264711A CN 103337475 A CN103337475 A CN 103337475A
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Abstract
The invention relates to the field of MOS (Metal Oxide Semiconductor) devices, particularly to a double-structure contact hole synchronous-etching technology. The silicon nitride barrier layer in a photosensitive area is removed immediately after a silicon nitride barrier layer is deposited, so that the deposit layer structure of a double-structure contact hole of a CIS (Complementary Metal Oxide Semiconductor Image Sensor) product is changed; the etching selection ratio of an interlayer dielectric layer (insulating dielectric layer) to the barrier layer and a silicone substrate is enlarged in the follow-up etching technology, so that the etching step special for a monox barrier layer at the bottom of the photosensitive area is reduced, the monox loss on STI (Shallow Trench Isolation) of a borderless contact hole in a logic area is reduced while the double-structure contact hole is formed, and the yield of products is improved while the technological reliability and stability are enhanced.
Description
Technical field
The present invention relates to the manufacturing process field of semiconductor MOS device, relate in particular to the synchronous etching technics of a kind of double structure contact hole.
Background technology
At present, the etching of silica contact hole is the critical process in the etching technics, one of its critical technological point is that the aperture is little, etching depth dark (characteristic that namely has high-aspect-ratio), and etching depth changes greatly with pattern (device) surface topography, especially product CIS(CMOS Image Sensor), its high aspect ratio features is more special.
Have photosensitive area (Pixel) and logic area (Logic) on the CIS product simultaneously, this just makes its contact hole manufacturing process and traditional logic or memory chip that a lot of differences are arranged; When preparation CIS product, generally adopt the synchronous etching technics of double structure contact hole, its concrete technological process is as follows:
Fig. 1 is the device architecture schematic diagram of traditional preparation CIS product; As shown in Figure 1, the substrate 1 of the device of preparation CIS product is provided with logic area (logic) 11 and photosensitive area (pixel) 12, and the substrate 1 that is arranged in logic area 11 also is provided with shallow ditch non-intercommunicating cells (STI) 111, nickel silicide layer 112 and first grid structure 113, and the substrate 1 that is positioned at photosensitive area 12 is provided with barrier layer (SOR) 121 and second grid structure 122; Etching stop layer (CESL) 13 covers nickel silicide layer 112, first grid structure 113, shallow ditch non-intercommunicating cells 111, the surface of silica barrier layer 121 and second grid structure 122, high-aspect-ratio dielectric layer (HARP) 14 covers the surface of etching stop layer 13, teos layer (TEOS) 15 covers the surface of high-aspect-ratio dielectric layer (HARP) 14, top layer silica (cap oxide) 16 covers the surface of teos layer (TEOS) 15, bottom anti-reflection layer (BARC) 17 covers the surface of top layer silica (cap oxide) 16, and forms photoresistance pattern 18 in the surface of bottom anti-reflection layer (BARC) 17.
Because photosensitive area 12 is compared with logic area 11, has following difference: do not have metal silicide (being nickel silicide layer 112) on the active area (AA) in (1) photosensitive area 12 and the second grid structure (Gate), but covered one deck silica barrier layer 121, silica barrier layer 121 covers above then is the identical silicon nitride etch barrier layer 13 of logic area 11, and the sedimentary deposit structure more than 13 is identical on the silicon nitride etch barrier layer; (2) in the logic area 11 owing to be provided with fleet plough groove isolation structure 111, make its figure comparatively intensive, and area is less, the highest static random access memory district (SRAM) of the figure integrated level in logic area 11 particularly, for keeping higher pattern density to reduce technology difficulty again, need be set to non-boundary contact hole (borderless contact), be that contact hole bottom major part will contact active area, remainder then can contact on the fleet plough groove isolation structure 111, and lower owing to its pattern density in the photosensitive area 12, generally do not need the design of non-boundary contact hole.
Traditional synchronous etching technics of double structure contact hole generally comprises step: (1) each insulating layer deposition and photoresist coating and development; (2) BARC etching; (3) dielectric insulation layer silica main etching; (4) dielectric insulation layer silica over etching; (5) photoresist ashing is removed; (6) silicon nitride etch barrier etch; (7) photosensitive area bottom silica barrier layer etching.Fig. 2 is the structural representation that traditional synchronous etching technics of double structure contact hole designs, and according to technological design, on the basis of structure shown in Figure 1, passes through above-mentioned processing step successively, can obtain structure as shown in Figure 2.Though above-mentioned processing step (1)-(6) can utilize same light shield, finish the contact hole etching of the different structure in two zones simultaneously, but, when carrying out step (7) photosensitive area bottom silica barrier layer etching technics, can carry out synchronous etching to logic area, and then bring defective workmanship.
Fig. 3 is the structural representation in the traditional synchronous etching technics actual production of double structure contact hole; In the explained hereafter of reality, the thickness of photosensitive area bottom silica reaches 600A, and be the silica of removing this 600A, this etch step must have total silica etching removal amount of 900A, to guarantee enough technology over etching windows, will carry out synchronous etching to the silica among the STI of the non-boundary contact hole of logic area bottom and the silicon oxide layer at contact hole top like this; Namely as shown in Figure 3, the synchronous etching that silica among the STI of the non-boundary contact hole of logic area bottom is carried out, can form the deep hole 19 that reaches 700A～800A deeply at STI, and the degree of depth of this deep hole 19 substantially exceeds the well depth (about 500～600A) that active area (AA) ion injects, the land (junction) that makes contact hole electric current after the tungsten plug is filled can cross the ion injection forms path and causes electric leakage (leakage) with substrate silicon, makes component failure; The silicon oxide layer at the contact hole top of logic area is carried out synchronous etching then can form the excessive ring-type scarf 191 in contact hole top, this excessive ring-type scarf 191 can be when follow-up Ti/TiN barrier deposition, owing to the bombardment of Ar sputter (sputter) becomes bigger, cause the improper connection (contact bridge) after tungsten plug deposition and grinding between the contact hole easily, thereby make component failure.
Current, for fear of the defective of bringing because of the synchronous etching of carrying out on the silica among the STI of the non-boundary contact hole of logic area bottom, general way is to make an amendment from figure composing (layout), avoid using the non-boundary contact hole, and make the size (CD) of logic area contact hole little more a lot of than the size of active area (AA), to guarantee to have enough pattern alignments (overlay) process window, as passing through the active area figure is amplified, to avoid using the non-boundary contact hole, the device integrated level is reduced; Perhaps the contact hole size is dwindled, to avoid using the non-boundary contact hole, so then can increase the contact hole technology difficulty greatly.For example, on the logic chip of 55nm, the size of its active area (AA) is generally 86nm, and normal contact hole is of a size of 85～90nm, its contact hole etching process using photoresist masking process gets final product, but on 55nm CIS chip, if the size constancy of AA, that is for guaranteeing enough process windows, logic area contact hole size need narrow down to about 70nm, this size just can not be finished with simple photoresist mask etching technology, then needs non-setting carbon hardmask etching technics to finish, and its process complexity and cost all increase greatly.
In addition, the defective of bringing for fear of the synchronous etching of silicon oxide layer at the contact hole top of logic area, existing technology mainly is the thickness that increases as the silicon oxide layer of interlayer dielectric layer (ILD), and the cmp time after the filling of increase tungsten plug, to cause the excessive loss of ILD silicon oxide layer, thereby reduce the contact hole top ring-type scarf degree of depth, reduce the influence to subsequent handling, avoid causing the improper connection of contact hole; But this method technology difficulty is bigger, and technological effect neither be very desirable, causes other technological problems easily.
Summary of the invention
The invention discloses the synchronous etching technics of a kind of double structure contact hole, be applied to have the Semiconductor substrate of logic area and photosensitive area, wherein, may further comprise the steps:
The preparation silicon nitride barrier covers the surface of described Semiconductor substrate;
Removal is positioned at the silicon nitride barrier of described photosensitive area top;
Deposition high-aspect-ratio dielectric layer covers the surface of residual silicon nitride barrier layer and Semiconductor substrate exposure;
Continue to deposit successively teos layer, protective layer and bottom anti-reflection layer;
The spin coating photoresist covers the surface of described bottom anti-reflection layer, after exposure, the development, removes unnecessary photoresist, forms photoresistance;
Be after mask carries out etching technics, to remove described photoresistance with described photoresistance;
Continue logic area silicon nitride barrier etching technics, form double structure contact hole device.
The above-mentioned synchronous etching technics of double structure contact hole, wherein, described semiconductor device substrate comprises a silicon base, and the silicon base that is positioned at described logic area is provided with shallow ditch non-intercommunicating cells;
Wherein, the surface that is positioned at the silicon base of described logic area is provided with first grid structure and nickel silicide layer, the surface that is positioned at the silicon base of described photosensitive area is provided with second grid structure and silica barrier layer, and described silica barrier layer covers the surface of described second grid structure and the surface that described silicon base is positioned at described photosensitive area exposure.
The above-mentioned synchronous etching technics of double structure contact hole, wherein, described photoresistance has the double structure contact hole pattern.
The above-mentioned synchronous etching technics of double structure contact hole wherein, constitutes a dielectric insulation layer by high-aspect-ratio dielectric layer and teos layer;
Wherein, be that mask carries out etching technics with described photoresistance, comprising:
Carry out the bottom anti-reflection layer etching technics;
Dielectric insulation layer main etching technology;
Dielectric insulation layer over etching technology.
The above-mentioned synchronous etching technics of double structure contact hole wherein, adopts silica and silicon nitride is selected to carry out described dielectric insulation layer main etching technology than not high gas.
The above-mentioned synchronous etching technics of double structure contact hole wherein, is describedly selected than not high gas to mainly by CF silica and silicon nitride
4, C
4F
8, Ar and O
2The mist of forming.
The above-mentioned synchronous etching technics of double structure contact hole wherein, adopts silica and silicon nitride, silica and silicon nitride is selected to carry out described dielectric insulation layer over etching technology than higher gas.
The above-mentioned synchronous etching technics of double structure contact hole wherein, is describedly selected than higher gas to mainly by C silica and silicon nitride
4F
6, Ar and O
2The mist of forming.
The above-mentioned synchronous etching technics of double structure contact hole wherein, adopts the mist of being made up of CH3F6, Ar and O2 to carry out described logic area silicon nitride barrier etching technics.
The above-mentioned synchronous etching technics of double structure contact hole, wherein, the material of high-aspect-ratio dielectric layer and teos layer is silica.
In sum, owing to adopted technique scheme, the synchronous etching technics of a kind of double structure contact hole of the present invention, behind the deposited silicon nitride barrier layer, remove immediately and be arranged in the photosensitive area silicon nitride barrier, and then changed the sedimentary deposit structure of the double structure contact hole of CIS product, and in follow-up etching technics, increase the relatively etching selection ratio of barrier layer and silicon base of interlayer dielectric layer (insulation dielectric layer), and then reduced separately etch step at photosensitive area bottom silica barrier layer, reach when forming the double structure contact hole, reduce the silica loss of logic area non-boundary contact hole on STI, effectively avoided because logic area non-boundary contact hole, causes the problem of crossing the electric leakage that land that ion injects causes with substrate silicon formation path at tungsten plug fill process after-current in the dark excessively silica loss of STI; Simultaneously, can also effectively avoid the excessive problem of contact hole top ring-type scarf, and then reduced to have improved the yield of reliability of technology and stability and product because the excessive technology risk that causes the improper connection of contact hole of the oblique facet of top ring-type has increased process window.
Description of drawings
Fig. 1 is the device architecture schematic diagram of traditional preparation CIS product;
Fig. 2 is the structural representation that traditional synchronous etching technics of double structure contact hole designs;
Fig. 3 is the structural representation in the traditional synchronous etching technics actual production of double structure contact hole;
Fig. 4-the 11st, the flowage structure schematic diagram of the synchronous etching technics of a kind of double structure contact hole among the embodiment.
Embodiment
Below in conjunction with accompanying drawing the specific embodiment of the present invention is further described:
The application's the synchronous etching technics of double structure contact hole, at first, after a Semiconductor substrate with logic area and photosensitive area is carried out the depositing operation of silicon nitride barrier, carry out photoresist coating, developing process, form photoresistance, expose to the open air out so that be positioned at the silicon nitride barrier of photosensitive area; Secondly, be that mask carries out etching technics with above-mentioned photoresistance, to remove the silicon nitride barrier that exposes, can cause the silica that is arranged in below the photosensitive area silicon nitride barrier to have certain etching loss simultaneously, after photoresistance is removed in ashing, carry out deposition, photoresist coating and the developing process thereof of silicon oxide layer, form first photoresistance with double structure contact hole pattern; Wherein, above-mentioned silicon oxide layer comprises HARP layer, TEOS layer, top layer silica (Cap oxide) and BARC layer from bottom to up in proper order successively.
Then, carry out BARC and be etched to top layer silica (preferred, the material of this top layer silica is silicon oxynitride), in this technology, can cause the certain etching loss of top layer silica; Continue dielectric insulation layer silica main etching technology, namely utilize CF
4/ C
4F
8/ Ar/O
2Etc. combination of gases, etching top layer silica, TEOS layer and/or HARP layer successively, because that above-mentioned combination of gases is selected silica/silicon nitride etch is higher than not, and etching speed is fast, etching homogeneity is good; In addition, when carrying out etching technics, make contact hole bottom from the silicon nitride barrier of logic area top portions of gates 200～300A(such as 200A, 230A, 260A, 290A or 300A equivalence be arranged) silica exist.
Afterwards, adopt C
4F
6/ Ar/O
2Combination of gases, carry out dielectric insulation layer silica over etching technology, finishing the over etching of photosensitive area silica, and because C
4F
6/ Ar/O
2Combination of gases the etch rate of silica and silicon nitride/substrate silicon is selected (more preferred than high, be respectively 12:1 and 20～30:1), make that the etching speed of silicon nitride/substrate silicon is slower, so just can make logic area grid and active area, and the silica on photosensitive area grid and the active area (AA) all is etched totally, and logic area contact hole bottom is parked on the silicon nitride barrier (corresponding, have certain silicon nitride barrier loss), and photosensitive area contact hole bottom is parked on the substrate silicon; Wherein, because the selection of etching than high, makes the loss of substrate silicon less than 50A.
At last, the first above-mentioned photoresistance ashing is removed (preferred, and in same etching reaction chamber, utilize O
2Carry out the ashing removal of photoresist, and remove the etching residual polyalcohol in the contact hole simultaneously) after, CH adopted
3F/O
2Combination of gases such as/Ar are carried out logic area silicon nitride barrier etching technics, and because at CH
3F/O
2In the environment of combination of gases such as/Ar, silicon nitride is selected than high (as 15:1) the etch rate of silica, have the silicon nitride over etching amount of certain (generally greater than 30%), and then make the grid of logic area and the silicon nitride in the AA district remove clean, and the metal silicide that brings loss and formation meeting are less than 100A, and the loss of the substrate silicon in photosensitive area contact hole, grid and active area is less than 120A.
Double structure contact hole through above-mentioned processing step preparation, by omitting the step of removing photosensitive area bottom silica barrier layer, avoided the STI silica of non-boundary contact hole to lose problems such as too much, that contact hole top ring-type scarf is excessive, namely increase (the substrate silicon loss is increased to about 100A from 70A) under the little condition in the loss of photosensitive area contact hole substrate silicon, the STI silica loss of the non-boundary contact hole on the logic area active area (AA) is reduced to less than 100A from about 700A; Simultaneously, can make the contact hole ring-type scarf degree of depth by 400～500A, narrow down to less than 300A, make the semiconductor structure of preparation meet the degree of depth requirement (200～300A) of the contact hole top ring-type scarf of logic chip, and then enlarged process window, increased technology stability.
Embodiment:
Fig. 4-the 11st, the flowage structure schematic diagram of the synchronous etching technics of a kind of double structure contact hole among the embodiment; Shown in Fig. 4-11, the synchronous etching technics of a kind of double structure contact hole of the present invention:
At first, provide a substrate 2 with logic area (logic) 21 and photosensitive area (pixel) 22, this substrate 2 is for the preparation of the CIS product; The substrate 2 that is arranged in logic area 21 also is provided with shallow ditch non-intercommunicating cells (STI) 211, nickel silicide layer 212 and first grid structure 213, and this nickel silicide layer 212 is covered in the logic area not by the upper surface of grid in the surface of the substrate 2 of first grid structure 213 coverings and the first grid structure 213; It is preferred that the substrate 2 that is arranged in photosensitive area 22 is provided with barrier layer (SOR) 221(, the material on this barrier layer 221 is silica) and second grid structure 222, and this barrier layer 221 covers the surface of second grid structure 222 and is arranged in photosensitive area 12 not by the surface of the substrate 2 of second grid structure 222 coverings; Continuing deposition-etch, to stop layer (CESL) 23(preferred, and the material of this etching stop layer 23 is silicon nitride) cover the surface of nickel silicide layer 212, first grid structure 213, shallow ditch non-intercommunicating cells 211 and silica barrier layer 221, form structure as shown in Figure 4.
Secondly, the spin coating photoresist covers the surface of etching stop layer 23, after exposure, the development, remove unnecessary photoresist, forming second photoresistance (this second photoresistance is the top in covering logic district 21 only), and be mask (indicating among the figure) with this second photoresistance, etching is removed the etching stop layer that is arranged in photosensitive area 22, after adopting cineration technics to remove second photoresist, and then the residue etching stop layer 231 of formation 21 tops, only covering logic district as shown in Figure 5; Wherein, in the production technology of reality, when etching formed residue etching stop layer 231, the silica barrier layer 221 in the photosensitive area had certain etching loss.
Then, the surface of deposition high-aspect-ratio dielectric layer (HARP) 24 capping oxidation silicon barrier layers 221 and residue etching stop layer 231, and the depositing operation of teos layer (TEOS) 25, top layer silica (cap oxide) 26 and bottom anti-reflection layer (BARC) 27 is carried out in continuation successively, after the spin coating photoresist covers the surface of bottom anti-reflection layer 27, behind exposure, developing process, remove unnecessary photoresist and form the 3rd photoresistance 28 with doubled via structure plan 29; Wherein, in this processing step, in logic area 21, the thickness of metal silicide (nickel silicide layer 212) is 200-300A(such as 200A, 220A, 240A, 260A, 280A or 300A equivalence), the thickness of silicon nitride barrier (residue etching stop layer 231) is 600A, the thickness of silicon oxide layer (high-aspect-ratio dielectric layer 24 and bottom anti-reflection layer 27 common these silicon oxide layers of formation) is 2700A, and in photosensitive area 22, silica barrier layer 221, high-aspect-ratio dielectric layer 24 and bottom anti-reflection layer 27 three's thickness sums are 3300A, the thickness of top layer silica (cap oxide) 26 is 600A, the thickness of bottom anti-reflection layer (BARC) 27 is 900A, and the thickness of the 3rd photoresistance 28 is 2000A.
Afterwards, adopt 130～170mT(such as 130mT, 150mT or 170mT equivalence) pressure, utilize 1000～1700W(such as 1000W, 1200W, 1500W or 1700W equivalence) the source radio-frequency power, 300～500W(such as 300W, 400W or 500W equivalence) the bias voltage radio-frequency power, in reaction chamber, feed 4～10sccm(such as 4sccm, 6sccm, 8sccm or 10sccm equivalence) C
4F
8, 200～400sccm(such as 200sccm, 280sccm, 360sccm or 400sccm equivalence) CF
4, be under 20 ℃ the condition, to be that mask bottom anti-reflection layer 27 is carried out the etching technics of 50s to the surface of top layer silica (cap oxide) 26 with the 3rd photoresistance 28 in the ESC temperature, form the structure that has residue bottom anti-reflection layer 271 as shown in Figure 7; Wherein, in the etching technics of reality, this etching technics is the position that stops in the top layer silica (cap oxide) 26.
Carry out silica main etching technology, be 20～50mT(such as 20mT, 30mT, 40mT or 50mT equivalence at pressure namely), the source radio-frequency power is 300～700W(such as 300W, 350W, 450W, 550W or 700W equivalence), the bias voltage radio-frequency power is 1300～1700W(such as 1300W, 1400W, 1600W or 1700W equivalence) condition under, in reaction chamber, feed 18～24sccm(such as 18sccm, 20sccm, 22sccm or 24sccm equivalence) C
4F
8, 20～24sccm(such as 20sccm, 23sccm or 24sccm equivalence) O
2, 40～60sccm(such as 40sccm, 50sccm or 60sccm equivalence) CF
4600～800sccm(such as 600sccm, 650sccm, 700sccm, 750sccm or 800sccm equivalence) Ar, and 20 ℃ of ESC temperature are set, continuation is mask with the 3rd photoresistance 28, etching top layer silica (cap oxide) 26, high-aspect-ratio dielectric layer (HARP) 24 and/or teos layer (TEOS) 25, and that this etching technics is 45s; Wherein, in this processing step, the via etch that is arranged in the grid structure top stops at high-aspect-ratio dielectric layer (HARP) 24, via etch above active area then stops in the teos layer (TEOS) 25, and the distance H in logic area between the surface of the bottom of the through hole of first grid structure 213 tops and residue etching stop layer 231 is 200-300A(such as 200A, 240A, 260A, 280A or 300A equivalence), to etch away most of ILD silicon oxide layer, formation has residue top layer silica (cap oxide) 261 as shown in Figure 8, the structure of residue teos layer (TEOS) 251 and residue high-aspect-ratio dielectric layer (HARP) 241.
Proceed silica over etching technology, be 20～40mT(such as 20mT, 30mT or 40mT equivalence at pressure namely), the source radio-frequency power is 300～800W(such as 300W, 450W, 550W, 750W or 800W equivalence), the bias voltage radio-frequency power is 300～700W(such as 300W, 400W, 500W or 700W equivalence) condition under, in reaction chamber, feed 10～14sccm(such as 10sccm, 11sccm, 12sccm or 14sccm equivalence) C
4F
6, 10～15sccm(such as 10sccm, 13sccm or 15sccm equivalence) O
2400～600sccm(such as 400sccm, 450sccm, 500sccm, 550sccm or 600sccm equivalence) Ar, and 20 ℃ of ESC temperature are set, and continuing with the 3rd photoresistance 28 is mask, carry out the etching technics of 90s, with silicon oxide layer residual on the active area of removing logic area 21 and photosensitive area 22 (residue high-aspect-ratio dielectric layer 241 and barrier layer 221), and utilize in the above-mentioned mist silica to the etching high selectivity of silicon nitride, through hole 33 and the contact hole 32 on the active area of first grid structure 213 tops of logic area 21 are rested on the residue etching stop layer 231; Equally, utilize silica to the etching high selectivity of substrate silicon, the through hole 32 of second grid structure 222 tops of photosensitive area 22 and the contact hole 30 on the active area are rested on the substrate silicon 2, and then form the structure that has again etching residue high-aspect-ratio dielectric layer (HARP) 242 and residue barrier layer 223 as shown in Figure 9.
The 3rd photoresistance 28 is carried out cineration technics, be 40～60mT(such as 40mT, 50mT or 60mT equivalence at pressure namely), the source radio-frequency power is 300～500W(such as 300W, 350W, 400W, 450W or 500W equivalence), the bias voltage radio-frequency power is 200～600W(such as 200W, 300W, 500W or 600W equivalence) condition under, in reaction chamber, feed 200～600sccm(such as 200sccm, 400sccm or 600sccm equivalence) O
2400～600sccm(such as 400sccm, 450sccm, 500sccm, 550sccm or 600sccm equivalence) Ar, and 20 ℃ of ESC temperature are set, carry out the etching technics of 60s, to remove all photoresists and BARC layer, and the etch polymers in the contact hole etc., form structure shown in Figure 10.
At last, be 20～30mT(such as 20mT, 25mT or 30mT equivalence at pressure), the source radio-frequency power is 300～700W(such as 300W, 350W, 450W, 650W or 700W equivalence), the bias voltage radio-frequency power is 100～300W(such as 100W, 150W, 200W or 300W equivalence) condition under, in reaction chamber, feed 18～24sccm(such as 18sccm, 20sccm, 22sccm or 24sccm equivalence) CH
3F, 6～8sccm(such as 6sccm, 7sccm or 8sccm equivalence) O
2200～400sccm(such as 200sccm, 250sccm, 300sccm, 350sccm or 400sccm equivalence) Ar, and 20 ℃ of ESC temperature are set, carry out the etching technics of 45s, with the silicon nitride barrier in through hole 33 and the active area contact hole 32 on first grid structure 213 grids in the removal logic area 21; Because in the production technology of reality, at CH
3F/O
2In the environment of combination of gases such as/Ar, silicon nitride is selected than high (as 15:1) the etch rate of silica, have the silicon nitride over etching amount of certain (generally greater than 30%), and then make the grid of logic area and the silicon nitride in the AA district remove clean, but the metal silicide that can bring simultaneously loss (less than 100A), and the substrate silicon in photosensitive area contact hole, grid and active area also has loss (less than 120A), and make the top of contact hole form ring-type scarf (degree of depth is less than 300A), i.e. structure as shown in figure 11.
Preferably, the synchronous etching technics of a kind of double structure contact hole of present embodiment on technology nodes such as 65/55nm or 90nm, can be applicable to technology platforms such as Dry etch.
In sum, owing to adopted technique scheme, the present invention proposes the synchronous etching technics of a kind of double structure contact hole, behind the deposited silicon nitride barrier layer, remove immediately and be arranged in the photosensitive area silicon nitride barrier, and then changed the sedimentary deposit structure of the double structure contact hole of CIS product, and in follow-up etching technics, increase the relatively etching selection ratio of barrier layer and silicon base of interlayer dielectric layer (insulation dielectric layer), and then reduced separately etch step at photosensitive area bottom silica barrier layer, reach when forming the double structure contact hole, reduce the silica loss of logic area non-boundary contact hole on STI, effectively avoided because logic area non-boundary contact hole, causes the problem of crossing the electric leakage that land that ion injects causes with substrate silicon formation path at tungsten plug fill process after-current in the dark excessively silica loss of STI; Simultaneously, can also effectively avoid the excessive problem of contact hole top ring-type scarf, and then reduced to have improved the yield of reliability of technology and stability and product because the excessive technology risk that causes the improper connection of contact hole of the oblique facet of top ring-type has increased process window.
By explanation and accompanying drawing, provided the exemplary embodiments of the ad hoc structure of embodiment, based on spirit of the present invention, also can do other conversion.Although foregoing invention has proposed existing preferred embodiment, yet these contents are not as limitation.
For a person skilled in the art, read above-mentioned explanation after, various changes and modifications undoubtedly will be apparent.Therefore, appending claims should be regarded whole variations and the correction of containing true intention of the present invention and scope as.Any and all scope of equal value and contents all should be thought still to belong in the intent of the present invention and the scope in claims scope.
Claims (10)
1. the synchronous etching technics of double structure contact hole is applied to have the Semiconductor substrate of logic area and photosensitive area, it is characterized in that, may further comprise the steps:
The preparation silicon nitride barrier covers the surface of described Semiconductor substrate;
Removal is positioned at the silicon nitride barrier of described photosensitive area top;
Deposition high-aspect-ratio dielectric layer covers the surface of residual silicon nitride barrier layer and Semiconductor substrate exposure;
Continue to deposit successively teos layer, protective layer and bottom anti-reflection layer;
The spin coating photoresist covers the surface of described bottom anti-reflection layer, after exposure, the development, removes unnecessary photoresist, forms photoresistance;
Be after mask carries out etching technics, to remove described photoresistance with described photoresistance;
Continue logic area silicon nitride barrier etching technics, form double structure contact hole device.
2. the synchronous etching technics of double structure contact hole according to claim 1 is characterized in that, described semiconductor device substrate comprises a lining substrate, and the silicon base that is positioned at described logic area is provided with shallow ditch non-intercommunicating cells;
Wherein, the surface that is positioned at the silicon base of described logic area is provided with first grid structure and nickel silicide layer, the surface that is positioned at the silicon base of described photosensitive area is provided with second grid structure and silica barrier layer, and described silica barrier layer covers the surface of described second grid structure and the surface that described silicon base is positioned at described photosensitive area exposure.
3. the synchronous etching technics of double structure contact hole according to claim 1 is characterized in that described photoresistance has the double structure contact hole pattern.
4. the synchronous etching technics of double structure contact hole according to claim 3 is characterized in that, constitutes a dielectric insulation layer by high-aspect-ratio dielectric layer and teos layer;
Wherein, be that mask carries out etching technics with described photoresistance, comprising:
Carry out the bottom anti-reflection layer etching technics;
Dielectric insulation layer main etching technology;
Dielectric insulation layer over etching technology.
5. the synchronous etching technics of double structure contact hole according to claim 4 is characterized in that, adopts silica and silicon nitride are selected to carry out described dielectric insulation layer main etching technology than not high gas.
6. the synchronous etching technics of double structure contact hole according to claim 5 is characterized in that, described silica and silicon nitride is selected than not high gas to mainly by CF
4, C
4F
8, Ar and O
2The mist of forming.
7. the synchronous etching technics of double structure contact hole according to claim 4 is characterized in that, adopts silica and silicon nitride, silica and silicon nitride are selected to carry out described dielectric insulation layer over etching technology than higher gas.
8. the synchronous etching technics of double structure contact hole according to claim 7 is characterized in that, described silica and silicon nitride is selected than higher gas to mainly by C
4F
6, Ar and O
2The mist of forming.
9. the synchronous etching technics of double structure contact hole according to claim 1 is characterized in that, adopts the mist of being made up of CH3F6, Ar and O2 to carry out described logic area silicon nitride barrier etching technics.
10. the synchronous etching technics of double structure contact hole according to claim 1 is characterized in that the material of high-aspect-ratio dielectric layer and teos layer is silica.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201310264711.5A CN103337475B (en) | 2013-06-27 | 2013-06-27 | The synchronous etching technics of double structure contact hole |
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| CN103560137A (en) * | 2013-11-13 | 2014-02-05 | 上海华力微电子有限公司 | CMOS complementary metal oxide semiconductor contact hole etching method and CMOS complementary metal oxide semiconductor manufacturing method |
| CN103560082A (en) * | 2013-11-13 | 2014-02-05 | 上海华力微电子有限公司 | CMOS complementary metal oxide semiconductor contact hole etching method and CMOS complementary metal oxide semiconductor manufacturing method |
| CN103633106A (en) * | 2013-11-28 | 2014-03-12 | 上海华力微电子有限公司 | CMOS (complementary metal oxide semiconductor) contact hole etching method and CMOS manufacturing method |
| CN105742237A (en) * | 2016-02-26 | 2016-07-06 | 上海华力微电子有限公司 | Synchronous etching process of dual-structure contact hole |
| WO2017185921A1 (en) * | 2016-04-26 | 2017-11-02 | 京东方科技集团股份有限公司 | Via hole forming method, array substrate and forming method therefor, and display device |
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| CN107665856A (en) * | 2016-07-29 | 2018-02-06 | 中微半导体设备(上海)有限公司 | For forming the method and method for etching plasma of contact hole |
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| CN108538871A (en) * | 2018-03-16 | 2018-09-14 | 德淮半导体有限公司 | The forming method and imaging sensor of contact hole |
| CN109904072A (en) * | 2017-12-07 | 2019-06-18 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor devices and forming method thereof |
| CN111261636A (en) * | 2020-01-21 | 2020-06-09 | 长江存储科技有限责任公司 | Contact groove forming method and semiconductor |
| CN111653476A (en) * | 2020-05-13 | 2020-09-11 | 上海华虹宏力半导体制造有限公司 | Etching method and structure of contact hole |
| CN113284808A (en) * | 2021-07-22 | 2021-08-20 | 江苏茂硕新材料科技有限公司 | Preparation method of semiconductor structure |
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| CN103560082A (en) * | 2013-11-13 | 2014-02-05 | 上海华力微电子有限公司 | CMOS complementary metal oxide semiconductor contact hole etching method and CMOS complementary metal oxide semiconductor manufacturing method |
| CN103560137A (en) * | 2013-11-13 | 2014-02-05 | 上海华力微电子有限公司 | CMOS complementary metal oxide semiconductor contact hole etching method and CMOS complementary metal oxide semiconductor manufacturing method |
| CN103633106A (en) * | 2013-11-28 | 2014-03-12 | 上海华力微电子有限公司 | CMOS (complementary metal oxide semiconductor) contact hole etching method and CMOS manufacturing method |
| CN103633106B (en) * | 2013-11-28 | 2016-06-29 | 上海华力微电子有限公司 | CMOS contact hole etching method and CMOS manufacture method |
| CN105742237B (en) * | 2016-02-26 | 2019-01-18 | 上海华力微电子有限公司 | Double structure contact hole synchronizes etching technics |
| CN105742237A (en) * | 2016-02-26 | 2016-07-06 | 上海华力微电子有限公司 | Synchronous etching process of dual-structure contact hole |
| WO2017185921A1 (en) * | 2016-04-26 | 2017-11-02 | 京东方科技集团股份有限公司 | Via hole forming method, array substrate and forming method therefor, and display device |
| US10204802B2 (en) | 2016-04-26 | 2019-02-12 | Boe Technology Group Co., Ltd. | Method of forming via hole, array substrate and method of forming the same and display device |
| CN107546118A (en) * | 2016-06-29 | 2018-01-05 | 中芯国际集成电路制造(北京)有限公司 | A kind of cmos image sensor and preparation method thereof and electronic installation |
| CN107546118B (en) * | 2016-06-29 | 2020-05-22 | 中芯国际集成电路制造(北京)有限公司 | CMOS image sensor, preparation method thereof and electronic device |
| CN107665856A (en) * | 2016-07-29 | 2018-02-06 | 中微半导体设备(上海)有限公司 | For forming the method and method for etching plasma of contact hole |
| CN107665856B (en) * | 2016-07-29 | 2020-04-03 | 中微半导体设备(上海)股份有限公司 | Method for forming contact hole and plasma etching method |
| CN108511342B (en) * | 2017-02-24 | 2021-05-14 | 中芯国际集成电路制造(上海)有限公司 | Method for manufacturing semiconductor device |
| CN108511342A (en) * | 2017-02-24 | 2018-09-07 | 中芯国际集成电路制造(上海)有限公司 | The preparation method of semiconductor devices |
| CN109904072A (en) * | 2017-12-07 | 2019-06-18 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor devices and forming method thereof |
| CN109904072B (en) * | 2017-12-07 | 2022-04-15 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor device and method of forming the same |
| CN108538871A (en) * | 2018-03-16 | 2018-09-14 | 德淮半导体有限公司 | The forming method and imaging sensor of contact hole |
| CN111261636A (en) * | 2020-01-21 | 2020-06-09 | 长江存储科技有限责任公司 | Contact groove forming method and semiconductor |
| CN111261636B (en) * | 2020-01-21 | 2021-07-20 | 长江存储科技有限责任公司 | Contact groove forming method and semiconductor |
| CN111653476A (en) * | 2020-05-13 | 2020-09-11 | 上海华虹宏力半导体制造有限公司 | Etching method and structure of contact hole |
| CN113284808A (en) * | 2021-07-22 | 2021-08-20 | 江苏茂硕新材料科技有限公司 | Preparation method of semiconductor structure |
| CN113284808B (en) * | 2021-07-22 | 2021-10-15 | 江苏茂硕新材料科技有限公司 | Preparation method of semiconductor structure |
| CN113838881A (en) * | 2021-11-26 | 2021-12-24 | 晶芯成(北京)科技有限公司 | Image sensor and method for manufacturing the same |
| CN113838881B (en) * | 2021-11-26 | 2022-02-08 | 晶芯成(北京)科技有限公司 | Image sensor and method for manufacturing the same |
| CN115148666A (en) * | 2022-09-02 | 2022-10-04 | 合肥晶合集成电路股份有限公司 | Method for manufacturing semiconductor device |
| CN116936469A (en) * | 2023-09-14 | 2023-10-24 | 深圳基本半导体有限公司 | Method for manufacturing semiconductor device |
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