CN103311210A - 用于组装半导体器件的引线框 - Google Patents

用于组装半导体器件的引线框 Download PDF

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CN103311210A
CN103311210A CN201210057325.4A CN201210057325A CN103311210A CN 103311210 A CN103311210 A CN 103311210A CN 201210057325 A CN201210057325 A CN 201210057325A CN 103311210 A CN103311210 A CN 103311210A
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conductive support
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lead frame
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CN103311210B (zh
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邱书楠
白志刚
刘海燕
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NXP USA Inc
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Freescale Semiconductor Inc
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    • H01L2224/42Wire connectors; Manufacturing methods related thereto
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Abstract

本发明提供一种用于组装半导体器件的引线框。引线框具有标记、外周框、将标记耦合至外周框的主连接条。至少一个交叉连接条在所述主连接条中的两个主连接条之间延伸,并且外部连接器焊盘的内部排从交叉连接条内侧延伸,且外部连接器焊盘的外部排从交叉连接条外侧延伸。内部非导电性支撑条和外部非导电性支撑条两者都跨过所述两个主连接条而附接。内部非导电性支撑条被附接到所述两个主连接条的上表面,并且被附接到外部连接器焊盘的内部排的上表面。

Description

用于组装半导体器件的引线框
技术领域
本发明涉及一种用于封装半导体管芯的引线框,且更具体地,涉及一种用于组装具有大数量的外部连接器焊盘的半导体器件的引线框和方法。
背景技术
半导体芯片封装的一个典型的类型是四方扁平封装(QFP),其通过安装到引线框的半导体管芯来进行组装。引线框由具有通常被叫作标记(flag)的管芯附接焊盘的金属片和将标记附接到外框的连接条(tie bar)形成。引线框上的外部连接器焊盘,有时被称为引线指,其被丝线键合到管芯的焊盘或电极,以提供将管芯电连接到电路板等的方式。在电极和外部连接器焊盘被丝线键合之后,将半导体管芯和外部连接器焊盘密封在诸如塑性材料的模制化合物中,形成半导体芯片封装,其一般只露出外部连接器焊盘的底侧和外框。然后从外框切割半导体芯片封装(单体化)。
不幸的是,用于扁平封装和QFP封装的引线框的固有结构限制了可以用于特定封装尺寸的外部连接器焊盘的数量。这种限制会与半导体技术中每十八个月左右使得半导体芯片的功能复杂性增加一倍的总体趋势相冲突。因此,如果引线框和半导体芯片封装可以提供增加的外部连接器焊盘数,则会是有益的。
附图说明
参考下面结合附图对优选实施例的描述,本发明及其目的和优点都将被更好地理解,附图中:
图1是根据本发明优选实施例的引线框的顶视平面图;
图2是通过图1的2-2’的截面图;
图3是图1的引线框在将支撑条附接到引线框之后的顶视平面图;
图4是通过图3的4-4’的截面图;
图5是图3的引线框在移除了交叉连接条之后的顶视平面图;
图6是通过图5的6-6’的截面图;
图7是图5的引线框在将半导体管芯安装并电连接到引线框之后的顶视平面图;
图8是通过图7的8-8’的截面图;
图9是图7的引线框在密封半导体管芯以形成已经从引线框的外周框切割了的半导体芯片封装之后的顶视平面图;
图10是通过图9的10-10’的截面图;
图11是根据本发明另一个优选实施例、图1的引线框在将支撑条附接到引线框之后的顶视平面图;
图12是通过图11的12-12’的截面图;以及
图13是图示出用于组装图9的半导体芯片封装的方法的流程图。
具体实施方式
以下结合附图所提出的详细说明是旨在作为对本发明目前优选实施例的说明,而不是意图表现仅有的可以实践本发明的形式。要理解的是,可以通过意图被囊括在本发明的精神和范围之内的不同的实施例来实现相同或等同的功能。附图中,相同的附图标记始终表示相同的元件。此外,术语“包括”、“包含”或其任何其他变形,都旨在涵盖非排他性的包括,使得包括一系列元件或步骤的模块、电路、装置组件、结构和方法步骤不仅包括那些元件而且还可以包括未明确列入的或者这样的模块、电路、装置组件或步骤本身所固有的其他元件或步骤。在没有更多限制的情况下,通过“包括……”引导的元件或步骤,不排除存在包括该元件或步骤的额外的相同的元件或步骤。
在一个实施例中,本发明提供一种用于组装半导体器件的方法,该方法包括:提供引线框,所述引线框具有标记、外周框、将标记耦合至外周框的主连接条;在所述主连接条中的两个主连接条之间延伸至少一个交叉连接条;以及从交叉连接条内侧延伸外部连接器焊盘的内部排、从交叉连接条外侧延伸外部连接器焊盘的外部排。该方法包括:跨过上述两个主连接条而附接内部非导电性支撑条和外部非导电性支撑条这两者。所述内部非导电性支撑条被附接到所述两个主连接条的上表面并与之邻接,并且也被附接到外部连接器焊盘的内部排的上表面并与之邻接。
外部非导电性支撑条被附接到上述两个主连接条的上表面并与之邻接,并且也被附接到所述外部连接器焊盘的外部排的上表面并与之邻接。上述方法包括:移除交叉连接条,使得外部连接器焊盘的内部排由内部非导电性支撑条支撑,并且外部连接器焊盘的外部排由外部非导电性支撑条支撑。然后执行将半导体管芯安装到标记,之后,将半导体管芯上的焊盘电连接到外部连接器焊盘的内部排上的相应的焊盘,和外部连接器焊盘的外部排上的相应的焊盘。然后密封半导体管芯,并且分离外周框,以形成完成的封装。
在另一个实施例中,本发明提供一种引线框,该引线框具有外周框、标记、主连接条、以及内部非导电性支撑条,其中,所述主连接条将标记耦合至外周框,所述内部非导电性支撑条跨过所述主连接条中的两个主连接条而延伸,并且支撑外部连接器焊盘的内部排。外部非导电性支撑条跨过所述两个主连接条而延伸,并且支撑外部连接器焊盘的外部排。
在又一个实施例中,本发明提供一种具有引线框的半导体器件,所述引线框具有外周框、标记、主连接条、内部非导电性支撑条,其中,所述主连接条将标记耦合至外周框,所述内部非导电性支撑条跨过所述主连接条中的两个主连接条而延伸,并且支撑外部连接器焊盘的内部排。外部非导电性支撑条跨过所述两个主连接条而延伸,并支撑外部连接器焊盘的外部排。半导体管芯被安装到上述标记。所述半导体管芯具有被电连接到外部连接器焊盘的内部排和外部排上的相应焊盘的焊盘,并且密封体覆盖所述半导体管芯。
现在参照图1,图示出根据本发明优选实施例的引线框100的顶视平面图。引线框100具有标记101、外周框102和将标记101耦合至外周框102的主连接条103。交叉连接条104在相应的主连接条103对之间延伸,并且外部连接器焊盘的内部排105从交叉连接条104的内侧延伸。还存在外部连接器焊盘的外部排106,其从交叉连接条104的外侧延伸。如图1所示,外部连接器焊盘的内部排105中每一个的焊盘与外部连接器焊盘的外部排106中的相应的焊盘对准。然而,在一些实施例中,外部连接器焊盘的内部排105中的每个焊盘相对于外部连接器焊盘的外部排106中的焊盘交错布置。引线框100具有外部连接器焊盘的外周排107,其从外周框102延伸,并且外部连接器焊盘的外周排107中的焊盘相对于外部连接器焊盘的外部排106中的焊盘交错布置。
提供图2,以从侧截面图图示出引线框100。图3中,示出了引线框100在执行了将支撑条附接到引线框100的工艺之后的顶视平面图。该工艺包括使内部非导电性支撑条301和外部非导电性支撑条302两者跨过主连接条103的相应对而附接。就这点而言,将内部非导电性支撑条301附接到主连接条103的上表面并与之邻接,并且同样地,其也被附接到外部连接器焊盘的内部排105的上表面并与之邻接。此外,将外部非导电性支撑条302附接到两个主连接条的上表面并与之邻接,并且其也被附接到外部连接器焊盘的外部排106的上表面并与之邻接。
每个内部非导电性支撑条301和每个外部非导电性支撑条302向引线框100提供额外的或者三重支撑,如稍后将描述的。然而,为了提供更进一步的支撑,该工艺包括将主非导电性支撑条303附接在主连接条103中的每个上。如图所示,非导电性支撑条303高于支撑条301、302,但在另外一些实施例中不必如此。上述附接也可能可以包括将每个内部非导电性支撑条301附接到标记101的上表面。这将向引线框100提供额外的支撑,因为内部非导电性支撑条301的下表面将与标记101的上表面邻接。但是,如果标记的表面积足够大而容纳这样的附接,则该特征是最有用的。对于本领域技术人员而言将显而易见的是,上述附接可以进一步包括将每个外部非导电性支撑条302附接到外周框102的上表面,但这又要取决于空间可利用性。
在本实施例中,附接工艺一般通过每个内部非导电性支撑条301、每个外部非导电性支撑条301和每个主非导电性支撑条303的注射模制来执行。
提供图4,以在执行完附接之后从侧截面视图图示出引线框100。图5中示出了引线框100在移除了引线框100的交叉连接条104之后的顶视平面图。移除交叉连接条104的工艺一般通过切割或冲压槽504来执行,并且导致每个外部连接器焊盘的内部排105都由一个内部非导电性支撑条301支撑。同样,该工艺也导致每个外部连接器焊盘的外部排106都由一个外部非导电性支撑条302支撑。在本实施例中,每个外部连接器焊盘的内部排105和每个外部连接器焊盘的外部排106进一步由两个主非导电性支撑条303支撑。
提供图6,以在执行完移除工艺之后从侧截面视图图示出引线框100。图7中,示出了引线框100在将半导体管芯701安装并电连接到引线框100之后的顶视平面图。在该工艺中,将半导体管芯701安装到标记101。然后执行的是将半导体管芯701上的焊盘702(电极)电连接到外部连接器焊盘的内部排105上的相应的焊盘和外部连接器焊盘的外部排106上的相应的焊盘。上述电连接一般利用键合丝线703,通过丝线键合工艺来执行,并且包括将半导体管芯701上的焊盘702电连接到外部连接器焊盘的外周排107中的相应的焊盘。
提供图8,以在执行完安装和电连接的工艺之后从侧截面视图图示出引线框100。图9中示出了在密封半导体管芯701以提供已从外周框102分离或者切断的半导体器件900之后的引线框100。上述密封通常通过在引线框100顶部之上注射模制塑性材料901来执行。当从下面看或者如图10所示从侧截面视图看时,可以看见半导体器件900为QFP封装。
图11中示出了根据本发明另一个优选实施例的在将支撑条附接到引线框100之后的引线框100的顶视平面图。引线框100的大多数特征都与上面的相同,因此为了避免重复将仅描述不同之处。在本实施例中,跨过主连接条103相应的对来附接内部非导电性支撑条301,并且内部非导电性支撑条301的下表面邻接标记101的上表面。每个主连接条103上的每个主非导电性支撑条1103不沿着其相应的下面的条103的全长延伸。如图所示,非导电性支撑条303高于支撑条301、302,但在其他一些实施例中不必如此。
如上述实施例中所述,附接工艺一般通过每个内部非导电性支撑条1101、每个外部非导电性支撑条302和每个主非导电性支撑条1103的注射模制来执行。
图12图示出在执行完附接工艺之后从侧截面观看的图11的引线框。如果在引线框100上执行附接每个内部非导电性支撑条1101和每个主非导电性支撑条1103的工艺,则最后将会得到类似于半导体器件900的半导体芯片封装。
将参照图13描述用于组装半导体器件900或者类似的封装型器件的方法130的概要。在步骤1310,方法1300一般将引线框100提供到模制台,并且在步骤1320通过注射模制来执行对支撑条301、302、303的附接。一旦支撑条301、302、303冷却变硬,就将引线框100移至冲压机,并且在步骤1330通过冲压工艺移除交叉连接条104。一旦交叉连接条104被移除,支撑条301、302、303就支撑并维持引线框100的结构完整性,从而支撑引线框100上的连接器焊盘105、106。在步骤1340,将引线框100移至安装台,并且通过常规工艺(例如,用管芯附接粘合剂)将半导体管芯701安装或者附接到标记101。然后在步骤1350,在丝线键合台处将半导体管芯701上的焊盘702电连接到相应的焊盘105、106和107。然后在步骤1360,将引线框100移至另一个模制台,在这里,方法1300执行密封半导体管芯701的工艺,以提供半导体器件900。因为引线框100是较大一片相同框体的一部分,所以在步骤1370,例如用已知的单体化工艺将外周框102与器件900分离。
有利的是,本发明可以允许提供增加外部连接器焊盘数的经济方式,尤其是对于扁平封装和QFP封装而言。这是因为连接器焊盘105、106和支撑条301、302、303的组合允许相对较大的焊盘数,而不影响引线框的结构完整性。因而,在将半导体管芯701安装到标记101之后,丝线键合、密封和切断(单体化)相对较为简单直接。
出于例示和说明的目的,已展开了对本发明优选实施例的描述,但并非意图穷尽本发明的形式,或者将本发明限制到所公开的形式。本领域技术人员将要理解的是,在不脱离上述实施例的广泛发明构思的情况下可以对这些实施例做出各种改变。因此,应了解的是,本发明不限于所公开的具体实施利,而是涵盖了如随附的权利要求书所界定的本发明的精神和范围内的各种修改。

Claims (10)

1.一种引线框,包括:
外周框;
标记;
多个主连接条,所述多个主连接条将所述标记耦合至所述外周框;
内部非导电性支撑条,所述内部非导电性支撑条跨过所述主连接条中的至少两个主连接条而延伸,并且支撑外部连接器焊盘的内部排;和
外部非导电性支撑条,所述外部非导电性支撑条跨过所述至少两个主连接条而延伸,并且支撑外部连接器焊盘的外部排。
2.如权利要求1所述的引线框,其中,所述外部连接器焊盘的内部排具有被安装到所述内部非导电性支撑条的上表面,并且所述外部连接器焊盘的外部排具有被安装到所述外部非导电性支撑条的上表面。
3.如权利要求2所述的引线框,其中,所述内部非导电性支撑条位于所述标记和所述外部连接器焊盘的内部排之间,并且其中,所述内部非导电性支撑条被附接到所述标记的上表面并与所述标记的上表面邻接。
4.如权利要求3所述的引线框,其中,所述内部非导电性支撑条位于所述标记和外部连接器焊盘的内部排之间。
5.如权利要求3所述的引线框,其中,所述外部非导电性支撑条位于所述外周框和外部连接器焊盘的外部排之间。
6.如权利要求3所述的引线框,其中,外部连接器焊盘的外周排从所述外周框延伸。
7.一种半导体器件,包括:
引线框,所述引线框具有外周框、标记、主连接条、内部非导电性支撑条和外部非导电性支撑条,其中,所述主连接条将所述标记耦合至所述外周框,所述内部非导电性支撑条跨过所述主连接条中的两个主连接条而延伸并支撑外部连接器焊盘的内部排,并且所述外部非导电性支撑条跨过所述两个主连接条而延伸并支撑外部连接器焊盘的外部排;
被安装到所述标记的半导体管芯,所述半导体管芯具有电连接到所述外部连接器焊盘的内部排和所述外部连接器焊盘的外部排上的相应焊盘的焊盘;和
密封所述半导体管芯的密封体。
8.如权利要求7所述的半导体器件,其中,所述外部连接器焊盘的内部排具有被安装到所述内部非导电性支撑条的上表面,并且所述外部连接器焊盘的外部排具有被安装到所述外部非导电性支撑条的上表面。
9.如权利要求7所述的半导体器件,其中,所述内部非导电性支撑条位于所述标记和外部连接器焊盘的内部排之间。
10.如权利要求7所述的半导体器件,其中,所述外部非导电性支撑条位于所述外周框和外部连接器焊盘的外部排之间,并且其中,外部连接器焊盘的外周排从所述外周框延伸。
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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN111370382A (zh) * 2018-12-25 2020-07-03 恩智浦美国有限公司 用于具有改进的爬电距离的半导体管芯封装的混合引线框架

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9425139B2 (en) * 2012-09-12 2016-08-23 Marvell World Trade Ltd. Dual row quad flat no-lead semiconductor package
US10770377B2 (en) 2018-12-31 2020-09-08 Texas Instruments Incorporated Leadframe die pad with partially-etched groove between through-hole slots

Family Cites Families (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5258331A (en) * 1989-10-20 1993-11-02 Texas Instruments Incorporated Method of manufacturing resin-encapsulated semiconductor device package using photoresist or pre-peg lead frame dam bars
US5270262A (en) * 1991-02-28 1993-12-14 National Semiconductor Corporation O-ring package
JPH0595079A (ja) * 1991-10-02 1993-04-16 Ibiden Co Ltd リードフレーム、半導体集積回路搭載用基板及び半導体装置並びにそれらの製造方法
US5422313A (en) * 1994-05-03 1995-06-06 Texas Instruments Incorporated Integrated circuit device and manufacturing method using photoresist lead covering
TW351008B (en) * 1996-12-24 1999-01-21 Matsushita Electronics Corp Lead holder, manufacturing method of lead holder, semiconductor and manufacturing method of semiconductor
JP3444410B2 (ja) * 2000-03-23 2003-09-08 株式会社三井ハイテック リードフレームおよび半導体装置の製造方法
SG120858A1 (en) 2001-08-06 2006-04-26 Micron Technology Inc Quad flat no-lead (qfn) grid array package, methodof making and memory module and computer system including same
US6838751B2 (en) * 2002-03-06 2005-01-04 Freescale Semiconductor Inc. Multi-row leadframe
US6818973B1 (en) * 2002-09-09 2004-11-16 Amkor Technology, Inc. Exposed lead QFP package fabricated through the use of a partial saw process
JP3851264B2 (ja) * 2002-12-17 2006-11-29 株式会社巴川製紙所 リードフレームおよびリードフレーム固定テープの接着強度測定方法
KR100568225B1 (ko) * 2003-11-06 2006-04-07 삼성전자주식회사 리드 프레임 및 이를 적용한 반도체 패키지 제조방법
US7598606B2 (en) 2005-02-22 2009-10-06 Stats Chippac Ltd. Integrated circuit package system with die and package combination
CN102354691B (zh) * 2011-11-04 2013-11-06 北京工业大学 一种高密度四边扁平无引脚封装及制造方法

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN111370382A (zh) * 2018-12-25 2020-07-03 恩智浦美国有限公司 用于具有改进的爬电距离的半导体管芯封装的混合引线框架

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