CN103309837A - Interface board card of CPCI (Compact Peripheral Component Interconnect) framework based on MIL-STD-1553B - Google Patents
Interface board card of CPCI (Compact Peripheral Component Interconnect) framework based on MIL-STD-1553B Download PDFInfo
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Abstract
The invention relates to a computer board card of a CPCI (Compact Peripheral Component Interconnect) framework, in particular to a standard bus interface module based on a MIL-STD-1553B protocol, namely, a plane internal time-division system command/response multipath transmission data bus interface module, which is widely applied to plane comprehensive avionics systems and external store management and integration systems, and gradually expands to plane control systems and the like as well as the fields of tanks, ships, spaceflight and the like. The MIL-STD-1553B protocol is realized through an FPGA (Field Programmable Gata Array); coding and decoding of a Manchester code are realized by using a VHDL (Hardware Description Language); a reasonable small-sized bus driving circuit is designed according to the MIL-STD-1553B protocol; a DSP (Digital Signal Processor) program which can support the protocol is written, and an assembled interface assembly function is realized. Due to the adoption of the interface board card, the design requirement of small size is met, functional expansion can be performed easily as required, using flexibility is realized, and the development cost of a product is much lower than that of a foreign special interface chip.
Description
Affiliated technical field
The present invention relates to the computer card of a kind of compact interface (CPCI) framework, be based on MIL-STD-1553B consensus standard bus interface module, it is interior of aircraft time-devision system instruction/response type multiplex data bus interface module, be widely used in airplane synthetic avionics system, plug-in property management reason and integrated system, and progressively expand to fields such as flight system such as control and tank, naval vessel, space flight.
Background technology
1553B bus standard full name MIL_STD_1553B (hereinafter to be referred as 1553), it started from the beginning of nineteen sixty-eight, on September 21st, 1978, after obtaining formal written authorization, delivered as the file announcement of U.S. official.One of basis of this standard and standardized management integrated as U.S. Department of Defense's armament systems is widely used in airplane synthetic avionics system, plug-in property management reason and integrated system, and progressively expands to fields such as system such as flight control and tank, naval vessel, space flight.It is used for airplane avionics system by USAF at first, has been widely used in the US and European sea, land and sky army at present, and has become a kind of international standard.There are many countries to quote this standard in the world, the standard of also having formulated corresponding this country that has (China is GJB289A-97).
The 1553B bus standard is formulated by US military.Support the protocol chip of this standard that the BU-6517X of DDC company, BU-615XX series are arranged; The HI-61XX series of HOLT company; The BCRTM of UTMC company etc.These chips are all integrated BC, RT, the function of BM, but these chips are all produced by u s company, and price is very expensive, the supply channel instability.For using the extraordinary data bus of this reliability at low cost, employing FPGA designs and Implements the data link layer protocol of remote endpoint, becomes a kind of demand of reality; Can better lay the first stone for practical application by the realization to the 1553B agreement, for the 1553B bus expands to 4M, 10M and even higher rate provides foundation; Provide technical possibility for realizing that the 1553B bus reduces cost.
The present invention adopts the C3 Series FPGA of ALTERA, realizes the agreement of 1553B substantially, can be in general the application the outer chip of subrogate country, if employing military products FPGA, by the experimental verification of strictness, can substituting import one military products chip; This problem has now realized the multi-functional task agreement of single-chip; And then the upgrading expansion of realization protocol bus speed, extend to 4M, 10M.
Summary of the invention
The present invention's " based on interface integrated circuit board of the CPCI framework of MIL-STD-1553B bus " realizes that with soft, the hardware of each subsystem of weapon bus is connected according to the MIL-STD-1553B consensus standard by the form with the compact peripheral component interconnect, by sharing of information and resource, according to the Operation Target of weapon, real realization function is comprehensive on application layer.
The present invention expands the development platform of realizing setting up based on consensus standard buses such as ARINC429/629, CAN, ARINC664/AFDX, MIC, 1394, FC optical fiber, for Aeronautics and Astronautics and relevant military and civilian field provide high bandwidth communication, high-speed data, high-speed data storage, high image resolution solution, be widely used in the electronic apparatus system of bus system such as Aeronautics and Astronautics, naval vessel, guided missile, panzer, tank and civil area.
The subject matter that the present invention will solve is: realize the MIL-STD-1553B agreement by FPGA; Realize the Manchester code coding and decoding with the VHDL hardware description language; Adopt MAX+PLUS II to carry out sequential emulation; According to the MIL-STD-1553B agreement, miniaturization bus driving circuits reasonable in design; Write the DSP program curing, can reach supported protocol, finish modularization interface module function.
Solution of the present invention is: the 1553B bus is interior of aircraft time-devision system instruction/response type multiplex data bus.It carries out data transmission with the maskable twisted-pair feeder, and signal is to transmit with the form of serial digital pulse, and its data code represents that with the form of two-phase Man Chete sign indicating number its transfer rate is 1Mb/s.Be connected with three types system on the 1553B data bus: 1. bus controller (BC)---the data transmission on the control bus; 2. data transmission is carried out in remote terminal controller (RT)---the order that response BC comes; 3. bus monitor (BM)---receive the information on the data bus selectively and preserve it.Each subsystem can be connected to any one subsystem by the 1553B bus.Data are transmitted in bus.
What bus was transmitted three types word arranged: command word, status word and data word.The word length of every kind of word is 20, and the effective information position is that the front three of 16 each words is synchronous prefix, and last position is odd parity bit.Effective information (16) and parity check bit form with Manchester code on bus are transmitted, and every time that accounts for is 1 μ s.Synchronously prefix accounts for three, or earlier positive back negative (command word, status word) or negative earlier after just (data word).Just/negative level respectively accounts for 1.5 μ s, namely accounts for half with potential field.Because the type difference of system can pick out command word and status word, command word is sent by existing bus controller, and status word is always sent by remote terminal RT.
Data is based on message mechanism alternately on the 1553B bus.This standard definition 10 kinds of transmission of messages forms, and these 10 kinds of transformats all adopt aforesaid 3 kinds of word types, the data transmission on the bus is exactly to adopt a kind of in these 10 kinds of transmission of messages forms.Its transmission course is as follows: BC sends certain command word by bus, and all RT receive this command word, and the address field in the command word is compared with the address of oneself, identical this command word that then receives; Subsequently, RT is, and command word is resolved, and finishes corresponding operation (receive data word, send data word, synchronously, self check etc.) according to order.These operations all can produce corresponding status word and send to BC.BC judges by status word whether RT is working properly.If the terminal address in the command word that RT receives is broadcast address, then all RT receive this order, but all BC given in the non-return state word.
Interface as the MIL-STD-1553B bus should be finished following function: 1. the Serial Flow on the bus is converted to the manageable parallel information of processor or in contrast; 2. receive or during the information of transmission, can identify or generate 1553B information word and the message of standard; 3. finish and processor between message exchange, comprise the distribution of 1553B message address, the decoding of command word (or status word) or return state word, send data word etc.What the Manchester code codec was finished is coding and the decoding of Manchester code, and detects mistake.It receives the Manchester code with effective synchronization character, the row decoding of going forward side by side, and identify its type and serial/parallel conversion, parity checking etc.; The parallel binary data of perhaps processor being sent are carried out Manchester code coding, add synchronous prefix and parity bit and make it to become the word that meets the 1553B standard and export.
Interface module hardware design of the present invention need be finished following function: total line traffic control and communication, and data buffer memory and processing, the driving circuit of the elementary interface of 1553B bus, general frame is as Fig. 1. shown in.
Interface module hardware of the present invention is made up of level shifting circuit, Manchester code codec, command word/status word decoding logic and CPU and interlock circuit, as Fig. 2. shown in.Except codec can be realized by FPGA, the interlock circuit between it and the CPU also can be realized by FPGA as RAM Shared, command word/status word decoding and memory management, processor and memory interface logic etc.; This interface module hardware composition has XC2VP30 device, SDRAM (can expand to 2GB), high speed SelectMAPFPGA configuration PROM, RS232 serial ports, embeds USB configured port, the High Speed System expansion interface (linking to each other with the I/O pin of FPGA) of platform.
Interface module of the present invention determines to adopt FPGA (being field programmable gate array) to realize the 1553B bus interface logic.
The protocol processes of 1553B and encoding and decoding are all realized by FPGA.Integrated BC, BM and R/T function on same circuit can be selected required function by software setting.Simultaneously, it combines communication and test function, can either detect the various mistakes that may occur, and can produce various mistakes according to test request again.
The 1553B bus protocol is cooperated by hardware and software to be realized.Whole design idea is: hardware and software adopts interruption and inquires about 2 kinds of modes, carries out information interaction by a shared data Buffer.Following introducing system overall data transmitting-receiving flow process.The software and hardware function of native system is divided the work according to this flow process and is realized.
1. data transmission flow
Upper layer software (applications) will be controlled with the form of data structure and data information transfer is given hardware logic electric circuit, and hardware circuit automatically sends to data on the 1553B bus according to control information.When CPU sent data to hardware logic, whether the transmission that at first should detect last time finished.Concrete grammar is: the read channel status register is sent completely the position, if effectively, expression transmission last time is through with.Only detect transmission last time and be through with, just can carry out the transmit operation of data.Hardware circuit can produce interrupt request after data are sent.Software removes the query State register according to interrupt request, determines next step operation.Transfer process is summarized as follows:
(1) CPU sends FIFO to data and writes 1 instruction word/status word and error-control information;
(2) CPU writes the transmission enable signal to channel control register;
(3) CPU sends FIFO to data and writes 0～32 secondary data and error-control information;
(4) hardware logic detects the transmission enable signal;
(5) the hardware logic data that will be stored among the FIFO automatically take out in turn;
(6) hardware logic carries out after the respective handling data being sent on the 1553B bus to data according to error-control information;
(7) hardware logic is put and is sent completely mode bit after sending the end of message 2 μ s, and produces look-at-me.
2. data receive flow process
Hardware logic carries out error-detecting to these data after receiving data on the 1553B bus, and corresponding status information and data are combined to be deposited into together receives among the FIFO.After reception FIFO reaches a constant volume, just produce look-at-me to CPU.The FIFO of CPU carries out read operation, and data and state are taken out.Receiving step is as follows:
(1) hardware logic receives the data on the bus;
(2) hardware logic carries out error-detecting to data, produces status information;
(3) hardware logic writes data and status information among the reception FIFO;
(4) when reaching a constant volume, FIFO just produces look-at-me when receiving;
(5) the CPU response external is interrupted;
(6) the FIFO of CPU carries out read operation, and status information and data are taken away;
(7) the status information of CPU is resolved, and determines the processing to data.
The exploitation of 1553B bus protocol is mainly developed in the FPGA device, so the quality of the performance of FPGA own will influence the exploitation of system.It is that 428KB, 136 multiplier unit pieces, RAM are 2448KB, 8 DCM, gigabit transceiver more than 8 that XC2VP30 inside has 2 PowerPC405 processor cores, 13969 Slices, distributed RAM.Therefore, select for use XC2VP30FPGA to satisfy 1553B bus logic development requirement fully.This interface module solves coding, the decoding technique problem of graceful Chester sign indicating number with the VHDL hardware description language; Realize communication protocol and storage administration with the New DSP chip, the requirement of satisfiability energy, and reduce volume; Metal-oxide-semiconductor with miniaturization is realized bus driver, satisfies the designing requirement of miniaturization in conjunction with stacked IC package technique.
After the design of 1553B bus interface circuit is finished, can in the bag that develops software of FPGA, compile and emulation, further optimize logic and structure Design at the problem of finding, and generation programmed configurations file, carry out the Configuration Online chip by programming cable (or CPU of inside modules) then, perhaps by programmable device to this chip programming, just can carry out function debugging at circuit board then.If pinpoint the problems, make amendment again design, emulation, reconfigure and on-line debugging, up to debugging successfully.
The function of FPGA all adopts VHDL language to realize that its functional block diagram as shown in Figure 2.Its work of mainly finishing has: the encoding and decoding of (1) Manchester code comprise serial/parallel conversion.(2) parsing of the message of 1553B agreement comprises the identification of synchronous head, and identification of various mistakes, parity checking etc.(3) message of 1553B agreement takes place, and comprises the generation of the generation of synchronous head, various mode bits and the generation of various error messages.(4) with the realization of cpu i/f.(5) realization of various look-at-mes.(6) timing and overtime control circuit etc.
3. the bus transtation mission circuit is realized
If do not inject wrong requirement, the realization of scrambler is just fairly simple, only needs with the transfer rate (the design adopts 12 frequencys multiplication) of several times 1553B parallel data to be converted to serial data, adds that corresponding synchronous head gets final product.Data transmit circuit mainly is made up of a state machine, twoport FIFO, injection error flag register and control circuit on hardware.The constitutional diagram of state machine as shown in Figure 3.After resetting, this state machine detects at the rising edge of each clock whether data are arranged among the FIFO, if sky then rests on idle condition.In case after upper layer software (applications) write data by the EBC interface to FIFO, hardware circuit was read data automatically.Enter into synchronous head and send state, hardware circuit is sent corresponding serial synchronous head according to the control word of command register, enters data subsequently and sends state.On each clock edge, shift register shifts out the data of data register, carries out sending behind the graceful sign indicating number coding, and simultaneously, data counter adds 1 automatically.When count value is 16, then be transferred to parity state, send behind the check digit coding that XOR is obtained.
The present invention requires to have test function, mainly contains the following wrong requirement of injecting:
(1) EI_BITCOUNT: the figure place mistake of specific data in the message (not being 16);
(2) EI_PARITY: the check bit mistake of specific data in the message;
(3) EI_SYNC: the synchronous head of mistake;
(4) EI_WORDCOUNT: make data length in the message be not equal to length in the command word;
(5) EI_MIDBIT: specific data position zero crossing mistake, than desired locations time-delay 300ns;
(6) EI_MIDSYNC: the zero crossing mistake of synchronous head, than desired locations time-delay 300ns;
(7) EI_BIPHASE: do not have zero crossing in the time of whole.
Hardware circuit requires to add corresponding circuit in state machine, detects the zone bit in the error register, and produces corresponding mistake.
4. the bus receiving circuit is realized
Be that BC or RT need the data of receiving are resolved.The major function of receiving circuit has: the detection of decoding, string and conversion, synchronous head detection, parity checking and the various mistakes of graceful sign indicating number.As shown in Figure 4, enter the synchronous head search condition after state machine resets.Hardware circuit removes to detect several synchronous heads with the frequency of 12 times of 1553 bus transfer rate.Then with the correspondence position position in the status register, and change data receiving state over to by synchronous head if receive; Otherwise, rest under this state.Under the data receiving state, shift register will move into through the data of decoding on the clock edge.After counting down to 16, data counter is transferred to parity state; Afterwards, data and state are written among the FIFO.Hardware circuit will detect various mistakes in each stage of state machine, if make mistakes then get back to the synchronous head search condition.Simultaneously, produce error flag and look-at-me.
5. the realization of hardware interrupts function
As mentioned above, the communication of native system software and hardware is mainly carried out information interaction by the mode of interrupting and inquire about.Hardware circuit has been realized following interrupt function:
(1) receives that whenever 1 order/status word produces interruption;
(2) the data length counter interrupts and enables.Software is resolved order/status word of receiving, if there are data to prepare to receive, the data length value is write the data length counter, simultaneously enable counter.Hardware is received 1 data word, and down counter interrupts up to 0 generation, forbids that simultaneously this data counter interrupts;
(3) it is half-full or 3/4 produce at full capacity to give birth to and interrupt to receive FIFO;
(4) receive FIFO full up (overflow) and produce interruption;
(5) sending FIFO is that empty the generation interrupted;
(6) interruption status/enable register;
(7) wait timeout interrupts (it is not enough to receive data length);
(8) the data counter interruptions is stamped timestamp; Receive that each order/status word stamps timestamp; The synchronous head zero crossing of the order/status word that sends is stamped timestamp.
Characteristics according to data layout and the Manchester code of 1553B can adopt state machine to its realization of encoding, decoding.State machine is the sequential circuit of a broad sense, and image shift register, counter etc. all are a kind of in its specific function type.According to the relation between input, output and the state, state machine can be divided into two classes: a kind of is that output state is relevant, and the input with state do not have state machine types, be called the More state machine; Another kind is output and input and all related state machine of state, is called the Mealy state machine.What the design adopted is the Mealy state machine.Code And Decode is two separate modules.
6. decoding
The process of decoding can be divided into three parts: 1. prefix detects synchronously, and distinguishes that it is data word or command word.2. the data of graceful sign indicating number form are decoded.Because Manchester code carries timer clock, so can isolate synchronous clock from data.The design adopts is that the method for traditional usefulness digital phase-locked loop is come separated clock; Clock and data are handled make graceful code data be converted into the non-return-to-zero binary data.3. serial data is converted into parallel data, and carries out parity checking.
7. encode
Whether the process of coding also can be divided into three parts: 1. detect code period and begin, produce synchronous prefix; 2. carry out serial conversion, produce parity check bit; 3. 16 valid data and parity bit are encoded, code period finishes.With the decoding in like manner, the coding also realized by state machine.
The software design comprises that plate carries embedding program, host driver design.Plate carries the embedding program and host driver is finished data interaction by sharing the plug-in internal memory of PPC, and plate carries embedded program finishes hardware operation and data transmit-receive by register and the FIFO that visits FPGA.
When module option is multifunction module, require each passage can carry out work as BC, BM and maximum 31 RT simultaneously period in same work.When the got terminal of system under test (SUT) has in limited time, wish to obtain sufficient complete test again, multifunction module will provide sufficient terminal in order to test.In order simultaneously and correctly to serve as BC, BM, a RT3 different role, the state machine design thought of FPGA (Field Programmable Gate Array) design has been introduced in the embedded program design of module.BC, BM, RT have the state machine of oneself separately.
Key technologies for application in the system development:
● encoding and decoding VHDL in Manchester realizes;
● the VHDL of CRC cyclic redundancy check (CRC) realizes;
● the hardware of trembling wave filter that disappears is realized;
● the hardware expanding of shared storage;
● the VHDL of 1553B core protocol realizes;
● 4M, 10M transceiver;
● software and Driver Development.
The performance of system or index:
● satisfy the requirement of GJB289A-97 interior of aircraft time-devision system instruction/response type multiplex data bus;
● multichannel dual redundant bus;
● support the single function operation pattern of BC/RT/MT, support BC﹠amp; NRT﹠amp; The MT multifunctional mode;
● the software programming of RT address is selected;
● bus transfer rate 1M, 4M, 10Mbps;
● bus transfer word error rate is not more than 10-7;
● the RT status word response time is not more than 12 μ S;
● supporting bus directly is coupled or is transformer coupled;
● hyperchannel BC synchronizing function.
BC：
● support the asynchronous message transmission;
● the control of message time
● support retry and bus to switch.
RT：
● single buffer memory;
● two buffer memorys;
● invalid message.
MT：
● full message monitoring;
● can select message monitoring.
1553B bus interface assembly has been finished support to the MIL-STD-1553B procotol at software, realized perfect communication algorithm with DSP, realized that short message reacts with quick RT at interval, can be used as real-time bus controller (BC) or bus monitor (MT), also can make remote terminal (RT), support two redundant operations of all working pattern.
The invention has the beneficial effects as follows: realize the MIL-STD-1553B agreement by FPGA; Solve coding, the decoding technique problem of graceful Chester sign indicating number with the VHDL hardware description language; Realize communication protocol and storage administration with the New DSP chip, RAM Shared is utilized the DSP on-chip memory, realizes that software emulation is shared, and reduces volume, satisfies the designing requirement of miniaturization, also is easy to carry out as required the function expansion, uses flexibly.The Products Development cost is far below the external special purpose interface chip of exploitation.
Description of drawings
The present invention is further described below in conjunction with drawings and Examples.
Fig. 1 is general frame schematic diagram of the present invention.
Fig. 2 is 1553B bus interface circuit of the present invention.
Fig. 3 is 1553B data transmission system structural drawing of the present invention.
Fig. 4 is decoder logic block diagram of the present invention.
Fig. 5 is encoder logic block diagram of the present invention.
Embodiment
In Fig. 1, the bonding properties index is that main composition device is selected, and builds overall architecture.The research and development of total system are based on the PCI/CPCI bus, and module PCI bridge is realized the data interaction of PC and system; FPGA is responsible for the realization of 1553B bus protocol; The SDRAM module realizes the storage of data; Transceiver is responsible for the coupling conversion of level and impedance.
In Fig. 2, the 1553B bus interface is made up of level shifting circuit, Manchester code codec, command word/status word decoding logic and CPU and interlock circuit, except codec can be realized by FPGA, interlock circuit between it and the CPU also can be realized by FPGA as RAM Shared, command word/status word decoding and memory management, processor and memory interface logic etc.Adopt the FPGA technology that the 1553B bus interface logic is designed, realize the principle of Manchester encoding and decoding and coordinate the work of each functional circuit with DSP with VHDL language.The software design is by studying the 1553B agreement, and three kinds of mode of operations, word format and message formats of design 1553B have designed BC in the 1553B communication, RT, the operating process of three kinds of mode of operations of MT.
Provide the source code of part coding module below:
Figure 3 shows that 1553B data transmission system structural drawing, the unique lane controller of summing up of the control of bus system information transmission owns, the operation of bus system should be the asynchronous operation of instruction/response type, information transmission on the data bus should be carried out with half-duplex mode, information flow on the data bus should be made up of message, and bus system should have the mode control ability.
Figure 4 shows that the decoder logic block diagram, data is serial input data among the figure.Carrying out synchronous head when data begins saltus step takes place detects, if height (or low) level when after data changes, detecting greater than a position, think that then synchronous head is effective, output synchronous head type (comnd) and synchronous head detecting position (synerr) (being low level, if high level represents that then synchronous head is wrong).After synchronous head is effective, carry out clock separation and code conversion and displacement, to carry out parity checking after displacement is finished, and data are write the maintenance register surely, this moment, rxrdy became high level, and the expression DSR can sense data.Enter the next decoding cycle, wait for serial input data.
Figure 5 shows that the encoder logic block diagram, the input clock of scrambler (mclk) is 16MHz.When write signal (wr) was low level, it was high level that synchronous head is selected position (cmnd), begins to produce the synchronous prefix of command word; Otherwise, be synchronous prefix.Because when the high-low level of prefix respectively accounts for 1.5 positions synchronously, be 2MHz so choose its tranmitting data register, this clock is obtained by mclk eight frequency divisions.Prefix produces and finishes synchronously, then sends control signal and begins displacement.Clock two frequency divisions of using when shift clock (1MHz) is generated by synchronous head produce.When finishing, the data displacement adds parity bit automatically.Graceful sign indicating number shaper is handled data, parity bit, synchronous head and is formed bipolarity word tx and the ntx that meets the 1553B standard, and txrdy is high level after finishing, and that waits for next data writes beginning cataloged procedure again.
Claims (3)
1. the interface integrated circuit board based on the CPCI framework of MIL-STD-1553B bus is characterized in that: realize the MIL-STD-1553B bus protocol by FPGA.
2. the interface integrated circuit board of the CPCI framework based on the MIL-STD-1553B bus according to claim 1 is characterized in that: realize the Manchester code coding and decoding with the VHDL hardware description language.
3. the interface integrated circuit board of the CPCI framework based on the MIL-STD-1553B bus according to claim 1 is characterized in that: adopt MAX+PLUS II to carry out sequential emulation; According to the MIL-STD-1553B agreement, miniaturization bus driving circuits reasonable in design; Write the DSP program curing, can reach supported protocol, finish modularization interface module function.
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| CN103723288A (en) * | 2013-12-19 | 2014-04-16 | 上海卫星工程研究所 | Miniaturized satellite open power supply and distribution subsystem |
| CN104679693A (en) * | 2013-11-26 | 2015-06-03 | 深圳市国微电子有限公司 | Multi-interface mode realization method of 1553B bus protocol IP (Internet Protocol) core |
| CN105425137A (en) * | 2015-10-09 | 2016-03-23 | 天津市英贝特航天科技有限公司 | Test base plate for 61580 chips |
| CN109347474A (en) * | 2018-09-28 | 2019-02-15 | 深圳忆联信息系统有限公司 | Signal sequence configuration method, device, computer equipment and storage medium |
| CN109450761A (en) * | 2018-12-20 | 2019-03-08 | 成都旋极历通信息技术有限公司 | A kind of multi-functional 1553B communication module |
| CN109542818A (en) * | 2018-11-16 | 2019-03-29 | 陕西千山航空电子有限责任公司 | A kind of general 1553B interface arrangement |
| CN113595842A (en) * | 2021-06-18 | 2021-11-02 | 天津津航计算技术研究所 | FC-AE-1553 protocol message communication processing system |
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| CN113595842A (en) * | 2021-06-18 | 2021-11-02 | 天津津航计算技术研究所 | FC-AE-1553 protocol message communication processing system |
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