CN113595842A

CN113595842A - FC-AE-1553 protocol message communication processing system

Info

Publication number: CN113595842A
Application number: CN202110678275.0A
Authority: CN
Inventors: 赵昶宇; 黄庆海; 刘振业
Original assignee: Tianjin Jinhang Computing Technology Research Institute
Current assignee: Tianjin Jinhang Computing Technology Research Institute
Priority date: 2021-06-18
Filing date: 2021-06-18
Publication date: 2021-11-02
Anticipated expiration: 2041-06-18
Also published as: CN113595842B

Abstract

The invention relates to a FC-AE-1553 protocol message communication processing system, belonging to the technical field of FC-AE-1553 bus and MIL-STD-1553 bus communication; the host module of the main controller receives the control instruction of the upper computer and stores the control instruction in the message queue, stores the actually received control instruction of the upper computer into the stack of the programmable logic module of the main controller from the message queue each time, and establishes the mapping relation between the sequence number of the received control instruction and the sequence number of the control instruction in the stack; the programmable logic module sends the control instruction to the bridge module, the bridge module sends the control instruction to the terminal simulator equipment through the MIL-STD-1553 bus, the phenomenon that the control instruction is covered is avoided, hardware resource expenditure is saved, the real-time performance and the reliability of processing the control instruction of the upper computer are obviously improved, and the method is particularly suitable for the situation that the RT addresses and the RT sub-addresses related to the control instruction sent by the upper computer each time are not large, but the sending frequency of the control instruction of the upper computer is high.

Description

FC-AE-1553 protocol message communication processing system

Technical Field

The invention belongs to the technical field of FC-AE-1553 bus and MIL-STD-1553 bus communication, and relates to an FC-AE-1553 protocol message communication processing system.

Background

The 1553B bus is an MIL-STD-1553 bus for short, is a time-division command/response type multiplexing data bus in an airplane, and has three terminal types: the main characteristics of the bus controller, the remote terminal and the bus monitor are distributed processing, centralized control and real-time response.

The FC-AE-1553 bus is an extension of the MIL-STD-1553B bus in bandwidth, address space, and data traffic for the purpose of better supporting communication between elements in an avionics system. The FC-AE-1553 bus protocol defines a command/response type bus, adopts a fiber channel technology, and generally consists of a network controller, a network terminal, a fiber channel network, an FC-AE-1553 bus bridge and an MIL-STD-1553 bus.

And the FC-AE-1553 protocol and the MIL-STD-1553 are mutually converted in a bridge of the avionic test system. The upper computer sends an upper computer control instruction to the main controller host module through the Ethernet, the main controller host module receives the upper computer control instruction sent by the upper computer through the Ethernet, analyzes and processes the upper computer control instruction, generates an FC-AE-1553 control instruction, and sends the generated FC-AE-1553 control instruction to the main controller programmable logic module through a DMA mode. And the main controller programmable logic module receives the FC-AE-1553 control instruction sent by the main controller host module and sends the FC-AE-1553 control instruction to the bridge module through the optical fiber switch.

And the bridge module converts the FC-AE-1553 control instruction through an MIL-STD-1553 protocol to generate an MIL-STD-1553 data instruction, and sends the generated MIL-STD-1553 data instruction to the terminal simulator equipment through an MIL-STD-1553 bus.

And the terminal simulator equipment sends the MIL-STD-1553 feedback data generated by the terminal simulator equipment to the bridge module through an MIL-STD-1553 bus.

The bridge module receives MIL-STD-1553 feedback data sent by the terminal simulator equipment, the MIL-STD-1553 feedback data is converted through an FC-AE-1553 protocol to generate FC-AE-1553 feedback data, and the generated FC-AE-1553 feedback data is sent to the main controller programmable logic module through the optical fiber switch. And the main controller programmable logic module sends FC-AE-1553 feedback data to the main controller host module in a DMA mode.

After receiving the FC-AE-1553 feedback data, the main controller host module performs package processing on the FC-AE-1553 feedback data according to the Ethernet message to generate an upper computer feedback instruction, and sends the generated upper computer feedback instruction to an upper computer through the Ethernet.

A main controller module of the avionic test system is composed of a host module and a programmable logic module, if the number of RT addresses and RT sub-addresses related to the communication between an upper computer and the host module is large (the number of RT addresses is 32 at most, and the number of RT sub-addresses is 32 at most), and the information of the number of the RT addresses and the RT sub-addresses contained in control instructions of the upper computer cannot be obtained before the host module communicates with the upper computer, the number of the control instructions sent to the programmable logic module by the host module cannot be determined (each control instruction sent to the programmable logic module by the host module contains 1 RT address and 1 RT sub-address information). In order to ensure normal communication between the host computer and the terminal simulator device, the host computer module needs to configure the theoretically maximum number of control instructions, namely 32 × 2 (including NC- > NT and NT- > NC two types of control instructions, the control instruction sequence numbers are not repeated, the RT addresses are 32 at most, and the RT sub-addresses are 32 at most) to the programmable logic module during initialization. Since the number of control instructions that can be accommodated in the stack of the programmable logic module is N (0< N <256, and much less than 32 × 2), the programmable logic module is configured according to the above method, and most FC-AE-1553 control instructions are lost by the programmable logic module, which finally results in a failure in communication between the upper computer and the terminal simulator.

Disclosure of Invention

The technical problem solved by the invention is as follows: overcomes the defects of the prior art and provides a method for improving the bonding strength of rubber and fiber fabric.

The technical scheme of the invention is as follows:

a FC-AE-1553 protocol message communication processing system comprises an upper computer, a main controller host module, a main controller programmable logic module, a fiber switch, a bridge module and terminal simulator equipment;

an upper computer: generating a control instruction, and sending the control instruction to a host module of the main controller through the Ethernet; each control instruction comprises an RT address message, and the RT address message is only corresponding to an RT sub-address message; receiving an upper computer feedback instruction transmitted by a main controller host module, and realizing the communication between the upper computer and the terminal simulator equipment;

main controller host computer module: receiving a control instruction transmitted by an upper computer, analyzing the control instruction, saving a serial number distributed during initialization of the control instruction corresponding to an RT sub-address in an array A taking a received control instruction count as a subscript when processing the RT sub-address information corresponding to the RT sub-address, adding one to the received control instruction count, and generating an FC-AE-1553 control instruction; sending the generated one or more FC-AE-1553 control instructions, the received control instruction count and the array A to a programmable logic module of a main controller in a DMA mode; receiving FC-AE-1553 feedback data transmitted by a programmable logic module of the main controller, performing security violation processing on the FC-AE-1553 feedback data according to an Ethernet message, generating an upper computer feedback instruction, and transmitting the upper computer feedback instruction to an upper computer through the Ethernet;

the main controller programmable logic module: receiving an FC-AE-1553 control instruction transmitted by a host module of the main controller, receiving a control instruction count and an array A; saving the FC-AE-1553 control instruction into a stack; counting the received control instructions as the number of the control instructions in the stack; using the subscript of the array A as the serial number of each control instruction in the stack; and sending the FC-AE-1553 control instruction to a bridge module through an optical fiber switch; receiving FC-AE-1553 feedback data transmitted by the bridge module, and transmitting the FC-AE-1553 feedback data to the main controller host module in a DMA mode;

a bridge module: receiving an FC-AE-1553 control instruction transmitted by a programmable logic module of the main controller, converting the FC-AE-1553 control instruction by an IL-STD-1553 protocol and generating an MIL-STD-1553 data instruction; sending the MIL-STD-1553 data instruction to terminal simulator equipment through an MIL-STD-1553 bus; receiving MIL-STD-1553 feedback data transmitted by terminal simulator equipment, converting the MIL-STD-1553 feedback data through an FC-AE-1553 protocol to generate FC-AE-1553 feedback data, and transmitting the FC-AE-1553 feedback data to a programmable logic module of a main controller through an optical fiber switch;

terminal simulator equipment: and receiving an MIL-STD-1553 data instruction transmitted by the bridge module, generating MIL-STD-1553 feedback data, and transmitting the MIL-STD-1553 feedback data to the bridge module.

Before the message communication processing system works, the FC-AE-1553 protocol message communication processing system performs initialization processing on a host module of a main controller, specifically: dynamically applying for a block of memory space for storing 32 × 2 control instructions; each control instruction comprises RT sub-address information, the count of the initialized received control instruction is 0, and the serial number of each control instruction is initialized.

In the FC-AE-1553 protocol message communication processing system, the control instruction sequence numbers are increased progressively from 0, and all the sequence numbers are not repeated.

Before the message communication processing system works, the main controller host module dynamically applies for a memory space for storing control instructions of different RT addresses and different RT sub-addresses transmitted by the upper computer; the RT address types are 32 at most, and each RT address corresponds to the RT sub-address type of 32 at most; then, the principle of the sequence number allocated by the control instruction corresponding to the RT sub-address during initialization is as follows:

the serial numbers of RT address 0 and RT sub-address 0 are 0, RT address 0 and RT sub-address 1 are 1, RT address 0 and RT sub-address 2 are 2, ·, RT address 0 and RT sub-address 31 are 31, RT address 1 and RT sub-address 0 are 32, RT address 1 and RT sub-address 1 are 33, RT address 1 and RT sub-address 2 are 34, ·, RT address 1 and RT sub-address 31 are 63, ·, RT address 31 and RT sub-address 0 are 992, RT address 31 and RT sub-address 1 are 993, RT address 31 and RT sub-address 2 are 994, ·, RT address 31 and RT sub-address 31 are 1023.

In the FC-AE-1553 protocol message communication processing system, the format of the upper computer control instruction is instruction identification + information source identification + information sink identification + instruction sequence number + instruction length + instruction valid field content + checksum; the content of the last word of the control instruction is a checksum, and the checksum is calculated according to the CRC16 check algorithm by using the content of the control instruction except the checksum.

In the FC-AE-1553 protocol message communication processing system, the specific method for the main controller host module to analyze and process the control instruction is as follows:

when processing a certain RT sub-address information, the main controller host module sets a source address sent by a data frame, a destination address sent by the data frame, a data frame sub-address and a data frame length in a data frame header, fills the content of an effective field of an upper computer instruction into a data field, calculates the CRC check value of the data frame header and the data field, and generates an FC-AE-1553 control instruction according to the data format of the data frame start + the data frame header + the data field + the CRC check + the data frame end.

In the FC-AE-1553 protocol message communication processing system, the host module of the main controller stores the generated FC-AE-1553 control instruction, the count of the received control instruction and the content of the array a in the DDR data buffer area, notifies the programmable logic module of the main controller through the PCIE bus that the data is ready to be received from the DDR data buffer area, and sends the start address space, the data length, the source address of the received data, and the destination address of the received data to the programmable logic module of the main controller.

In the FC-AE-1553 protocol message communication processing system, after the host module of the main controller receives the data receiving ready signal of the programmable logic module of the main controller through the PCIE bus, the DMA controller is started, and the data in the DDR buffer area is sent to the programmable logic module of the main controller in a DMA manner.

In the FC-AE-1553 protocol message communication processing system, after the data in the DDR buffer area is taken away by the main controller programmable logic module, a data reception completion signal is sent to the main controller host module through the PCIE bus, and FC-AE-1553 control instructions in the DDR buffer area are stored in the stack, and the reception control instruction count in the DDR buffer area is used as the number of control instructions in the stack of the main controller programmable logic module; the subscript of the array A in the DDR buffer area is used as the serial number of each control instruction in the stack, and the array element content corresponding to the subscript of the array A is the serial number allocated to the control instruction during initialization.

In the FC-AE-1553 protocol message communication processing system, after the main controller programmable logic module receives FC-AE-1553 feedback data sent by the optical fiber switch, the FC-AE-1553 feedback data is stored in a DDR data buffer area, the PCIE bus informs the main controller host module to prepare to receive data from the DDR data buffer area, and sends the initial address space, the data length, the received data source address and the received data destination address of the received data to the main controller host module; and after receiving the information, the host module of the main controller starts the DMA controller to acquire FC-AE-1553 feedback data stored in the DDR buffer area by the programmable logic module of the main controller in a DMA mode.

Compared with the prior art, the invention has the beneficial effects that:

(1) when the host module configures a control instruction to the programmable logic module, the phenomenon of read-write conflict when the host module and the programmable logic module access a shared storage area is avoided;

(2) the invention adopts the message mapping method to configure the control instruction, does not need to increase the hardware memory space and the hardware resources in the programmable logic module, and has the characteristics of simple program processing, low system overhead, low cost and the like;

(3) the method obviously improves the real-time performance and reliability of receiving and processing the control instruction of the upper computer, and is particularly suitable for the situation that the RT addresses and the RT sub-addresses involved in the control instruction sent by the upper computer each time are not many, but the sending frequency of the control instruction of the upper computer is relatively high.

Drawings

Fig. 1 is a schematic diagram of a message communication processing system according to the present invention.

Detailed Description

The invention is further illustrated by the following examples.

The FC-AE-1553 protocol message communication processing system provided by the invention is used for realizing communication between an upper computer and terminal simulator equipment and has higher requirements on the real-time property and the reliability of the communication. The external interface of the upper computer is only an Ethernet interface, so that the upper computer and the main controller module adopt Ethernet communication. In order to improve the transmission efficiency and the throughput of the whole system, an FC-AE-1553 bus + protocol bridging mode is adopted between a main controller module and terminal simulator equipment, so that on one hand, the FC-AE-1553 bus can greatly improve the data transmission speed and the data transmission quantity; on the other hand, the mode of protocol bridging enables the main controller module to be matched with terminal simulator equipment with different communication rates, improves the efficiency of protocol conversion and avoids system overhead caused by software processing.

Because the number information of the RT addresses and the RT sub-addresses contained in the control instructions of the upper computer cannot be obtained before the host module of the main controller communicates with the upper computer, only by adopting the scheme of the invention, the phenomenon of read-write conflict when the host module and the programmable logic module access a shared storage area can be avoided, and the phenomenon that the FC-AE-1553 control instructions are lost or covered due to insufficient resources of the programmable logic module can be avoided, thereby obviously improving the reliability of the communication between the upper computer and the terminal simulator equipment.

As shown in fig. 1, the FC-AE-1553 protocol packet communication processing system specifically includes an upper computer, a main controller host module, a main controller programmable logic module, a fiber switch, a bridge module, and a terminal simulator.

An upper computer: generating a control instruction, and sending the control instruction to a host module of the main controller through the Ethernet; each control instruction comprises an RT address message, and the RT address message is only corresponding to an RT sub-address message; and receiving an upper computer feedback instruction transmitted by the main controller host module to realize the communication between the upper computer and the terminal simulator equipment.

Before the message communication processing system works, the initialization processing is carried out on a main controller host module, and the initialization processing specifically comprises the following steps: dynamically applying for a block of memory space for storing 32 × 2 control instructions; each control instruction comprises RT sub-address information, the count of the initialized received control instruction is 0, and the serial number of each control instruction is initialized. The control command sequence number is incremented from 0, and all the sequence numbers are not repeated. The main controller host module dynamically applies for a block of memory space for storing control instructions of different RT addresses and different RT sub-addresses transmitted by the upper computer; the RT address types are 32 at most, and each RT address corresponds to the RT sub-address type of 32 at most; then, the principle of the sequence number allocated by the control instruction corresponding to the RT sub-address during initialization is as follows:

for NC- > NT type, the sequence number of RT address 0 and RT sub-address 0 is 0, the sequence number of RT address 0 and RT sub-address 1 is 1, the sequence number of RT address 0 and RT sub-address 2 is 2, ·, the sequence number of RT address 0 and RT sub-address 31 is 31, the sequence number of RT address 1 and RT sub-address 0 is 32, the sequence number of RT address 1 and RT sub-address 1 is 33, the sequence number of RT address 1 and RT sub-address 2 is 34,..., the sequence number of RT address 1 and RT sub-address 31 is 63,..., the sequence number of RT address 31 and RT sub-address 0 is 992, the sequence number of RT address 31 and RT sub-address 1 is 993, the sequence number of RT address 31 and RT sub-address 2 is 994,. the sequence number of RT address 31 and RT sub-address 31 is 1023. For the NT- > NC type, the numbering principle is the same as that of the NC- > NC type, the serial number of the RT address 0 and the RT sub-address 0 is 1024, the numbering is increased, and the serial number of the RT address 31 and the RT sub-address 31 is 2047.

Main controller host computer module: and receiving a control instruction transmitted by the upper computer, and analyzing the control instruction. The specific method for analyzing and processing the control instruction by the main controller host module comprises the following steps:

When processing RT sub-address information corresponding to an RT address, storing a serial number distributed during initialization of a control instruction corresponding to the RT sub-address in an array A taking a received control instruction count as a subscript, adding one to the received control instruction count, and generating an FC-AE-1553 control instruction; sending the generated one or more FC-AE-1553 control instructions, the received control instruction count and the array A to a programmable logic module of a main controller in a DMA mode; and receiving FC-AE-1553 feedback data transmitted by the programmable logic module of the main controller, performing security processing on the FC-AE-1553 feedback data according to an Ethernet message, generating an upper computer feedback instruction, and transmitting the upper computer feedback instruction to an upper computer through the Ethernet.

The host module of the main controller stores the generated FC-AE-1553 control instruction, the received control instruction count and the content of the array A in a DDR data buffer area, informs the programmable logic module of the main controller of being ready to receive data from the DDR data buffer area through a PCIE bus, and sends the initial address space, the data length, the received data source address and the received data destination address of the received data to the programmable logic module of the main controller. And after receiving a data receiving and preparing signal of the programmable logic module of the main controller through the PCIE bus, the host module of the main controller starts the DMA controller and sends the data in the DDR buffer area to the programmable logic module of the main controller in a DMA mode.

The main controller programmable logic module: receiving an FC-AE-1553 control instruction transmitted by a host module of the main controller, receiving a control instruction count and an array A; saving the FC-AE-1553 control instruction into a stack; counting the received control instructions as the number of the control instructions in the stack; using the subscript of the array A as the serial number of each control instruction in the stack; and sending the FC-AE-1553 control instruction to a bridge module through an optical fiber switch; and receiving FC-AE-1553 feedback data transmitted by the bridge module, and transmitting the FC-AE-1553 feedback data to the host controller module in a DMA mode.

After taking the data in the DDR buffer area, the main controller programmable logic module sends a data receiving completion signal to the main controller host module through the PCIE bus, and stores FC-AE-1553 control instructions in the DDR buffer area into a stack, and the receiving control instruction count in the DDR buffer area is used as the control instruction number in the stack of the main controller programmable logic module; the subscript of the array A in the DDR buffer area is used as the serial number of each control instruction in the stack, and the array element content corresponding to the subscript of the array A is the serial number allocated to the control instruction during initialization.

After receiving FC-AE-1553 feedback data sent by the optical fiber switch, the main controller programmable logic module stores the FC-AE-1553 feedback data in a DDR data buffer area, informs a main controller host module through a PCIE bus that the data is ready to be received from the DDR data buffer area, and sends a starting address space, a data length, a received data source address and a received data destination address of the received data to the main controller host module; and after receiving the information, the host module of the main controller starts the DMA controller to acquire FC-AE-1553 feedback data stored in the DDR buffer area by the programmable logic module of the main controller in a DMA mode.

The format of the upper computer control instruction is instruction identification, information source identification, information sink identification, instruction sequence number, instruction length, instruction effective field content and checksum; the content of the last word of the control instruction is a checksum, and the checksum is calculated according to the CRC16 check algorithm by using the content of the control instruction except the checksum.

1. The host module receives the upper computer control instruction and sends a handshake signal to the programmable logic module

After receiving an upper computer control instruction sent by an upper computer, the host module analyzes and processes an RT address, an RT sub-address, data length, data content and a message type in the message through a message queue, and divides the message into an NC-NT type message and an NT-NC type message. The host module sends a handshake signal to the programmable logic module through the PCIE bus to inform the programmable logic module that the host module is ready to receive the FC-AE-1553 control command.

2. The host module completes the configuration of each FC-AE-1553 control instruction

In order to avoid the storage overflow phenomenon of the stack of the programmable logic module, the host module only needs to store the upper computer control instruction actually received from the message queue into the stack of the programmable logic module each time. Therefore, when the host module sends the FC-AE-1553 control instructions to the programmable logic module, a mapping relation between the FC-AE-1553 control instruction serial numbers (at most 32 × 2) of the maximum number that may be theoretically generated and the FC-AE-1553 control instruction serial numbers (the number is not more than 256) actually stored in the stack of the programmable logic module each time is established. By the mapping mode, the number of effective FC-AE-1553 control instructions in the stack of the programmable logic module is effectively controlled, and the real-time performance and the reliability of the processing stack of the programmable logic module are ensured.

3. The host module informs the programmable logic module of the completion of message configuration and initiates message transmission

After the host module completes the configuration of the FC-AE-1553 control instruction, a handshake signal is sent to the programmable logic module through the PCIE bus to inform the FC-AE-1553 control instruction configuration completion, and the programmable logic module can start the sending work of the FC-AE-1553 control instruction in the stack.

In order to solve the problem that the host module sends the FC-AE-1553 control instruction to the programmable logic module, prevent the FC-AE-1553 control instruction from being covered or lost and improve the real-time performance and reliability of communication transmission between an upper computer and terminal simulator equipment, the invention provides a FC-AE-1553 bus protocol message communication method. The method comprises the following implementation steps:

s1: the host module receives and analyzes the upper computer control instruction

The host module dynamically applies for a memory space during initialization, stores 32 × 2 control instructions in the memory space, and initializes the serial number of each control instruction (the serial number is incremented from 0 and is not repeated).

And the host module stores the received upper computer control instruction in a message queue.

The host module takes out a message from the message queue, analyzes and processes the RT address, the RT sub-address, the data length, the data content and the message type in the message, and divides the message into two message messages of NC- > NT type and NT- > NC type. When processing information of a certain RT sub-address in the upper computer control instruction, storing a serial number distributed by the control instruction corresponding to the RT sub-address during initialization in an array A taking the received control instruction count as a subscript, adding one to the received control instruction count, and generating an FC-AE-1553 control instruction.

S2: the host module sends handshake signals and FC-AE-1553 control instructions to the programmable logic module

The host module sends a handshake signal to the programmable logic module through the PCIE bus to inform the programmable logic module to stop operating the current stack. After the programmable logic module processes all the control instructions in the stack, the control instructions are fed back to the host module through the PCIE bus, and after the host module receives a feedback signal of the programmable logic module, the host module resets the received control instruction count.

The host module stores the generated FC-AE-1553 control command, the received control command count and the content of the array A in a DDR data buffer area, informs the programmable logic module of being ready to receive data from the DDR data buffer area through a PCIE bus, and sends the initial address space, the data length, the received data source address and the received data destination address of the received data to the programmable logic module. After receiving a data receiving ready signal of the programmable logic module through the PCIE bus, the host module starts the DMA controller and sends data in the DDR buffer area to the programmable logic module in a DMA mode.

S3: the programmable logic module completes FC-AE-1553 control instruction receiving processing

After taking data in the DDR buffer area away, the programmable logic module sends a data receiving completion signal to the host module through the PCIE bus, the programmable logic module obtains the total number of control instructions stored in a stack according to a received control instruction count value, then obtains a sequence number value (array element content corresponding to the subscript of the array A and recorded as a V instruction) distributed by the control instruction during initialization according to a stack sequence number value (the subscript of the array A and recorded as a V stack), and stores an FC-AE-1553 control instruction with the sequence number value of the V instruction into a stack space with the sequence number value of the V stack. And the programmable logic module sends the received FC-AE-1553 control instruction message to the terminal simulator equipment through an FC-AE-1553 bus.

After receiving the "data reception complete" signal sent by the programmable logic module, the host module determines an interrupt status register of the main controller module, and if the interrupt status register indicates that the current FC-AE-1553 control instruction has been processed, the host module then takes out the upper computer control instruction sent by the next upper computer from the message queue, and starts to execute the processing from step S1.

Examples

(1) The main controller host module dynamically applies for a memory space during initialization, and is used for storing 32 × 2 control instructions, each control instruction comprises an RT sub-address message, the count of the initialized received control instruction is 0, and the serial number of each control instruction is initialized (the serial number of the control instruction is increased from 0, and all the serial numbers are not repeated); and receiving upper computer control instructions sent by an upper computer through the Ethernet, wherein each upper computer control instruction comprises RT subaddress information. And analyzing the upper computer control instruction, storing the serial number which is distributed during initialization of the control instruction corresponding to the RT subaddress in an array A taking the received control instruction count as a subscript when processing certain RT subaddress information, adding one to the received control instruction count, and generating an FC-AE-1553 control instruction. Finally, one or more generated FC-AE-1553 control instructions, the count of the received control instructions and the content of the array A are sent to a programmable logic module of the main controller in a DMA mode; the preferred scheme is as follows:

preferably, the following method is adopted to initialize the storage space of the control command in the host module of the main controller and number each control command:

when the main controller host module is initialized, a system malloc function is called to dynamically apply for a memory space for storing control instructions of different RT addresses and different RT sub-addresses, and each control instruction comprises an RT address and RT sub-address information in the RT address. Since the control instructions are divided into two types of NC- > NT and NT- > NC, the RT addresses are 32 at most, and the sub-addresses of each RT are 32 at most, so that the total number of the control instructions is 32 × 2. The main controller host module initializes the serial number of each control instruction (the serial number of the control instruction increases from 0, all the serial numbers are not repeated), and the numbering principle of the control instruction is as follows: for NC- > NT type, the sequence number of RT address 0 and RT sub-address 0 is 0, the sequence number of RT address 0 and RT sub-address 1 is 1, the sequence number of RT address 0 and RT sub-address 2 is 2, ·, the sequence number of RT address 0 and RT sub-address 31 is 31, the sequence number of RT address 1 and RT sub-address 0 is 32, the sequence number of RT address 1 and RT sub-address 1 is 33, the sequence number of RT address 1 and RT sub-address 2 is 34,..., the sequence number of RT address 1 and RT sub-address 31 is 63,..., the sequence number of RT address 31 and RT sub-address 0 is 992, the sequence number of RT address 31 and RT sub-address 1 is 993, the sequence number of RT address 31 and RT sub-address 2 is 994,. the sequence number of RT address 31 and RT sub-address 31 is 1023. For the NT- > NC type, the numbering principle is the same as that of the NC- > NC type, the serial number of the RT address 0 and the RT sub-address 0 is 1024, the numbering is increased, and the serial number of the RT address 31 and the RT sub-address 31 is 2047.

Preferably, the following method is adopted to analyze the upper computer control instruction and generate the FC-AE-1553 control instruction:

the format of the upper computer control command is composed of "command identification (2 bytes)" + "source identification (4 bytes)" + "sink identification (4 bytes)" + "command sequence number (2 bytes)" + "command length (2 bytes)" + "command valid field content (N bytes, N >0 and N is a positive integer multiple of 4)" + "checksum (2 bytes)". And calculating the checksum of the contents of the other fields except the 'checksum' field in the upper computer control instruction according to a CRC16 checking algorithm. The format of the "instruction valid field contents" is: the "RT address number (2 bytes)" + "RT address number n (n >0,2 bytes)" corresponding to the "RT address number" + "RT sub-address number 1(2 bytes)" + "RT sub-address number 1 data length (2 bytes)" + "RT sub-address number 1 data content (64 bytes)" + "RT sub-address number 2(2 bytes)" + "RT sub-address number 2 data length (2 bytes)" + "RT sub-address number 2 data content (64 bytes)" + … + "RT sub-address number n (2 bytes)" + "RT sub-address number n data length (2 bytes)" + "RT sub-address number n data content (64 bytes)". And the host module of the main controller judges the identifier of the upper computer control instruction, and if the current control instruction identifier indicates that the upper computer sends a bus control command to the terminal simulator equipment, the host module calculates and judges whether the length and the check sum of the current control instruction are correct or not. If the control instruction length and the checksum are both correct, the 'instruction effective field content' of the bus control command is extracted from the current control instruction.

Next, the 'instruction effective field content' needs to be split into one or more FC-AE-1553 control instructions, so that each FC-AE-1553 control instruction only contains information of one RT subaddress. Because each upper computer control instruction contains an RT address number and contains one or more pieces of RT sub-address number information corresponding to the RT address number. Therefore, the subaddress number, the data length and the data content of each RT subaddress are respectively extracted and stored according to the format of the 'instruction valid field content', and the data content of each RT subaddress is recorded as 'subaddress bus data'.

If the 'information source identifier' of the upper computer control instruction is an upper computer and the 'information sink identifier' is terminal simulator equipment, the type of the control instruction is 'NC- > NT'; if the 'information source identifier' of the upper computer control instruction is the terminal simulator equipment and the 'information sink identifier' is the upper computer, the type of the control instruction is 'NT- > NC'. In order to process a certain RT sub-address information in the upper computer control instruction, the main controller host module extracts the RT address number of the current instruction and any RT sub-address number corresponding to the RT address from the 'instruction effective field content', and obtains the serial number values of the current RT address number and the RT sub-address number by combining the type of the current control instruction ('NC- > NT' type or 'NT- > NC' type), wherein the serial number value is the serial number of the FC-AE-1553 control instruction. And storing the serial number value of the FC-AE-1553 control instruction in an array A taking the count of the received control instruction as a subscript, and adding one to the count of the received control instruction.

The format of the FC-AE-1553 data frame (FC-AE-1553 control instruction) consists of sections "SOF (data frame start)" + "data frame header" + "data field" + "CRC check" + "EOF (data frame end)". Wherein, the "SOF (start of data frame)" occupies 4 bytes, the "header of data frame" occupies 24 bytes, the "field of data" occupies 2112 bytes, and the "CRC check" occupies 4 bytes for detecting the data integrity of the "header of data frame" and the "field of data", excluding the "SOF" and the "EOF", and the "end of data frame" occupies 4 bytes. The main controller host module sets a source address sent by a data frame, a destination address sent by the data frame, a data frame sub-address (RT sub-address number) and a data frame length (RT sub-address data length) in a data frame header, fills the content of sub-address bus data into a data field, and generates one or more FC-AE-1553 control instructions according to the data frame format.

Preferably, the main controller host module sends the generated one or more FC-AE-1553 control instructions, the received control instruction count and the contents of the array a to the main controller programmable logic module in a DMA manner by adopting the following method:

the host module of the main controller stores one or more generated FC-AE-1553 control instructions, the received control instruction count and the content of the array A in a DDR data buffer area, and the host module of the main controller sends a handshake signal to the programmable logic module of the main controller through a PCIE bus to inform the programmable logic module of the main controller to stop the operation on the current stack. The host module of the main controller feeds back to the host module of the main controller through the PCIE bus after processing all control commands in the stack, after receiving a feedback signal of the host module of the main controller, the host module of the main controller clears the count of the received control commands, then informs the host module of the main controller through the PCIE bus that the programmable logic module is ready to receive data from the DDR data buffer area, and sends the initial address space, the data length, the source address and the destination address of the received data to the programmable logic module of the main controller. After receiving a data receiving ready signal of the main controller programmable logic module through the PCIE bus, the main controller host module starts a DMA controller and sends data in the DDR buffer area to the main controller programmable logic module in a DMA mode.

(2) And the main controller programmable logic module receives the FC-AE-1553 control instruction sent by the main controller host module, receives the control instruction count and the content of the array A, and stores the FC-AE-1553 control instruction into a stack. The received control instruction count is the number of control instructions in the stack of the programmable logic module of the main controller, the subscript of the array A is the serial number of each control instruction in the stack, and the array element content corresponding to the subscript of the array A is the serial number distributed by the control instruction during initialization. The main controller programmable logic module sends the received FC-AE-1553 control instruction to the bridge module through the optical fiber switch; the preferred scheme is as follows:

preferably, the FC-AE-1553 control instruction is saved in a stack by a main controller programmable logic module by adopting the following method:

the main controller programmable logic module obtains the total number of control instructions stored in the stack according to the received control instruction count value, and then the total number is recorded as V according to the stack number value (subscript of array A)_Stack) Obtaining the serial number value (array element content corresponding to the subscript of the array A, noted as V) allocated by the control instruction during initialization_Instructions) The serial number is V_InstructionsThe FC-AE-1553 control instruction is stored to be with a serial number value of V_StackWithin the stack space of (a).

(3) The bridge module converts the FC-AE-1553 control instruction through an MIL-STD-1553 protocol to generate an MIL-STD-1553 data instruction, and sends the generated MIL-STD-1553 data instruction to the terminal simulator equipment through an MIL-STD-1553 bus; the preferred scheme is as follows:

preferably, the FC-AE-1553 control instruction is converted into an MIL-STD-1553 protocol by adopting the following method to generate an MIL-STD-1553 data instruction:

the format of the FC-AE-1553 control instruction consists of sections "SOF (start of data frame)" + "data frame header" + "data field" + "CRC check" + "EOF (end of data frame)". Wherein, the "SOF (start of data frame)" occupies 4 bytes, the "header of data frame" occupies 24 bytes, the "field of data" occupies 2112 bytes, and the "CRC check" occupies 4 bytes for detecting the data integrity of the "header of data frame" and the "field of data", excluding the "SOF" and the "EOF", and the "end of data frame" occupies 4 bytes.

The MIL-STD-1553 data instruction sent by the bridge module to the terminal simulator device includes a command word and a data word. The command word is 20 bits and comprises a synchronization header (3 bits), a remote terminal address (5 bits), a T/R flag (1bit), a sub-address/mode (5 bits), a data word count/mode code (5 bits) and a parity bit (1 bit). The data word is 20 bits and includes a sync header (3 bits), data (16 bits) and parity (1 bit). Filling a data frame sub-address of a data frame header in an FC-AE-1553 control instruction into a sub-address/mode in a command word, filling a data frame length into a data word counting/mode code in the command word, setting a T/R mark as R (receiving), and setting a remote terminal address of the terminal simulator equipment, namely finishing the command word setting in an MIL-STD-1553 data instruction of the terminal simulator equipment. And extracting effective contents of a data field in the FC-AE-1553 control instruction as contents of each data word in an MIL-STD-1553 data instruction of the terminal simulator equipment. The conversion from the FC-AE-1553 control instruction to the MIL-STD-1553 data instruction is completed through the conversion from the FC-AE-1553 protocol to the MIL-STD-1553 protocol.

(4) The terminal simulator equipment sends the MIL-STD-1553 feedback data generated by the terminal simulator equipment to the bridge module through an MIL-STD-1553 bus; the preferred scheme is as follows:

(5) the bridge module receives MIL-STD-1553 feedback data sent by the terminal simulator equipment, generates FC-AE-1553 feedback data after the MIL-STD-1553 feedback data is subjected to FC-AE-1553 protocol conversion, and sends the generated FC-AE-1553 feedback data to the main controller programmable logic module through the optical fiber switch; the preferred scheme is as follows:

preferably, the bridge module converts the MIL-STD-1553 feedback data into FC-AE-1553 feedback data by the following method:

the format of the FC-AE-1553 feedback data consists of "SOF (start of data frame)" + "data frame header" + "data field" + "CRC check" + "EOF (end of data frame)" sections. Here, "SOF (start of data frame)" occupies 4 bytes, "header of data frame" occupies 24 bytes, "field of data" occupies 2112 bytes, "CRC check" occupies 4 bytes, and "EOF (end of data frame)" occupies 4 bytes. The bridge module sets a source address sent by a data frame, a destination address sent by the data frame, a data frame sub-address and a data frame length (the parameter value is the effective field content length of the MIL-STD-1553 feedback data generated by the terminal simulator device) in a data frame header, and fills the MIL-STD-1553 feedback data content generated by the terminal simulator device into a data field. FC-AE-1553 feedback data is generated in accordance with the data frame format described above.

(6) The main controller programmable logic module sends FC-AE-1553 feedback data to a main controller host module in a DMA mode; the preferred scheme is as follows:

preferably, the programmable logic module of the main controller sends the FC-AE-1553 feedback data to the main controller host module in a DMA manner by the following method:

after receiving FC-AE-1553 feedback data sent by the optical fiber switch, the main controller programmable logic module stores the FC-AE-1553 feedback data in a DDR data buffer area, informs a main controller host module through a PCIE bus that the data is ready to be received from the DDR data buffer area, and sends a starting address space, a data length, a received data source address and a received data destination address of the received data to the main controller host module. And after receiving the information, the host module of the main controller starts the DMA controller to acquire FC-AE-1553 feedback data stored in the DDR buffer area by the programmable logic module of the main controller in a DMA mode.

(7) After receiving FC-AE-1553 feedback data, the main controller host module performs packet processing on the FC-AE-1553 feedback data according to an Ethernet message to generate an upper computer feedback instruction, and sends the generated upper computer feedback instruction to an upper computer through the Ethernet; the communication between the upper computer and the terminal simulator equipment is realized; the preferred scheme is as follows:

preferably, the host module of the main controller performs packet processing on the FC-AE-1553 feedback data according to the ethernet packet by using the following method:

the main controller host module receives FC-AE-1553 feedback data sent by the main controller programmable logic module, and the format of the feedback data consists of a plurality of parts of 'SOF (data frame start)' + 'data frame header' + 'data field' + 'CRC check' + 'EOF (data frame end)'. Here, "SOF (start of data frame)" occupies 4 bytes, "header of data frame" occupies 24 bytes, "field of data" occupies 2112 bytes, "CRC check" occupies 4 bytes, and "EOF (end of data frame)" occupies 4 bytes. The main controller host module extracts the content of a 'data field' in FC-AE-1553 feedback data as message content, generates an upper computer feedback instruction according to the format of 'instruction identification (2 bytes)' + 'information source identification (4 bytes)' + 'information sink identification (4 bytes)' + 'instruction sequence number (2 bytes)' + 'instruction length (2 bytes)' + 'instruction effective field content (N bytes, N >0 and N is a positive integer multiple of 4)' + 'checksum (2 bytes)', wherein an 'instruction length' field is the length of effective data in a serial port feedback data packet, an 'instruction effective field content' field is the content of the 'data field' in the FC-AE-1553 feedback data, and a 'checksum' field is calculated by the content of other fields except the 'checksum' field according to a CRC16 checking algorithm, sending the generated upper computer feedback instruction to an upper computer through the Ethernet

According to the method, an avionic system test environment is built according to fig. 1, the period of upper computer control instructions sent by an upper computer to a main controller host module is 50ms, the number of RT addresses contained in each control instruction is 1, the number of RT sub-addresses contained in each RT address is 10, and the length of data in each sub-address is 64 bytes. The upper computer control instruction is divided into two types, that is, data is sent to and read from the terminal simulator device.

The data transmission condition on the MIL-STD-1553 bus is monitored through a bus analyzer, and the condition that an upper computer sends a control instruction is monitored through an Ethernet packet capturing tool. The test results are: the upper computer sends two types of control instructions according to the frequency, 6000 control instructions are sent to the main controller host module, and the terminal simulator equipment receives 60000 MIL-STD-1553 control instructions. The data content of the control command sent by the upper computer is completely consistent with the data content received by the terminal simulator equipment, and the terminal simulator equipment does not find the unexecuted control command.

The test results show that: according to the scheme of the invention, the communication between the upper computer and the terminal simulator equipment is carried out, the packet loss rate of the control command sent by the upper computer to the terminal simulator equipment is 0, the phenomenon that the FC-AE-1553 control command is covered or lost is completely avoided, the phenomenon that a host module and a programmable logic module access a shared storage area to read and write conflict is avoided, the condition that the resources of the programmable logic module of the main controller are in shortage is relieved to a certain extent, and the real-time performance and the reliability of the communication between the upper computer and the terminal simulator equipment are obviously improved.

Although the present invention has been described with reference to the preferred embodiments, it is not intended to limit the present invention, and those skilled in the art can make variations and modifications of the present invention without departing from the spirit and scope of the present invention by using the methods and technical contents disclosed above.

Claims

1. A FC-AE-1553 protocol message communication processing system is characterized in that: the system comprises an upper computer, a main controller host module, a main controller programmable logic module, an optical fiber switch, a bridge module and terminal simulator equipment;

2. The FC-AE-1553 protocol message communication processing system according to claim 1, wherein: before the message communication processing system works, the host module of the main controller is initialized, and the initialization processing method specifically comprises the following steps: dynamically applying for a block of memory space for storing 32 × 2 control instructions; each control instruction comprises RT sub-address information, the count of the initialized received control instruction is 0, and the serial number of each control instruction is initialized.

3. The FC-AE-1553 protocol message communication processing system according to claim 2, wherein: the control command sequence number is incremented from 0, and all sequence numbers are not repeated.

4. The FC-AE-1553 protocol message communication processing system according to claim 1, wherein: before the message communication processing system works, the main controller host module dynamically applies for a memory space for storing control instructions of different RT addresses and different RT sub-addresses transmitted by the upper computer; the RT address types are 32 at most, and each RT address corresponds to the RT sub-address type of 32 at most; then, the principle of the sequence number allocated by the control instruction corresponding to the RT sub-address during initialization is as follows:

5. The FC-AE-1553 protocol message communication processing system according to claim 1, wherein: the format of the upper computer control instruction is instruction identification, information source identification, information sink identification, instruction sequence number, instruction length, instruction effective field content and checksum; the content of the last word of the control instruction is a checksum, and the checksum is calculated according to the CRC16 check algorithm by using the content of the control instruction except the checksum.

6. The FC-AE-1553 protocol message communication processing system according to claim 5, wherein: the specific method for analyzing and processing the control instruction by the main controller host module comprises the following steps:

7. The FC-AE-1553 protocol message communication processing system according to claim 1, wherein: the host module of the main controller stores the generated FC-AE-1553 control instruction, the received control instruction count and the content of the array A in a DDR data buffer area, informs the programmable logic module of the main controller of being ready to receive data from the DDR data buffer area through a PCIE bus, and sends the initial address space, the data length, the received data source address and the received data destination address of the received data to the programmable logic module of the main controller.

8. The FC-AE-1553 protocol message communication processing system according to claim 7, wherein: and after receiving a data receiving and preparing signal of the programmable logic module of the main controller through the PCIE bus, the host module of the main controller starts the DMA controller and sends the data in the DDR buffer area to the programmable logic module of the main controller in a DMA mode.

9. The FC-AE-1553 protocol message communication processing system according to claim 8, wherein: after taking the data in the DDR buffer area, the main controller programmable logic module sends a data receiving completion signal to the main controller host module through the PCIE bus, and stores FC-AE-1553 control instructions in the DDR buffer area into a stack, and the receiving control instruction count in the DDR buffer area is used as the control instruction number in the stack of the main controller programmable logic module; the subscript of the array A in the DDR buffer area is used as the serial number of each control instruction in the stack, and the array element content corresponding to the subscript of the array A is the serial number allocated to the control instruction during initialization.

10. The FC-AE-1553 protocol message communication processing system according to claim 9, wherein: after receiving FC-AE-1553 feedback data sent by the optical fiber switch, the main controller programmable logic module stores the FC-AE-1553 feedback data in a DDR data buffer area, informs a main controller host module through a PCIE bus that the data is ready to be received from the DDR data buffer area, and sends a starting address space, a data length, a received data source address and a received data destination address of the received data to the main controller host module; and after receiving the information, the host module of the main controller starts the DMA controller to acquire FC-AE-1553 feedback data stored in the DDR buffer area by the programmable logic module of the main controller in a DMA mode.