CN103295642A - Shifting register and panel display - Google Patents
Shifting register and panel display Download PDFInfo
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- CN103295642A CN103295642A CN2012103529018A CN201210352901A CN103295642A CN 103295642 A CN103295642 A CN 103295642A CN 2012103529018 A CN2012103529018 A CN 2012103529018A CN 201210352901 A CN201210352901 A CN 201210352901A CN 103295642 A CN103295642 A CN 103295642A
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Abstract
The technical scheme of the invention provides a shifting register and a panel display. A control end of a first transistor of the shifting register receives a first clock signal, a first end of the first transistor receives an output signal or a starting signal of an upper-level shifting register, a second end of the first transistor is connected with a first end of a capacitor and a control end of a second transistor, a first end of the second transistor receives a second clock signal, a second end of the second transistor is connected with a second end of a capacitor, a first end of a third transistor, a first end of a fourth transistor and a control end of a fifth transistor and outputs an output signal of a local-level shifting register, a control end of the third transistor receives a first clock signal, a second end of the third transistor is connected with a second of the fourth transistor and a second end of the fifth transistor and receives a low-level signal, a control end of the fourth transistor is connected with a first end of the fifth transistor and a negative end of a transistor unit, and an anode end of the transistor unit receives the second clock signal.
Description
Technical field
The present invention relates to field of liquid crystal display, particularly a kind of shift register and panel display apparatus.
Background technology
In LCD (LCD), perhaps structure other flat-panel monitors similarly such as e-book, Organic Light Emitting Diode flexible display in, grid driving circuit and data drive circuit all are to attach on the display panel in assembling in the later stage, and the cost height of driving circuit, the assembling attachment process also will spend a large amount of operations, manpower and time.
In order to reduce cost, (Amorphous Silicon Gate, ASG) technology is suggested in the amorphous silicon gate could driving.The ASG technology is the non-display area that gate driver circuit is integrated in display panel synchronous in the flat-panel monitor manufacture process, for example frame region of display panels.Owing to adopt the ASG technology can save original gate driver circuit, improve integrated level, reduce outer member, reduce manufacturing cost, so the ASG technology is used more and more.
By each row pixel cell, the circuit structure that produces gate drive signal separately is called the ASG unit.The ASG unit has the structure of a shift register usually, whole ASG driving circuit be the ASG unit in the repetition of all row, or the interlacing of parity rows ASG unit repeats.The on-off element (for example thin film transistor (TFT) TFT) of the pixel cell in gate drive signal and the pel array is connected, and controls conducting and the disconnection of described on-off element.
As shown in Figure 1, the ASG driving circuit is made up of a series of ASG unit (shift register) 121.ASG unit 121 comprises input node IN, output node OUT, voltage source node V1 and clock signal node C1 and C2.Input node IN input start signal or upper level output signal STV, output node OUT exports output signal GoutN at the corresponding levels, voltage source node V1 input low level signal VGL, clock signal clk and the CLKB of clock signal node C1 and the complementation of C2 input phase.
As shown in Figures 2 and 3, low level signal VGL is always low level, and the course of work of ASG unit is roughly as follows:
Upper level output signal STV be high level, clock signal clk B be low level, when clock signal clk is high level: the clock signal clk of high level makes MOS transistor T1 and MOS transistor T3 conducting; After the MOS transistor T1 conducting, the P point voltage becomes the high level identical with upper level output signal STV; The high level that P is ordered makes MOS transistor T2 conducting; Low level low level signal VGL and clock signal clk B by conducting MOS transistor T2 and MOS transistor T3 to make output signal GoutN be low level.
Upper level output signal STV by high level become low level, clock signal clk B become high level, when clock signal clk becomes low level: low level clock signal clk ends MOS transistor T1 and MOS transistor T3; The high level that P is ordered is kept MOS transistor T2 conducting, and the clock signal clk B of high level makes output signal GoutN become high level by low level, and has increased the magnitude of voltage of P point high level by capacitor C t.
MOS transistor T3 is generally the following trombone slide of ASG unit, by the above-mentioned course of work as can be seen, clock signal clk be low level at present trombone slide be cut-off state.Clock signal clk be the low level time probably account for the whole cycle 50%, that is to say that following trombone slide is cut-off state all in time of 50% in whole cycle, the following trombone slide that ends causes output node OUT to be in floating dummy status.
The output node OUT of floating dummy status is crosstalked seriously by outer signals, the output signal instability, and the output waveform distortion is serious after certain progression.
Summary of the invention
What technical solution of the present invention solved is that the output node that has shift register now is subjected to outer signals to crosstalk seriously the output signal instability.
Technical solution of the present invention provides a kind of shift register, comprising: the first transistor, transistor seconds, the 3rd transistor, the 4th transistor, the 5th transistor, transistor unit and electric capacity;
The control end of described the first transistor receives first clock signal, and first termination is received output signal or the start signal of upper level shift register, and second end connects first end of described electric capacity and the control end of transistor seconds;
First termination of described transistor seconds is received the second clock signal, second end connects second end, the 3rd transistorized first end, the 4th transistorized first end and the 5th transistorized control end of described electric capacity, and second end of described transistor seconds is exported the output signal of shift register at the corresponding levels;
The described the 3rd transistorized control end receives described first clock signal, and second end connects the described the 4th transistorized second end and the described the 5th transistorized second end, and the described the 3rd transistorized second termination is received low level signal;
The described the 4th transistorized control end connects the negative pole end of the described the 5th transistorized first end and described unit;
The positive terminal of described transistor unit receives described second clock signal;
The conducting resistance of described transistor unit is greater than the described the 5th transistorized conducting resistance.
Optionally, described first clock signal is the complementary signal of described second clock signal, and described low level signal is less than or equal to the low level magnitude of voltage of described first clock signal.
Optionally, described shift register also comprises: the 7th transistor, and the described the 7th transistorized control end receives the output signal of next stage shift register, and first end connects first end of described electric capacity, and second termination is received described low level signal.
Optionally, described shift register also comprises: the 8th transistor, and the described the 8th transistorized control end receives described first clock signal, and first end connects the described the 4th transistorized control end, and second termination is received described low level signal.
Optionally, described transistor unit comprises the 6th transistor, the described the 6th transistorized control end connects the described the 6th transistorized first end as the positive terminal of described transistor unit, the described the 6th transistorized second end is as the negative pole end of described transistor unit, and the described the 6th transistorized conducting resistance is greater than the described the 5th transistorized conducting resistance.
Optionally, described transistor unit comprises diode, described diode cathode is as the positive terminal of described transistor unit, and described diode cathode is as the negative pole end of described transistor unit, and the conducting resistance of described diode is greater than the described the 5th transistorized conducting resistance.
Optionally, described transistor is MOS transistor, and described transistorized control end is the grid of described MOS transistor;
Source electrode, second end that described transistorized first end is described MOS transistor are the drain electrode of described MOS transistor, and perhaps described transistorized first end is described MOS transistor drain electrode, second end are the source electrode of described MOS transistor.
Optionally, the described the 5th transistorized breadth length ratio is greater than the described the 6th transistorized breadth length ratio.
Optionally, the described the 5th transistorized breadth length ratio is greater than five times of described the 6th transistorized breadth length ratio.
Technical solution of the present invention also provides a kind of panel display apparatus, comprising: pixel cell and above-mentioned shift register, described shift register are suitable for producing the required signal of described pixel cell.
Compared with prior art, after can producing a pulse in the output signal of shift register, technical solution of the present invention continues to keep the low level of output signal, prevent that floating dummy status from appearring in the shift register output node, avoids output signal crosstalked by outer signals, stable output signal.
Description of drawings
Fig. 1 is the structural representation of existing shift register;
Fig. 2 is a kind of structural representation of existing shift register cell;
Fig. 3 is the input/output signal waveform synoptic diagram of shift register cell shown in Figure 2;
Fig. 4 is enforcement one structural representation of shift register of the present invention;
Fig. 5 is the input/output signal waveform synoptic diagram of shift register shown in Figure 4;
Fig. 6 is enforcement two structural representations of shift register of the present invention;
Fig. 7 is enforcement three structural representations of shift register of the present invention;
Fig. 8 is the input/output signal waveform synoptic diagram of shift register cell shown in Figure 7.
Embodiment
Below in conjunction with accompanying drawing the specific embodiment of the present invention is described in detail.In the following passage, with way of example the present invention is described more specifically with reference to accompanying drawing.According to following explanation, advantages and features of the invention will be clearer.
As shown in Figure 4, the embodiment of the invention one provides a kind of shift register, comprising: the first transistor M1, transistor seconds M2, the 3rd transistor M3, the 4th transistor M4, the 5th transistor M5, transistor unit 11 and capacitor C 1.
The control end of described the first transistor M1 receives first clock signal clk, and first termination is received output signal or the start signal STV of upper level shift register, and second end connects first end of described capacitor C 1 and the control end of transistor seconds M2;
First termination of described transistor seconds M2 is received second clock signal CLKB, second end connects second end of described capacitor C 1, first end of the 3rd transistor M3, first end of the 4th transistor M4 and the control end of the 5th transistor M5, and second end of described transistor seconds M2 is exported the output signal GoutN of shift register at the corresponding levels;
The control end of described the 3rd transistor M3 receives described first clock signal clk, and second end connects second end of described the 4th transistor M4 and second end of described the 5th transistor M5, and second termination of described the 3rd transistor M3 is received low level signal VGL;
The control end of described the 4th transistor M4 connects first end of described the 5th transistor M5 and the negative pole end of described transistor unit 11;
The positive terminal of described transistor unit 11 receives described second clock signal CLKB;
The conducting resistance of described transistor unit 11 is greater than the conducting resistance of described the 5th transistor M5.
Described capacitor C 1 can stored charge and is played the on-off action of transistor seconds M2.
Described transistor unit 11 can comprise the 6th transistor M6, the control end of described the 6th transistor M6 connects first end of described the 6th transistor M6 as the positive terminal of described transistor unit 11, second end of described the 6th transistor M6 is as the negative pole end of described transistor unit 11, and the conducting resistance of described the 6th transistor M6 is greater than the conducting resistance of described the 5th transistor M5.
The conducting resistance of described the 6th transistor M6 can be greater than the conducting resistance of described the 5th transistor M5.Concrete, described the 5th transistor M5 and the 6th transistor M6 are MOS transistor, the breadth length ratio of described the 5th transistor M5 is greater than the breadth length ratio of described the 6th transistor M6.Optionally, the breadth length ratio of described the 5th transistor M5 is greater than five times of the breadth length ratio of described the 6th transistor M6.
Described transistor unit 11 also can comprise diode, described diode cathode is as the positive terminal of described transistor unit, described diode cathode is as the negative pole end of described transistor unit, and the conducting resistance of described diode is greater than the described the 5th transistorized conducting resistance.
In conjunction with Fig. 4 and Fig. 5, first clock signal clk of present embodiment one is the complementary signal of described second clock signal CLKB, and low level signal VGL is less than or equal to the low level magnitude of voltage of described first clock signal clk.The shift register course of work is roughly as follows:
The output signal of upper level shift register or start signal STV be high level, first clock signal clk be high level, when second clock signal CLKB is low level:
First clock signal clk of high level makes the first transistor M1 and the 3rd transistor M3 conducting, and low level clock signal clk B ends the 6th transistor M6; After the first transistor M1 conducting, the P point voltage becomes the high level identical with the output signal of upper level shift register or start signal STV; The high level that P is ordered makes transistor seconds M2 conducting; Low level low level signal VGL and second clock signal CLKB make output signal GoutN become low level by the 3rd transistor M3 and the transistor seconds M2 of conducting; Low level output signal GoutN ends the 5th transistor M5; Ending of the 5th transistor M5 and the 6th transistor M6 causes the Q point to present floating dummy status, and the Q point voltage value of floating dummy status can't make the 4th transistor M4 conducting between high level and low level, and the 4th transistor M4 ends.
The output signal of upper level shift register or start signal STV by high level to become low level, first clock signal clk be low level, when second clock signal CLKB is high level:
Low level first clock signal clk ends the first transistor M1 and the 3rd transistor M3, and the clock signal clk B of high level makes the 6th transistor M6 conducting; The high level that P is ordered is kept transistor seconds M2 conducting; The second clock signal CLKB of high level makes output signal GoutN become high level by low level, and has increased the magnitude of voltage of P point high level by capacitor C 1; The output signal GoutN of high level makes the 5th transistor M5 conducting, because the conducting resistance of the 6th transistor M6 is greater than the conducting resistance of the 5th transistor M5, so the Q point voltage keeps floating dummy status, the 4th transistor M4 ends.
It is high level that the output signal of upper level shift register or start signal STV keep low level, first clock signal clk, when second clock signal CLKB is low level:
First clock signal clk of high level makes the first transistor M1 and the 3rd transistor M3 conducting, and low level clock signal clk B ends the 6th transistor M6; After the first transistor M1 conducting, the P point voltage becomes the low level identical with the output signal of upper level shift register or start signal STV; The low level that P is ordered is ended transistor seconds M2; It is low level that the three transistor M3 of low level low level signal VGL by conducting makes output signal GoutN; Low level output signal GoutN ends the 5th transistor M5; The 5th transistor M5 and the 6th transistor M6's still is floating dummy status by causing the Q point voltage, and the 4th transistor M4 ends;
It is low level that the output signal of upper level shift register or start signal STV keep low level, first clock signal clk, when second clock signal CLKB is high level:
Low level first clock signal clk ends the first transistor M1 and the 3rd transistor M3, and the clock signal clk B of high level makes the 6th transistor M6 conducting; The low level that P is ordered is kept transistor seconds M2 and is ended, and output signal GoutN still is low level; Low level output signal GoutN makes the 5th transistor M5 remain off; The 6th transistor M6 of conducting makes the Q point voltage become the high level identical with second clock signal CLKB; The Q point voltage of high level makes the 4th transistor M4 conducting; It is low level that the four transistor M4 of low level signal VGL by conducting keeps output signal GoutN.
After this, the 6th transistor M6 is along with periodically conducting and end the cyclical variation between high level and floating dummy status of Q point of second clock signal CLKB.
By the above-mentioned course of work as can be seen, output signal GoutN keeps low level after producing a pulse always, when first clock signal clk is high level, low level signal VGL keeps the low level of output signal GoutN by the 3rd transistor M3 of conducting, when second clock signal CLKB was high level, low level signal VGL kept the low level of output signal GoutN by the 4th transistor M4 of conducting.Therefore, the technical scheme of using present embodiment one can prevent that the shift register output node from occurring floating dummy status, avoids output signal crosstalked by outer signals, stable output signal.
As shown in Figure 6, the embodiment of the invention two is also to comprise the 7th transistor M7 with the difference of embodiment one, the control end of described the 7th transistor M7 receives the output signal GoutN+1 of next stage shift register, first end connects first end of described capacitor C 1, and second termination is received described low level signal VGL.
Continuation is with reference to figure 5, the 7th transistor M7 conducting when the output signal GoutN+1 of next stage shift register is high level, the low level that low level signal VGL makes P order is more stable, the output signal of less upper level shift register or the influence of the burr on the start signal STV.
As shown in Figure 7, the embodiment of the invention three is also to comprise the 8th transistor M8 with the difference of embodiment one, the control end of described the 8th transistor M8 receives described first clock signal clk, and first end connects the control end of described the 4th transistor M4, and second termination is received described low level signal VGL.
As shown in Figure 8, the 6th transistor M6 conducting when second clock signal CLKB is high level, the second clock signal CLKB of high level makes the Q point voltage become high level by the 6th transistor M6 of conducting; The 8th transistor M8 conducting when first clock signal clk is high level, low level signal VGL makes the Q point voltage become low level by the 8th transistor M8 of conducting.Can avoid the Q point floating dummy status to occur like this, guarantee the periodicity conducting of the 4th transistor M4 and end, further stablize output signal GoutN.
The transistor of above-described embodiment can be MOS transistor, and described transistorized control end is the grid of described MOS transistor; Source electrode, second end that described transistorized first end is described MOS transistor are the drain electrode of described MOS transistor, and perhaps described transistorized first end is described MOS transistor drain electrode, second end are the source electrode of described MOS transistor.
The embodiment of the invention also provides a kind of panel display apparatus, comprising: the described shift register of pixel cell and above-described embodiment, the described shift register of above-described embodiment is suitable for producing the required signal of described pixel cell.
Though the present invention discloses as above with preferred embodiment, the present invention is defined in this.Any those skilled in the art without departing from the spirit and scope of the present invention, all can do various changes and modification, so protection scope of the present invention should be with claim institute limited range.
Claims (10)
1. a shift register is characterized in that, comprising: the first transistor, transistor seconds, the 3rd transistor, the 4th transistor, the 5th transistor, transistor unit and electric capacity;
The control end of described the first transistor receives first clock signal, and first termination is received output signal or the start signal of upper level shift register, and second end connects first end of described electric capacity and the control end of transistor seconds;
First termination of described transistor seconds is received the second clock signal, second end connects second end, the 3rd transistorized first end, the 4th transistorized first end and the 5th transistorized control end of described electric capacity, and second end of described transistor seconds is exported the output signal of shift register at the corresponding levels;
The described the 3rd transistorized control end receives described first clock signal, and second end connects the described the 4th transistorized second end and the described the 5th transistorized second end, and the described the 3rd transistorized second termination is received low level signal;
The described the 4th transistorized control end connects the negative pole end of the described the 5th transistorized first end and described transistor unit;
The positive terminal of described transistor unit receives described second clock signal;
The conducting resistance of described transistor unit is greater than the described the 5th transistorized conducting resistance.
2. shift register as claimed in claim 1 is characterized in that, described first clock signal is the complementary signal of described second clock signal, and described low level signal is less than or equal to the low level magnitude of voltage of described first clock signal.
3. shift register as claimed in claim 1, it is characterized in that, also comprise: the 7th transistor, the described the 7th transistorized control end receives the output signal of next stage shift register, first end connects first end of described electric capacity, and second termination is received described low level signal.
4. shift register as claimed in claim 1, it is characterized in that, also comprise: the 8th transistor, the described the 8th transistorized control end receives described first clock signal, first end connects the described the 4th transistorized control end, and second termination is received described low level signal.
5. shift register as claimed in claim 1, it is characterized in that, described transistor unit comprises the 6th transistor, the described the 6th transistorized control end connects the described the 6th transistorized first end as the positive terminal of described transistor unit, the described the 6th transistorized second end is as the negative pole end of described transistor unit, and the described the 6th transistorized conducting resistance is greater than the described the 5th transistorized conducting resistance.
6. shift register as claimed in claim 5, it is characterized in that, described transistor unit comprises diode, described diode cathode is as the positive terminal of described transistor unit, described diode cathode is as the negative pole end of described transistor unit, and the conducting resistance of described diode is greater than the described the 5th transistorized conducting resistance.
7. as the described shift register of the arbitrary claim of claim 1-6, it is characterized in that described transistor is MOS transistor, described transistorized control end is the grid of described MOS transistor;
Source electrode, second end that described transistorized first end is described MOS transistor are the drain electrode of described MOS transistor, and perhaps described transistorized first end is described MOS transistor drain electrode, second end are the source electrode of described MOS transistor.
8. shift register as claimed in claim 7 is characterized in that, the described the 5th transistorized breadth length ratio is greater than the described the 6th transistorized breadth length ratio.
9. shift register as claimed in claim 8 is characterized in that, the described the 5th transistorized breadth length ratio is greater than five times of described the 6th transistorized breadth length ratio.
10. a panel display apparatus is characterized in that, comprising: each described shift register of pixel cell and claim 1-9, each described shift register of claim 1-9 is suitable for producing the required signal of described pixel cell.
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| CN103295642B (en) | 2016-02-17 |
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