CN102368378B - Gate drive unit and gate drive circuit - Google Patents
Gate drive unit and gate drive circuit Download PDFInfo
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- CN102368378B CN102368378B CN201110279654.9A CN201110279654A CN102368378B CN 102368378 B CN102368378 B CN 102368378B CN 201110279654 A CN201110279654 A CN 201110279654A CN 102368378 B CN102368378 B CN 102368378B
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Abstract
The invention discloses a gate drive circuit, comprising multistage gate drive units which are connected in series, wherein each stage of the gate drive unit is used for outputting a corresponding gate drive signal to drive a corresponding gate line. Each stage of the gate drive unit comprises a latch, a high-level generating module, a first low-level generating module, a second low-level generating module and a coupling capacitor, and the gate drive signal output by each stage of the gate drive unit comprises high level generated by the high-level generating module, first low level generated by the first low-level generating module and second low level generated by the second low-level generating module, the gate drive single is configured to be in a third time frame of the first low level is determined by time difference between a second time frame and a fourth time frame corresponding to the high level in a first clock signal and a second clock signal, the first low level is smaller than the second low level so as to generate pull-back voltage, so that parasitic capacitance on the corresponding gate line can be compensated, and thus, a displayed image of the liquid display device can be prevented from generating a flicker phenomenon.
Description
Technical field
The present invention relates to display technique field, particularly relate to a kind of gate driver circuit for flat display apparatus and drive element of the grid thereof.
Background technology
Flat display apparatus, liquid crystal indicator (liquid crystal display for example, LCD) there is the plurality of advantages such as frivolous, energy-conservation, radiationless, therefore it has replaced traditional cathode-ray tube (CRT) (cathode ray tube gradually, CRT) display device, becomes the main flow of display device.Liquid crystal indicator has been widely used in each class of electronic devices such as Digital Television, computing machine, personal digital assistant, mobile phone and digital camera at present.
Thin film transistor (TFT) (thin film transistor, the TFT) liquid crystal indicator of take is example, and it mainly comprises display panels and driving circuit.Wherein, display panels comprises many gate lines and many data lines, and two adjacent gate lines mutually intersect and form a pixel cell with two adjacent data lines.Each pixel cell comprises respectively a thin film transistor (TFT) and a pixel electrode.Driving circuit comprises gate driver circuit and source electrode drive circuit, is electrically connected respectively with gate line and the data line of LCD intralamellar part.
The basic functional principle of existing liquid crystal indicator is: by gate driver circuit output gate drive signal, with the thin film transistor (TFT) sequentially every a line gate line being electrically connected to, open, then by source electrode drive circuit, corresponding data voltage is passed to respectively by the thin film transistor (TFT) of opening on the pixel electrode in the pixel cell of this row, thereby makes the pixel cell of this row show different GTGs.When the pixel cell of this row receives data voltage, the thin film transistor (TFT) that gate driver circuit is electrically connected to this row gate line cuts out, then thin film transistor (TFT) next line gate line being electrically connected to is opened, by source electrode drive circuit, corresponding data voltage is passed in the pixel cell of this row again,, the like.When the pixel cell of last column receives after data voltage, from the first row, start to receive corresponding data voltage again.This technology is commonly referred to as progressive scanning technology.
Existing known gate driver circuit is considered for complexity in circuits, generally adopts second order driving method.In second order driving circuit and driving method thereof, owing to having stray capacitance Cgd between the grid (gate) of thin film transistor (TFT) and drain electrode (drain), therefore it can produce feedthrough (feed through) voltage, the existence of feed-trough voltage (conventionally representing with Vth) can cause the display frame of liquid crystal indicator to produce flicker (flicker) phenomenon, does not utilize the display effect of liquid crystal indicator.Therefore urgently need to propose a kind of method addressing the aforementioned drawbacks.
Summary of the invention
The object of the invention is to, overcome the defect that existing drive element of the grid and gate driver circuit exist, and a kind of new drive element of the grid and gate driver circuit, technical matters to be solved are provided, be to avoid adopting the liquid crystal indicator display frame of above-mentioned gate driver circuit to produce the defect of scintillation.
The object of the invention to solve the technical problems realizes by the following technical solutions.
The invention provides a kind of drive element of the grid, for exporting a gate drive signal to drive a corresponding gate line.This drive element of the grid comprises that latch, high level produce module, the first low level produces module, the second low level generation module and coupling capacitance.This latch comprises first input end, the second input end and output terminal, wherein this first input end receives the upper level gate drive signal that initial driving signal or upper level drive element of the grid are exported, and this second input end receives the next stage gate drive signal that next stage drive element of the grid is exported.This high level produces module and comprises control end, input end and output terminal, and wherein this control end is electrically connected this output terminal of this latch, and this input end receives the first clock signal.This first low level produces module and comprises control end, input end and output terminal, and wherein this control end receives this next stage gate drive signal that this next stage drive element of the grid is exported, and this input end receives the first low level.This second low level produces module and comprises control end, input end and output terminal, and wherein this control end receives second clock signal, and this input end receives the second low level.This output terminal and this high level that this coupling capacitance is connected in parallel on this latch produce between this output terminal of module.Wherein, thereby this high level produces this output terminal of module, this first low level produces this output terminal of module and this output terminal that this second low level produces module is electrically connected to using and exports this gate drive signal as the output terminal of this drive element of the grid; This gate drive signal has this high level and produces high level, this first low level that module produces and produce this first low level and this second low level that module produces and produce this second low level that module produces, and this first low level is less than this second low level to produce the voltage of pulling back; This first clock signal and this second clock signal are comprised of this high level and this second low level respectively, and this high level produces this high level that module produces and provided by this high level of this first clock signal, this gate drive signal is corresponding the second period of this high level in this first clock signal and this second clock signal and the mistiming between the 4th period and determine in this first low level the 3rd period.
Preferably, this high level produces module and comprises the first on-off element, this first on-off element comprises the first control end, the first link and the second link, wherein this first control end produces this control end of module as this high level, this first link produces this input end of module as this high level, and this second link produces this output terminal of module as this high level.This first low level produces module and comprises second switch element, this second switch element comprises the second control end, the 3rd link and the 4th link, wherein this second control end produces this control end of module as this first low level, the 3rd link produces this input end of module as this first low level, and the 4th link produces this output terminal of module as this first low level.This second low level produces module and comprises the 3rd on-off element, the 3rd on-off element comprises the 3rd control end, the 5th link and the 6th link, wherein the 3rd control end produces this control end of module as this second low level, the 5th link produces this input end of module as this second low level, and the 6th link produces this output terminal of module as this second low level.
Preferably, this latch comprises the 4th on-off element and the 5th on-off element, the 4th on-off element comprises the 4th control end, the 7th link and the 8th link, and wherein the 4th control end is as this first input end of this latch, and the 7th link is electrically connected the 4th control end.The 5th on-off element comprises the 5th control end, the 9th link and the tenth link, wherein the 5th control end is electrically as this second input end of this latch, the 9th link receives this first low level, and the tenth link is electrically connected the 8th link of the 4th on-off element and electric connection point therebetween as this output terminal of this latch.
Preferably, this drive element of the grid further comprises the 6th on-off element, it comprises the 6th control end, the 11 link and the 12 link, wherein the first link of the 6th control end and the first on-off element is electrically connected, the 11 link is electrically connected this output terminal of this latch, and the 12 link is electrically connected this output terminal of this drive element of the grid.
Preferably, in this first clock signal, corresponding this second period of this high level equated with corresponding the 4th period of this high level in this second clock signal, and this gate drive signal is the twice of corresponding this second period of this high level in this first clock signal in this first low level the 3rd period.This first low level produces module and further comprises the 7th on-off element, it comprises the 7th control end, the 13 link and the 14 link, wherein the 7th control end receives the lower two-stage gate drive signal that lower two-stage drive element of the grid is exported, the 13 link receives this first low level, and the 14 link is electrically connected this output terminal of this drive element of the grid.
Preferably, in this first clock signal, corresponding this second period of this high level equated with corresponding the 4th period of this high level in this second clock signal, and this gate drive signal is the twice of corresponding this second period of this high level in this first clock signal in this first low level the 3rd period.This second low level produces module and further comprises the 8th on-off element, it comprises the 8th control end, the 15 link and the 16 link, wherein the 8th control end receives lower three grades of gate drive signals that lower three grades of drive element of the grid are exported, the 15 link receives this second low level, and the 16 link is electrically connected this output terminal of this drive element of the grid.
Preferably, in this first clock signal, corresponding this second period of this high level equated with corresponding the 4th period of this high level in this second clock signal, and this gate drive signal is the twice of corresponding this second period of this high level in this first clock signal in this first low level the 3rd period.This first low level produces module and further comprises the 7th on-off element, it comprises the 7th control end, the 13 link and the 14 link, wherein the 7th control end receives the lower two-stage gate drive signal that lower two-stage drive element of the grid is exported, the 13 link receives this first low level, and the 14 link is electrically connected this output terminal of this drive element of the grid.And this second low level produces module and further comprises the 8th on-off element, it comprises the 8th control end, the 15 link and the 16 link, wherein the 8th control end receives lower three grades of gate drive signals that lower three grades of drive element of the grid are exported, the 15 link receives this second low level, and the 16 link is electrically connected this output terminal of this drive element of the grid.
The present invention also provides a kind of gate driver circuit, comprises the drive element of the grid of plural serial stage, and the drive element of the grid of every one-level is drive element of the grid as above.
The present invention compared with prior art has obvious advantage and beneficial effect.
By technique scheme, drive element of the grid of the present invention and gate driver circuit at least have following advantages and beneficial effect:
The gate drive signal that drive element of the grid of the present invention and gate driver circuit are exported is consisted of high level, the first low level and the second low level, and voltage difference between the first low level and the second low level can produce the voltage of pulling back, with the feed-trough voltage that on the corresponding gate line of effective compensation, stray capacitance was caused, thus the scintillation of effectively avoiding liquid crystal indicator to produce when display frame.
Above-mentioned explanation is only the general introduction of technical solution of the present invention, in order to better understand technological means of the present invention, and can be implemented according to the content of instructions, and for above and other object of the present invention, feature and advantage can be become apparent, below especially exemplified by preferred embodiment, and coordinate accompanying drawing, be described in detail as follows.
Accompanying drawing explanation
Fig. 1 is the block schematic diagram of a kind of gate driver circuit of disclosing of a preferred embodiment of the present invention.
Fig. 2 is the schematic diagram of the every one-level drive element of the grid in the gate driver circuit that discloses of Fig. 1.
Fig. 3 is the physical circuit schematic diagram of the drive element of the grid shown in Fig. 2 in a preferred embodiment.
Fig. 4 is the sequential chart of each signal in drive element of the grid.
Fig. 5 is the physical circuit schematic diagram of the drive element of the grid shown in Fig. 2 in another preferred embodiment.
Fig. 6 is the physical circuit schematic diagram of the drive element of the grid shown in Fig. 2 in another preferred embodiment.
The physical circuit schematic diagram that Fig. 7 is the drive element of the grid shown in Fig. 2 in a preferred embodiment again.
Embodiment
For further setting forth the present invention, reach technological means and the effect that predetermined goal of the invention is taked, below in conjunction with accompanying drawing and preferred embodiment, drive element of the grid and its embodiment of gate driver circuit, method, step, structure, feature and effect thereof to proposing according to the present invention, be described in detail as follows.
Relevant aforementioned and other technology contents of the present invention, Characteristic can be known and present in the following detailed description coordinating with reference to graphic preferred embodiment.By the explanation of embodiment, when can be to reach technological means and the effect that predetermined object takes to be able to more deeply and concrete understanding to the present invention, yet appended graphic being only to provide with reference to the use with explanation be not used for the present invention to be limited.
Fig. 1 is the block schematic diagram of a kind of gate driver circuit of disclosing of a preferred embodiment of the present invention.As shown in Figure 1, gate driver circuit 100 of the present invention comprises the drive element of the grid 110 of plural serial stage, wherein, the output terminal of every one-level drive element of the grid 110 is electrically connected a corresponding gate line to drive this corresponding gate line, for example, the output terminal of n level drive element of the grid is electrically connected corresponding gate lines G n, to utilize gate drive signal Vgn that its output terminal is exported to control the opening and closing of the thin film transistor (TFT) being electrically connected with gate lines G n.
In addition the upper level gate drive signal that the output terminal that, every one-level drive element of the grid 110 receives initial driving signal STV or upper level drive element of the grid is exported.Particularly, first order drive element of the grid 110 receives start signal STV, but not the n level drive element of the grid 110 of the first order receives (n-1) level gate drive signal Vg (n-1) that the output terminal of (n-1) level drive element of the grid 110 exports (being the upper level gate drive signal that the output terminal of upper level drive element of the grid is exported), to determine according to initial driving signal STV or (n-1) level gate drive signal Vg (n-1) whether it works.
Fig. 2 is the schematic diagram of the every one-level drive element of the grid in the gate driver circuit that discloses of Fig. 1.As shown in Figure 2, drive element of the grid 110 of the present invention comprises that latch 111, high level produce module 112, the first low level produces module 113, the second low level generation module 114 and coupling capacitance 115.Latch 111 can be SR latch, it comprises first input end Set, the second input end Reset and output terminal Q, wherein first input end Set receives initial driving signal STV or upper level (i.e. (n-1) grade, n >=2) the upper level gate drive signal Vg (n-1) that drive element of the grid is exported, and the second input end Reset receives the next stage gate drive signal Vg (n+1) that next stage (i.e. (n+1) level) drive element of the grid is exported.High level produces module 112 and comprises control end, input end and output terminal, and wherein control end is electrically connected the output terminal Q of latch 111, and input end receives the first clock signal clk 1.The first low level produces module 113 and comprises control end, input end and output terminal, and wherein control end receives the next stage gate drive signal Vg (n+1) that next stage drive element of the grid is exported, and input end receives the first low level Vgl1.The second low level produces module 114 and comprises control end, input end and output terminal, and wherein control end receives second clock signal CLK2, and input end receives the second low level Vgl.Thereby high level produces the output terminal of module 112,, the output terminal that the output terminal of the first low level generation module 113 and the second low level produce module 114 is electrically connected, the output terminal D of usining as drive element of the grid 110 exports gate drive signal Vgn.Coupling capacitance 115 is connected in parallel between the output terminal Q of latch 111 and the output terminal D of drive element of the grid 110.
Fig. 3 is the physical circuit schematic diagram of the drive element of the grid shown in Fig. 2 in a preferred embodiment, and Fig. 4 is the sequential chart of each signal in above-mentioned drive element of the grid.As Figure 2-3, high level produces module 112 and can utilize the first on-off element and realize, as transistor T 1, at this, the grid of transistor T 1 (i.e. the first control end of the first on-off element) produces the control end of module 112 as high level, the source electrode of transistor T 1 (i.e. the first link of the first on-off element) produces the input end of module 112 as high level, and the drain electrode of transistor T 1 (i.e. the second link of the first on-off element) produces the output terminal of module 112 as high level.
The first low level produces module 113 and can utilize second switch element and realize, as transistor T 2, at this, the grid of transistor T 2 (being the second control end of second switch element) produces the control end of module 113 as the first low level, the source electrode of transistor T 2 (being the 3rd link of second switch element) produces the input end of module 113 as the first low level, and the drain electrode of transistor T 2 (being the 4th link of second switch element) produces the output terminal of module 113 as the first low level.
The second low level produces module 114 and can utilize the 3rd on-off element and realize, as transistor T 3, at this, the grid of transistor T 3 (i.e. the 3rd control end of the 3rd on-off element) produces the control end of module 114 as the second low level, the source electrode of transistor T 3 (i.e. the 5th link of the 3rd on-off element) produces the input end of module 114 as the second low level, and the drain electrode of transistor T 3 (i.e. the 6th link of the 3rd on-off element) produces the output terminal of module 114 as the second low level.
Latch 111 comprises the 4th on-off element and the 5th on-off element, and wherein the 4th on-off element can utilize transistor T 4 and realize, and the 5th on-off element can utilize transistor T 5 and realize.At this, the grid of transistor T 4 (i.e. the 4th control end of the 4th on-off element) is as the first input end Set of latch 111, and the grid of transistor T 5 (i.e. the 5th control end of the 5th on-off element) is as the second input end Reset of latch 111.In addition, the source electrode of transistor T 4 (i.e. the 7th link of the 4th on-off element) is electrically connected its grid, and its drain electrode (i.e. the 8th link of the 4th on-off element) is electrically connected with the drain electrode (i.e. the tenth link of the 5th on-off element) of transistor T 5, and its tie point is as the output terminal Q of latch 111.The source electrode of transistor T 5 (i.e. the 9th link of the 5th on-off element) receives the first low level Vgl1.
Preferably, in the present embodiment, drive element of the grid 110 further comprises the 6th on-off element, the 6th on-off element comprises the 6th control end, the 11 link and the 12 link, wherein, the 6th on-off element can utilize transistor T 6, the grid of transistor T 6 (i.e. the 6th control end of the 6th on-off element) is electrically connected with the first link of the first on-off element T1, receive the first clock signal clk 1 simultaneously, the source electrode of transistor T 6 (i.e. the 11 link of the 6th on-off element) is electrically connected the output terminal Q of this latch 111, and the drain electrode of transistor T 6 (i.e. the 12 link of the 6th on-off element) is electrically connected the output terminal D of drive element of the grid 110.
Preferably, above-mentioned transistor can be N-type transistor, for example nmos pass transistor.And initial driving signal STV, the first clock signal clk 1, second clock signal CLK2 form by high level Vgh and the second low level Vgl.And the first low level Vgl1 is less than the second low level Vgl.
The principle of work of the drive element of the grid 110 shown in Fig. 2-3 will specifically be introduced below.See also Fig. 2-4, when initial driving signal STV or upper level gate drive signal Vg (n-1) are in i.e. the first period of the corresponding period t1(of high level Vgh) time, now, transistor T 4 is opened, drive the high level Vgh in signal STV or upper level gate drive signal Vg (n-1) to charge to the drain electrode of transistor T 4, thereby by the voltage V on the output terminal Q of latch 111
qbe pulled up to high level Vgh.But because the first clock signal clk 1 is now in the second low level Vgl, although therefore transistor T 1 is latched the upper voltage V in high level Vgh of output terminal Q of device 111
qopen, the gate drive signal Vgn that its drain electrode (being the output terminal D of drive element of the grid 110) is exported is still in the second low level Vgl.
When the first clock signal clk 1 is from the second low level Vgl saltus step during to high level Vgh, simultaneously, initial driving signal STV or upper level gate drive signal Vg (n-1) saltus step are to low level (the second low level Vgl or the first low level Vgl1), and now, transistor T 4 starts to close.Now owing to there is no discharge path, so the voltage V that exports of the output terminal Q of latch 111
qor in high level Vgh, transistor T 1 continues to open, the gate drive signal Vgn saltus step that its drain electrode (being the output terminal D of drive element of the grid 110) is exported is to high level Vgh.And now, the gate drive signal Vgn exporting due to transistor T 1 drain electrode is that direct saltus step is to high level Vgh, and coupling capacitance 115 is connected in parallel between the output terminal Q of latch 111 and the drain electrode of transistor T 1, according to capacitance coupling effect, the voltage V that the output terminal Q of latch 111 exports
qalso high level Vgh that can saltus step to 2 times, thus make transistor T 1 maintain open mode, and the gate drive signal Vgn at the corresponding levels that the drain electrode of transistor T 1 is exported keeps high level Vgh.That is to say, at the first clock signal clk 1 in the corresponding period t2 of high level Vgh when (i.e. the second period), the voltage V that the output terminal Q of latch 111 exports
qin the level of the high level Vgh of 2 times, transistor T 1 maintains open mode, and the gate drive signal Vgn that its drain electrode (being the output terminal D of drive element of the grid 110) is exported is in high level Vgh.
Because the output voltage V gn of n level gate driver circuit is in high level, so next stage (i.e. n+1 level) gate driver circuit is opened and is carried out work.When the first clock signal clk 1 is during from high level Vgh to the second low level Vgl saltus step, now, next stage (i.e. n+1 level) drive element of the grid carries out next stage gate drive signal Vg (n+1) that work exports will be from the second low level Vgl saltus step to high level Vgh, therefore transistor T 5 conductings, by the voltage V on the output terminal Q of latch 111
qbe pulled down to the first low level Vgl1 to close transistor T 1.Meanwhile, transistor T 2 is opened, and the gate drive signal Vgn at the corresponding levels that the output terminal D of drive element of the grid 110 is exported is pulled down to the first low level Vgl1.In other words, when the first clock signal clk 1 is again in the second low level Vgl period t3 when (i.e. the 3rd period), the voltage V on the output terminal Q of latch 111
qbe pulled down to the first low level Vgl1, transistor T 1 is closed, and the gate drive signal Vgn at the corresponding levels that the output terminal D of drive element of the grid 110 exports is pulled down to the first low level Vgl1.
When second clock signal CLK2 is from the second low level Vgl saltus step during to high level Vgh, now, transistor T 3 is opened, and the gate drive signal Vgn at the corresponding levels that the output terminal D of drive element of the grid 110 exports is pulled to the second low level Vgl.In other words, when second clock signal CLK2 is in the period of high level t4 when (i.e. the 4th period), transistor T 3 is opened, so that the gate drive signal Vgn at the corresponding levels that the output terminal D of drive element of the grid at the corresponding levels 110 exports is pulled to the second low level Vgl.
Therefore the gate drive signal Vgn that, drive element of the grid 110 is exported is in the present invention that the high level Vgh, the first low level that by high level, are produced module 112 (being transistor T 1) and provided the second low level Vgl that the first low level Vgl1 that module 113 (being transistor T 2) provides and the second low level produce module 114 (being transistor T 3) and provide is provided is formed.
Because the first low level Vgl1 is less than the second low level Vgl, so voltage difference therebetween may be defined as the voltage Ve that pulls back.In addition, it will be understood by those skilled in the art that, the voltage Ve that pulls back also can be expressed as Ve=(Vgh-Vgl1) * Cgd/ (Cs-Cgd), wherein, Cgd is the grid of the upper thin film transistor (TFT) being electrically connected of n level drive element of the grid 110 corresponding gate lines G n and the capacitance of the stray capacitance between drain electrode, and Cs is the capacitance of the upper memory capacitance being electrically connected of n level drive element of the grid 110 corresponding gate lines G n.Therefore when the manufacture process of display panels and gate drivers definite after, can determine the occurrence of the voltage Ve that pulls back, thereby determine the relation between high level Vgh, the first low level Vgl1 and the second low level Vgl, according to actual needs, and definite this three's occurrence.
The voltage Ve that pulls back can compensate the grid of the thin film transistor (TFT) that corresponding gate lines G n is electrically connected and the feed-trough voltage that the stray capacitance Cgd between drain electrode causes effectively, therefore the gate drive signal Vgn that drive element of the grid 110 of the present invention is exported can improve the feed-trough voltage that the upper stray capacitance Cgd of corresponding gate lines G n causes effectively, thus the scintillation of effectively avoiding liquid crystal indicator to produce when display frame.
In addition the voltage V on the output terminal Q of latch 111,
qbe pulled down to after the first low level Vgl1, transistor T 1 is closed.But, it should be noted that, between the grid of transistor T 1 (being the output terminal Q of latch 111) and the source electrode (it is electrically connected the first clock signal clk 1) of transistor T 1, exist stray capacitance, therefore when (i.e. n level) drive element of the grid 110 at the corresponding levels quits work, the first clock signal clk 1 still mutually transforms always between high level Vgh and the second low level Vgl.When the first clock signal clk 1 is changed to high level Vgh from the second low level Vgl, because the stray capacitance between the grid of transistor T 1 and the source electrode of transistor T 1 produces capacitance coupling effect, so the voltage V on the grid of transistor T 1 (being the output terminal Q of latch 111)
qcan be drawn high.After the first clock signal clk 1 multiple oscillation, the voltage V on the output terminal Q of latch 111
qjust may be pulled up to higher voltage, thereby transistor T 1 is opened, the high level Vgh in the first clock signal clk 1 can export in gate drive signal Vgn, thereby makes gate drive signal Vgn produce abnormal waveform.
Generation for fear of above-mentioned situation, in the present embodiment, drive element of the grid 110 also further comprises the 6th on-off element, the 6th on-off element can utilize transistor T 6 to realize, wherein, the 6th the first link of the 6th control end (being the grid of transistor T 6) and the first on-off element T1 that opens the light element is electrically connected, the 11 link (being the source electrode of transistor T 6) is electrically connected to the output terminal Q of latch 111, and the 12 link (being the drain electrode of transistor T 6) is to the output terminal D of gate driver circuit 110.In the present invention, owing to being provided with the 6th on-off element (being transistor T 6), therefore when (i.e. n level) drive element of the grid 110 at the corresponding levels quits work, although the first clock signal clk 1 still mutually transforms between high level Vgh and the second low level Vgl always, at the first clock signal clk 1 during in high level Vgh, transistor T 6 can be unlocked, therefore between the output terminal Q of latch 111 and the drain electrode of transistor T 1, form discharge path, the upper electric charge producing due to capacitance coupling effect of the output terminal Q of latch 111 can be discharged by transistor T 6, thereby while guaranteeing that (i.e. n level) drive element of the grid 110 at the corresponding levels quits work, voltage V on the output terminal Q of latch 111
qcan stably maintain the first low level Vgl1, avoid turn-on transistor T1, the gate drive signal Vgn that (i.e. n level) drive element of the grid 110 at the corresponding levels is exported can not produce abnormal waveform.
In addition, please continue to refer to Fig. 4, the period t3 (i.e. three period) of the gate drive signal Vgn that drive element of the grid 110 is exported in the first low level Vgl1 in the first clock signal clk 1 in the corresponding period t2 of high level Vgh (i.e. the second period) and second clock signal CLK2 the mistiming between the corresponding period t4 of high level Vgh (i.e. the 4th period) determine.That is to say, those skilled in the art can be by regulating the pulse of the first clock signal clk 1 and second clock signal CLK2 to regulate the period t3 of gate drive signal Vgn in the first low level Vgl1.
Separately, it will be understood by those skilled in the art that, the source electrode of the transistor T 4 in latch 111 can not be electrically connected with its grid yet, but be directly electrically connected power supply, the direct supply that for example supply voltage is Vgh, with when transistor T 4 is opened, utilize direct supply Vgh and high level Vgh is provided.
Fig. 5 is the physical circuit schematic diagram of the drive element of the grid shown in Fig. 2 in another preferred embodiment.As shown in Figure 5, the first low level in drive element of the grid 200 produces module 230 except comprising transistor T 2, also comprises another on-off element (the 7th on-off element), as transistor T 7.The grid of transistor T 7 (i.e. the 7th control end of the 7th on-off element) receives the lower two-stage gate drive signal Vg (n+2) that lower two-stage drive element of the grid is exported, its source electrode (i.e. the 13 link of the 7th on-off element) also receives the first low level Vgl1, and its drain electrode (i.e. the 14 link of the 7th on-off element) is electrically connected the output terminal D of drive element of the grid 200.
In the present embodiment, can set the first clock signal clk 1 and in the period of high level Vgh t4 (i.e. the 4th period), equate with second clock signal CLK2 in the period of high level Vgh t2 (i.e. the second period), and the period t3 (i.e. three period) of gate drive signal Vgn at the corresponding levels in the first low level Vgl1 is the twice of the second period t2 of the first clock signal clk 1 in high level Vgh.
Therefore within the later half period of period t3, transistor T 2 is subject to the impact of next stage gate drive signal Vg (n+1) and closes, and stops the first low level Vgl1 to be passed to the output terminal D of drive element of the grid 200.But at this moment, transistor T 7 is subject to the impact of lower two-stage gate drive signal Vg (n+2) and opens, continue the first low level Vgl1 to be passed to the output terminal D of drive element of the grid 200.That is to say, in the 3rd period t3, transistor T 2 and transistor T 7 are alternately opened, to guarantee that the gate drive signal Vgn at the corresponding levels that the output terminal D of drive element of the grid 200 is exported can be stably in the first low level Vgl1.
Fig. 6 is the physical circuit schematic diagram of the drive element of the grid shown in Fig. 2 in another preferred embodiment.As shown in Figure 6, the second low level in drive element of the grid 300 produces module 340 except comprising transistor T 3, also comprises another on-off element (the 8th on-off element), as transistor T 8.The grid of transistor T 8 (i.e. the 8th control end of the 8th on-off element) receives lower three grades of gate drive signal Vg (n+3) that lower three grades of drive element of the grid are exported, its source electrode (i.e. the 15 link of the 8th on-off element) also receives the second low level Vgl, and its drain electrode (i.e. the 16 link of the 8th on-off element) is electrically connected the output terminal D of drive element of the grid 300.
In the present embodiment, can set the first clock signal clk 1 and in the period of high level Vgh t4 (i.e. the 4th period), equate with second clock signal CLK2 in the period of high level Vgh t2 (i.e. the second period), and the period t3 (i.e. three period) of gate drive signal Vgn at the corresponding levels in the first low level Vgl1 is the twice of the first clock signal clk 1 in the period of high level Vgh t2.
Therefore, at second clock signal CLK2 during in the period of high level Vgh t4, lower three grades of gate drive signal Vg (n+3) are also in high level Vgh, and transistor T 8 is also opened, thereby guarantee the second low level Vgl to be passed to the output terminal D of drive element of the grid 300 at this moment.In other words, at this moment, even if transistor T 3 is impaired, and transistor T 8 also can guarantee the second low level Vgl to be passed to the output terminal D of drive element of the grid 300.
Fig. 7 is the physical circuit schematic diagram in the preferred embodiment again of drive element of the grid shown in Fig. 2.As shown in Figure 7, the first low level in drive element of the grid 400 produces module 430 except comprising transistor T 2, also comprise transistor T 7 (consistent with the drive element of the grid 200 shown in Fig. 5), in addition, the second low level produces module 440 except comprising transistor T 3, also comprises transistor T 8 (consistent with the drive element of the grid 300 shown in Fig. 6).
In sum, the gate drive signal that drive element of the grid of the present invention and gate driver circuit are exported is consisted of high level, the first low level and the second low level, and voltage difference between the first low level and the second low level can produce the voltage of pulling back, with the feed-trough voltage that on the corresponding gate line of effective compensation, stray capacitance was caused, thus the scintillation of effectively avoiding liquid crystal indicator to produce when display frame.
The above, it is only preferred embodiment of the present invention, not the present invention is done to any pro forma restriction, although the present invention discloses as above with preferred embodiment, yet not in order to limit the present invention, any those skilled in the art, do not departing within the scope of technical solution of the present invention, when can utilizing the technology contents of above-mentioned announcement to make a little change or being modified to the equivalent embodiment of equivalent variations, in every case be not depart from technical solution of the present invention content, any simple modification of above embodiment being done according to technical spirit of the present invention, equivalent variations and modification, all still belong in the scope of technical solution of the present invention.
Claims (8)
1. a drive element of the grid, for exporting a gate drive signal to drive a corresponding gate line, is characterized in that: this drive element of the grid comprises:
Latch, it comprises first input end, the second input end and output terminal, wherein this first input end receives the upper level gate drive signal that initial driving signal or upper level drive element of the grid are exported, and this second input end receives the next stage gate drive signal that next stage drive element of the grid is exported;
High level produces module, and it comprises control end, input end and output terminal, and wherein this control end is electrically connected this output terminal of this latch, and this input end receives the first clock signal;
The first low level produces module, and it comprises control end, input end and output terminal, and wherein this control end receives this next stage gate drive signal that this next stage drive element of the grid is exported, and this input end receives the first low level;
The second low level produces module, and it comprises control end, input end and output terminal, and wherein this control end receives second clock signal, and this input end receives the second low level; And
Coupling capacitance, this output terminal and this high level that are connected in parallel on this latch produce between this output terminal of module;
Wherein, thereby this high level produces this output terminal of module, this first low level produces this output terminal of module and this output terminal that this second low level produces module is electrically connected to using and exports this gate drive signal as the output terminal of this drive element of the grid; This gate drive signal has this high level and produces high level, this first low level that module produces and produce this first low level and this second low level that module produces and produce this second low level that module produces, and this first low level is less than this second low level to produce the voltage of pulling back;
This first clock signal and this second clock signal are comprised of this high level and this second low level respectively, and this high level produces this high level that module produces and provided by this high level of this first clock signal, this gate drive signal is corresponding the second period of this high level in this first clock signal and this second clock signal and the mistiming between the 4th period and determine in this first low level the 3rd period.
2. drive element of the grid as claimed in claim 1, is characterized in that:
This high level produces module and comprises the first on-off element, this first on-off element comprises the first control end, the first link and the second link, wherein this first control end produces this control end of module as this high level, this first link produces this input end of module as this high level, and this second link produces this output terminal of module as this high level;
This first low level produces module and comprises second switch element, this second switch element comprises the second control end, the 3rd link and the 4th link, wherein this second control end produces this control end of module as this first low level, the 3rd link produces this input end of module as this first low level, and the 4th link produces this output terminal of module as this first low level; And
This second low level produces module and comprises the 3rd on-off element, the 3rd on-off element comprises the 3rd control end, the 5th link and the 6th link, wherein the 3rd control end produces this control end of module as this second low level, the 5th link produces this input end of module as this second low level, and the 6th link produces this output terminal of module as this second low level.
3. drive element of the grid as claimed in claim 2, is characterized in that: this latch comprises:
The 4th on-off element, it comprises the 4th control end, the 7th link and the 8th link, and wherein the 4th control end is as this first input end of this latch, and the 7th link is electrically connected the 4th control end;
The 5th on-off element, it comprises the 5th control end, the 9th link and the tenth link, wherein the 5th control end is as this second input end of this latch, the 9th link receives this first low level, and the tenth link is electrically connected the 8th link of the 4th on-off element and electric connection point therebetween as this output terminal of this latch.
4. drive element of the grid as claimed in claim 2, is characterized in that: it further comprises:
The 6th on-off element, it comprises the 6th control end, the 11 link and the 12 link, wherein the first link of the 6th control end and the first on-off element is electrically connected, the 11 link is electrically connected this output terminal of this latch, and the 12 link is electrically connected this output terminal of this drive element of the grid.
5. drive element of the grid as claimed in claim 2, it is characterized in that: in this first clock signal, corresponding this second period of this high level equated with corresponding the 4th period of this high level in this second clock signal, and this gate drive signal is the twice of corresponding this second period of this high level in this first clock signal in this first low level the 3rd period; And this first low level produces module and further comprises:
The 7th on-off element, it comprises the 7th control end, the 13 link and the 14 link, wherein the 7th control end receives the lower two-stage gate drive signal that lower two-stage drive element of the grid is exported, the 13 link receives this first low level, and the 14 link is electrically connected this output terminal of this drive element of the grid.
6. drive element of the grid as claimed in claim 2, it is characterized in that: in this first clock signal, corresponding this second period of this high level equated with corresponding the 4th period of this high level in this second clock signal, and this gate drive signal is the twice of corresponding this second period of this high level in this first clock signal in this first low level the 3rd period; And this second low level produces module and further comprises:
The 8th on-off element, it comprises the 8th control end, the 15 link and the 16 link, wherein the 8th control end receives lower three grades of gate drive signals that lower three grades of drive element of the grid are exported, the 15 link receives this second low level, and the 16 link is electrically connected this output terminal of this drive element of the grid.
7. drive element of the grid as claimed in claim 2, it is characterized in that: in this first clock signal, corresponding this second period of this high level equated with corresponding the 4th period of this high level in this second clock signal, and this gate drive signal is the twice of corresponding this second period of this high level in this first clock signal in this first low level the 3rd period; And this first low level produces module and further comprises the 7th on-off element, it comprises the 7th control end, the 13 link and the 14 link, wherein the 7th control end receives the lower two-stage gate drive signal that lower two-stage drive element of the grid is exported, the 13 link receives this first low level, and the 14 link is electrically connected this output terminal of this drive element of the grid; And this second low level produces module and further comprises the 8th on-off element, it comprises the 8th control end, the 15 link and the 16 link, wherein the 8th control end receives lower three grades of gate drive signals that lower three grades of drive element of the grid are exported, the 15 link receives this second low level, and the 16 link is electrically connected this output terminal of this drive element of the grid.
8. a gate driver circuit, comprises and it is characterized in that the drive element of the grid of plural serial stage: the drive element of the grid of every one-level is the drive element of the grid as described in claim 1-7 any one.
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| CN201110279654.9A CN102368378B (en) | 2011-09-20 | 2011-09-20 | Gate drive unit and gate drive circuit |
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| CN102800292B (en) * | 2012-08-21 | 2014-12-10 | 昆山龙腾光电有限公司 | Gate driving circuit |
| CN103151013B (en) * | 2013-03-07 | 2015-11-25 | 昆山龙腾光电有限公司 | Gate driver circuit |
| CN104008739B (en) | 2014-05-20 | 2017-04-12 | 深圳市华星光电技术有限公司 | Scan drive circuit and liquid crystal display |
| CN104570431B (en) * | 2015-01-29 | 2017-06-27 | 深圳市华星光电技术有限公司 | Liquid crystal display panel and liquid crystal display device |
| CN104992673B (en) | 2015-07-23 | 2017-09-22 | 京东方科技集团股份有限公司 | A kind of phase inverter, gate driving circuit and display device |
| TWI604429B (en) * | 2015-10-16 | 2017-11-01 | 瑞鼎科技股份有限公司 | Gate driving circuit |
| CN105469754B (en) * | 2015-12-04 | 2017-12-01 | 武汉华星光电技术有限公司 | Reduce the GOA circuits of feed-trough voltage |
| CN106971697A (en) * | 2017-05-16 | 2017-07-21 | 昆山龙腾光电有限公司 | Display device |
| CN109949755B (en) * | 2017-12-20 | 2021-04-09 | 咸阳彩虹光电科技有限公司 | Feed-through voltage compensation circuit and liquid crystal display device |
| TWI728783B (en) * | 2020-04-21 | 2021-05-21 | 友達光電股份有限公司 | Display device |
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