CN103248360A - Fractional-N PLL (phase locking loop) circuit and direct current frequency modulation method - Google Patents
Fractional-N PLL (phase locking loop) circuit and direct current frequency modulation method Download PDFInfo
- Publication number
- CN103248360A CN103248360A CN2013101805395A CN201310180539A CN103248360A CN 103248360 A CN103248360 A CN 103248360A CN 2013101805395 A CN2013101805395 A CN 2013101805395A CN 201310180539 A CN201310180539 A CN 201310180539A CN 103248360 A CN103248360 A CN 103248360A
- Authority
- CN
- China
- Prior art keywords
- frequency
- modulation
- phase
- signal
- fractional
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Images
Landscapes
- Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
Abstract
The invention provides a fractional-N PLL (phase locking loop) circuit and a direct current frequency modulation method for solving the problem that the low-modulation-rate signal frequency modulation cannot be carried out in the phase locking state. The fractional-N PLL circuit comprises a reference clock, a phase discriminator, an integrator, a voltage-controlled oscillator, a prescalar and a Sigma-Delta fractional divider, wherein one path of output signals of the voltage-controlled oscillator is directly output, the other path of the output signals of the voltage-controlled oscillator realizes the frequency division through the prescalar and the Sigma-Delta fractional divider, the phase discriminator carries out phase discrimination on reference signals output by the reference clock and the signals subjected to the frequency division, the integrator carries out integration filtering on the phase discrimination error signals output by the phase discriminator to generate voltage-controlled oscillator tuning error control signals, and the output signals of the voltage-controlled oscillator are controlled and are locked at the reference clock frequency. The direct current frequency modulation in the phase lock state is realized, the modulation precision is high, the modulation distortion rate is small, the modulation is convenient, the modulation frequency offset can realize the tiny step continuous change, and the control is precise.
Description
Technical field
The present invention relates to electronic technology field, particularly a kind of fractional frequency-division phase-locked loop circuit also relates to a kind of direct current frequency modulation method.
Background technology
Along with development of electronic technology, FM signal is used widely in modern communication, broadcasting and field of radar as basic modulation format signal.People have also carried out a large amount of research to the FM signal generation technique, what be most widely used at present is direct frequency modulation of the phase locking mode, as shown in Figure 1, phase-locked loop comprises reference clock 60, phase discriminator 40, integrator 30, voltage controlled oscillator VCO 20 and frequency divider 50, modulation signal 10 directly is added in the input of voltage controlled oscillator 20, and the output frequency of voltage controlled oscillator 20 is changed along with the variation of modulation signal.But because loop is high pass characteristic to modulation signal, so the modulation signal low-limit frequency will be higher than the loop cut-off frequency, the modulation signal that is lower than the loop cut-off frequency will be suppressed after through the loop effect.Usually the signal modulation that is lower than the loop cut-off frequency is called the direct current modulation, its modulation rate from DC to thousands of hertz.Therefore, frequency modulation(FM) how to carry out low frequency signal is problem demanding prompt solution.
The present phase-locked loop overwhelming majority does not have the direct current frequency modulation function, if realize direct current frequency modulation, the main method of taking at present is that frequency modulation(FM) is carried out in the phase-locked loop open loop.As shown in Figure 2, phase-locked loop comprises reference clock 60, phase discriminator 40, integrator 30, voltage controlled oscillator 20 and presets DAC 70, because loop is open loop, therefore there is not the loop affects of phase-locked loop closed loop, can directly add low-frequency modulation signal at voltage controlled oscillator and carry out direct current frequency modulation.Carry out frequency modulation(FM) under the phase-locked loop open loop situations, because the phase-locked loop open loop cause oscillator drift, so frequency modulation(FM) is of low quality, frequency modulation(FM) does not have practical function and meaning.
Summary of the invention
The present invention proposes the method for a kind of fractional frequency-division phase-locked loop circuit and direct current frequency modulation, to solve the problem that phase locked state can not carry out the modulation of low modulation rate signal frequency.
Technical scheme of the present invention is achieved in that
A kind of fractional frequency-division phase-locked loop circuit comprises: reference clock, phase discriminator, integrator, voltage controlled oscillator, prescalar and sigma-delta decimal frequency divider; The output signal of voltage controlled oscillator, one the tunnel directly exports, another route prescalar and sigma-delta decimal frequency divider are realized frequency division, phase discriminator after to frequency division signal and the reference signal of reference clock output carry out phase demodulation, integrator carries out integral filtering to the phase demodulation error signal of phase discriminator output, generate the voltage controlled oscillator tuning error controling signal, the output signal of control voltage controlled oscillator also is locked on the reference clock frequency it.
Alternatively, described sigma-delta decimal frequency divider is the FPGA circuit.
Alternatively, also comprise analog to digital converter and gain, biasing control module, gained by gain, biasing control module control modulation signal, and realize analog-to-digital conversion through analog to digital converter, export 16 position digital signals to described sigma-delta decimal frequency divider.
Alternatively, described gain, biasing control module are 12 figure place weighted-voltage D/A converters.
Alternatively, described sigma-delta decimal frequency divider also comprises register, stores 118 fractional frequency division ratios.
The present invention also provides a kind of and has carried out the method for direct current frequency modulation by above-mentioned fractional frequency-division phase-locked loop circuit, may further comprise the steps:
Step 2, gain control digital to analog converter during according to described maximum modulation frequency deviation put the relevant position that number and described 16 position datawires are carried in described register, other frequency modulation deviation parameters are regulated, calculate the position that number and described 16 position datawires are carried in described register of putting of the gain corresponding with this frequency modulation deviation control digital to analog converter.
The invention has the beneficial effects as follows: realized the direct current frequency modulation of phase locked state, the modulation accuracy height, modulation distortion is little, debugging is convenient, and frequency modulation can superfine stepping change, control accurately continuously.
Description of drawings
In order to be illustrated more clearly in the embodiment of the invention or technical scheme of the prior art, to do to introduce simply to the accompanying drawing of required use in embodiment or the description of the Prior Art below, apparently, accompanying drawing in describing below only is some embodiments of the present invention, for those of ordinary skills, under the prerequisite of not paying creative work, can also obtain other accompanying drawing according to these accompanying drawings.
Fig. 1 is existing direct frequency modulation of the phase locking circuit control block diagram;
Fig. 2 is direct current FM circuit control block diagram under the existing open loop situations;
Fig. 3 is the control block diagram of fractional frequency-division phase-locked loop circuit of the present invention;
Fig. 4 is the frequency modulation deviation and the figure place graph of a relation of fractional frequency division than register of fractional frequency-division phase-locked loop circuit of the present invention;
Fig. 5 is the flow chart of an embodiment of direct current frequency modulation method of the present invention.
Embodiment
Below in conjunction with the accompanying drawing in the embodiment of the invention, the technical scheme in the embodiment of the invention is clearly and completely described, obviously, described embodiment only is the present invention's part embodiment, rather than whole embodiment.Based on the embodiment among the present invention, those of ordinary skills belong to the scope of protection of the invention not making the every other embodiment that obtains under the creative work prerequisite.
As shown in Figure 3, fractional frequency-division phase-locked loop circuit according to the present invention comprises: reference clock 60, phase discriminator 40, integrator 30, voltage controlled oscillator 20, prescalar 80 and sigma-delta decimal frequency divider 90.
According to an embodiment of fractional frequency-division phase-locked loop circuit of the present invention, the frequency of voltage controlled oscillator 20 is 500MHz ~ 1000MHz, and the reference signal of reference clock 60 is 5MHz.During work, voltage controlled oscillator 20 produces 500MHz ~ 1000MHz signal, one the tunnel directly exports, another routing variable mould prescalar 80 and sigma-delta decimal frequency divider 90 are realized the N.F frequency division, signal and 5MHz reference signal behind 40 pairs of frequency divisions of phase discriminator are carried out phase demodulation, the phase demodulation error signal of 30 pairs of phase discriminators of integrator, 40 outputs is carried out integral filtering, generates the voltage controlled oscillator tuning error controling signal, and the output of control voltage controlled oscillator 20 also is locked on the 5MHz reference clock frequency it.For example the fractional frequency division ratio is 120, and then voltage controlled oscillator 20 output frequencies multiply by reference clock, i.e. 120*5MHz=600MHz for the fractional frequency division ratio.
The N.F frequency division adopts the pure digi-tal design, and all circuit of sigma-delta decimal frequency divider all are integrated in a slice FPGA the inside.Datain is that fractional frequency division send the number end than N.F, and the fractional frequency division among reception Fig. 3 is than N.F signal 120; CLK0 is the decimal frequency divider work clock, receives the reference signal of reference clock 60; Fin is input signal, receives the output signal of prescalar 80; Fout is the output signal behind the frequency division, carries out phase demodulation with the 5MHz reference signal; Not shown among MC1, MC2, SC1(Fig. 3) be the pattern control line of multimode prescalar 80, FMOD[15..0] be through 16 position digital signals after the analog to digital converter ADC 110 modulation signal A/D conversion.
Before sending the fractional frequency division ratio, earlier fractional frequency division select lines strobe is dragged down, when point is worked frequently, by Datain port serial input fractional frequency division ratio, the fractional frequency division ratio has 118, first is-symbol position, next 10 is integer-bit, be 48 decimal place then, this 59 bit data is placed on register qh[58..0] in, other purposes made in addition for last 59, be placed on register ql[58..0] in, the fractional frequency division ratio send and counts up to when finishing, and strobe is drawn high, and fractional frequency division is started working.
When carrying out direct current frequency modulation, direct current frequency modulation Enable Pin is drawn high, modulation signal through the data after the A/D conversion through 16 position datawire FMOD[15..0] with register qh[58..0] certain 16 bit data (for example qh[15..0]) addition, because modulation signal is periodic, so FMOD[15..0] also be periodic variation, causing the fractional frequency division ratio that same periodic the variation also taken place, is frequency modulation(FM) thereby make voltage controlled oscillator 20 output signals that same cycle variation also take place.Because modulation signal is to enter loop from phase discriminator 40, loop is low-pass characteristic under the phase locked state, so this modulation signal can be modulated on voltage controlled oscillator 20 output signals by loop and forms FM signal.
Through the data FMOD[15..0 after the ADC 110 modulation signal A/D conversion] directly be added in fractional frequency division than register qh[58..0] go up and produce frequency modulation, so frequency modulation deviation (i.e. the scope of modulation back FM signal offset carrier) mainly with FMOD[15..0] size variation and be added in register qh[58..0] the position relevant.Frequency modulation deviation as shown in Figure 4 and fractional frequency division are than register qh[58..0] the figure place relation, qh[48] be the integer frequency ratio lowest order, a reference frequency frequency modulation deviation; Qh[48] be 1/2 reference frequency frequency modulation deviation; Qh[0] be 1/2
48Individual reference frequency frequency modulation deviation.
Fractional frequency division is than register qh[58..0] in the 1st qh[58] be sign bit, ensuing 10 qh[57..48] be integer-bit, so qh[48] be the minimum integer-bit of fractional frequency division ratio, if reference frequency is 5MHz, qh[48 so] change to 1 from 0 and will cause voltage controlled oscillator 20 frequency change 5MHz, qh[47] change to 1 from 0 and will cause voltage controlled oscillator 20 frequency change 2.5MHz, rule successively, qh[0] change to 1 from 0 and will cause that voltage controlled oscillator 20 frequency change are 1/2
48* therefore 5MHz passes through FMOD[15..0] be added in qh[58..0] the position can accurately regulate frequency modulation.Owing to be added in qh[58..0] on FMOD[15..0] move forward and backward one, frequency modulation deviation changes 2 times or 1/2, frequency modulation deviation can not change continuously, be head it off, special gain, the biasing control module 100 of before ADC 110, having increased, for example by the gain of one 12 DAC control modulation signal, then modulation signal can 1/4096 ~ 4095/4096 change in gain, so modulation signal gain control and FMOD[15..0] be added in register qh[58..0] change in location combines and just realized the accurate continuous control of frequency modulation deviation.
The direct current frequency modulation method embodiment according to the present invention, fractional frequency-division phase-locked loop reference clock 5MHz, signal output 500MHz ~ 1000MHz, frequency modulation deviation DC ~ 8MHz, as shown in Figure 5, the specific implementation step is as follows:
Step 2, other frequency modulation deviation parameters gain DAC and the FMOD[15..0 during with the 8MHz frequency deviation] be added in register qh[48..33] the position regulate.For example, frequency modulation deviation 5MHz is set, this moment FMOD[15..0] be added in register qh[48..33] and on remain unchanged, gain DAC is set to 5MHz/8MHz*2000=1250, the frequency modulation deviation that modulate out this moment is 5MHz.When frequency modulation deviation arranges and to change from 8MHz toward 4MHz, FMOD[15..0] be added in register qh[48..33] on remain unchanged, the numerical value that only needs gain DAC changes toward 1000 from 2000 and gets final product.When frequency modulation deviation is set to 4MHz, this moment FMOD[15..0] after move one, be added in register qh[47..32] on, the value of DAC of gaining this moment reverts to 2000.Therefore when the frequency modulation deviation setting changes from 4MHz toward 2MHz, FMOD[15..0] be added in register qh[47..32] on remain unchanged, only need the numerical value of gain DAC to get final product from 2000 toward 1000 variations.When frequency modulation deviation is set to 2MHz, this moment FMOD[15..0] move one after again, be added in register qh[46..31] on, the value of the DAC that gains this moment reverts to 2000.And the like, as long as value and the FMOD[15..0 of the gain DAC when determining maximum frequency deviation 8MHz] be added in fractional frequency division than register qh[58..0] the position, just can regulate value and the FMOD[15..0 of gain DAC according to the frequency modulation deviation that arranges] be added in fractional frequency division than register qh[58..0] the position, accurately realize the frequency modulation of DC ~ 8MHz.
The present invention has realized the direct current frequency modulation of phase locked state, and the modulation accuracy height, modulation distortion is little, debugging is convenient, and frequency modulation can superfine stepping change, control accurately continuously.
The above only is preferred embodiment of the present invention, and is in order to limit the present invention, within the spirit and principles in the present invention not all, any modification of doing, is equal to replacement, improvement etc., all should be included within protection scope of the present invention.
Claims (6)
1. a fractional frequency-division phase-locked loop circuit is characterized in that, comprising: reference clock, phase discriminator, integrator, voltage controlled oscillator, prescalar and sigma-delta decimal frequency divider; The output signal of voltage controlled oscillator, one the tunnel directly exports, another route prescalar and sigma-delta decimal frequency divider are realized frequency division, phase discriminator after to frequency division signal and the reference signal of reference clock output carry out phase demodulation, integrator carries out integral filtering to the phase demodulation error signal of phase discriminator output, generate the voltage controlled oscillator tuning error controling signal, the output signal of control voltage controlled oscillator also is locked on the reference clock frequency it.
2. fractional frequency-division phase-locked loop circuit as claimed in claim 1 is characterized in that, described sigma-delta decimal frequency divider is the FPGA circuit.
3. fractional frequency-division phase-locked loop circuit as claimed in claim 2, it is characterized in that, also comprise analog to digital converter and gain, biasing control module, by gain, the gain of biasing control module control modulation signal, and through analog to digital converter realization analog-to-digital conversion, export 16 position digital signals to described sigma-delta decimal frequency divider.
4. fractional frequency-division phase-locked loop circuit as claimed in claim 3 is characterized in that, described gain, biasing control module are 12 figure place weighted-voltage D/A converters.
5. fractional frequency-division phase-locked loop circuit as claimed in claim 4 is characterized in that, described sigma-delta decimal frequency divider also comprises register, stores 118 fractional frequency division ratios.
6. one kind is carried out the method for direct current frequency modulation by the described fractional frequency-division phase-locked loop circuit of claim 5, it is characterized in that, may further comprise the steps:
Step 1, be that benchmark carries out parameter and regulates with the maximum modulation frequency deviation, the modulation signal amplitude of input is the 2V peak-to-peak value, and this input signal amplitude immobilizes in the whole modulated process, modulation signal gain control digital to analog converter is put number, output signal is loaded on the relevant position of register by 16 position datawires through 16 analog to digital converter conversion backs, observe frequency modulation deviation with receiver, and regulate the number of putting that described 16 position datawires are loaded into the position of described register or gain control digital to analog converter according to frequency modulation deviation;
Step 2, gain control digital to analog converter during according to described maximum modulation frequency deviation put the relevant position that number and described 16 position datawires are carried in described register, other frequency modulation deviation parameters are regulated, calculate the position that number and described 16 position datawires are carried in described register of putting of the gain corresponding with this frequency modulation deviation control digital to analog converter.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201310180539.5A CN103248360B (en) | 2013-05-16 | 2013-05-16 | A kind of fractional-N PLL circuit and direct current frequency modulation method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201310180539.5A CN103248360B (en) | 2013-05-16 | 2013-05-16 | A kind of fractional-N PLL circuit and direct current frequency modulation method |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN103248360A true CN103248360A (en) | 2013-08-14 |
| CN103248360B CN103248360B (en) | 2016-02-17 |
Family
ID=48927614
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201310180539.5A Active CN103248360B (en) | 2013-05-16 | 2013-05-16 | A kind of fractional-N PLL circuit and direct current frequency modulation method |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN103248360B (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104218948A (en) * | 2014-09-01 | 2014-12-17 | 长沙景嘉微电子股份有限公司 | Frequency modulation system for achieving wide-range modulation depth compensation |
| CN104617948A (en) * | 2014-12-19 | 2015-05-13 | 中国电子科技集团公司第二十四研究所 | Active amplitude-phase control circuit |
| CN106788418A (en) * | 2016-11-15 | 2017-05-31 | 中国电子科技集团公司第四十研究所 | A kind of signal source outside FM circuit and method |
Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1433152A (en) * | 2002-01-18 | 2003-07-30 | 诺基亚有限公司 | Decimal frequency-dividing synthesizer with sinusoidal generator |
| US7279993B2 (en) * | 2004-09-29 | 2007-10-09 | Stmicroelectronics S.R.L. | Phase-locked loop |
| CN101800544A (en) * | 2010-03-11 | 2010-08-11 | 华东师范大学 | Fractional frequency multimode multi-frequency phase locked loop frequency synthesizer |
| CN102769462A (en) * | 2011-05-06 | 2012-11-07 | 成都天奥电子股份有限公司 | Direct digital frequency phase-locked frequency multiplier circuit |
| CN102882536A (en) * | 2012-08-28 | 2013-01-16 | 叶松 | Radio frequency receiver of BeiDou radio determination satellite service (RDSS) satellite navigation system |
| CN102882520A (en) * | 2012-09-28 | 2013-01-16 | 兆讯恒达微电子技术(北京)有限公司 | Device and method for clock frequency division based on sigma-delta phase locked loop |
-
2013
- 2013-05-16 CN CN201310180539.5A patent/CN103248360B/en active Active
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1433152A (en) * | 2002-01-18 | 2003-07-30 | 诺基亚有限公司 | Decimal frequency-dividing synthesizer with sinusoidal generator |
| US7279993B2 (en) * | 2004-09-29 | 2007-10-09 | Stmicroelectronics S.R.L. | Phase-locked loop |
| CN101800544A (en) * | 2010-03-11 | 2010-08-11 | 华东师范大学 | Fractional frequency multimode multi-frequency phase locked loop frequency synthesizer |
| CN102769462A (en) * | 2011-05-06 | 2012-11-07 | 成都天奥电子股份有限公司 | Direct digital frequency phase-locked frequency multiplier circuit |
| CN102882536A (en) * | 2012-08-28 | 2013-01-16 | 叶松 | Radio frequency receiver of BeiDou radio determination satellite service (RDSS) satellite navigation system |
| CN102882520A (en) * | 2012-09-28 | 2013-01-16 | 兆讯恒达微电子技术(北京)有限公司 | Device and method for clock frequency division based on sigma-delta phase locked loop |
Non-Patent Citations (3)
| Title |
|---|
| CHIH-WEI YAO: "A 2.8-3.2-GHz Fractional-N Digital PLL With ADC-Assisted TDC and Inductively Coupled Fine-Tuning DCO", 《SOLID-STATE CIRCUITS》, vol. 48, no. 3, 31 March 2013 (2013-03-31), pages 698 - 710, XP011494561, DOI: doi:10.1109/JSSC.2012.2230543 * |
| 何攀峰，刘亮: "Σ-Δ调制小数分频器四模分频控制方法的分析与实现", 《国外电子测量技术》, vol. 27, no. 4, 30 April 2008 (2008-04-30) * |
| 吴鹏: "雷达伺服系统中DAC位数和数字PWM位数的选择", 《电讯技术》, vol. 46, no. 5, 31 May 2006 (2006-05-31), pages 178 - 182 * |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104218948A (en) * | 2014-09-01 | 2014-12-17 | 长沙景嘉微电子股份有限公司 | Frequency modulation system for achieving wide-range modulation depth compensation |
| CN104617948A (en) * | 2014-12-19 | 2015-05-13 | 中国电子科技集团公司第二十四研究所 | Active amplitude-phase control circuit |
| CN104617948B (en) * | 2014-12-19 | 2018-01-02 | 中国电子科技集团公司第二十四研究所 | Active width phase control circuit |
| CN106788418A (en) * | 2016-11-15 | 2017-05-31 | 中国电子科技集团公司第四十研究所 | A kind of signal source outside FM circuit and method |
| CN106788418B (en) * | 2016-11-15 | 2020-06-09 | 中国电子科技集团公司第四十一研究所 | External frequency modulation circuit and method for signal source |
Also Published As
| Publication number | Publication date |
|---|---|
| CN103248360B (en) | 2016-02-17 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN103490777B (en) | low spurious frequency synthesizer | |
| CN103647553B (en) | Direct current frequency modulation reference source circuit of broadband ultra low phase noise | |
| CN101039117B (en) | Rubidium atom frequency scale digital phase-locking frequency doubler | |
| CN103152034B (en) | Decimal frequency dividing phase-locked loop circuit and control method for frequency dividing ratio | |
| CN103178838A (en) | Device and method for frequency synthesis of phase-locked loop or phase-locked ring | |
| CN104320137B (en) | A kind of phase-locked loop frequency synthesizer | |
| CN106341122A (en) | Phase-locked loop having a multi-band oscillator and method for calibrating same | |
| CN102769462A (en) | Direct digital frequency phase-locked frequency multiplier circuit | |
| US6701445B1 (en) | Frequency control system that stabilizes an output through both a counter and voltage-controlled oscillator via sampling a generated clock into four states | |
| CN201008145Y (en) | Rubidium atom frequency scale digital phase-locked frequency multiplier | |
| CN204131498U (en) | A kind of phase-locked loop frequency synthesizer | |
| CN102210103A (en) | Frequency translation using sigma-delta modulator controlled frequency divide | |
| CN105375922B (en) | A kind of microwave signal source for miniature atomic clock | |
| CN204633753U (en) | Based on HMC835 broadband Low phase noise low spurious frequency hopping synthesizer | |
| CN104601171A (en) | Fractional divider and fractional frequency-division phase locked loop | |
| CN103248360B (en) | A kind of fractional-N PLL circuit and direct current frequency modulation method | |
| CN103684445A (en) | Multiphase high-resolution phase locked loop | |
| CN104300975A (en) | Decimal and integer frequency divider circuit and implementation method thereof | |
| CN103957008A (en) | Multi-ring frequency mixing phase locking frequency synthesis type S frequency band small-step frequency synthesizer | |
| CN102946249A (en) | Frequency synthesizer | |
| CN101567689B (en) | Phase-locked loop based on equivalent phase demodulation frequency | |
| CN109104187B (en) | Full-digital broadband frequency synthesizer | |
| CN101765974A (en) | Phase locking on aliased frequencies | |
| KR20160132446A (en) | Frequency synthesizer | |
| CN104333378A (en) | Fast phase locking low-noise signal generator and signal generation method |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| TR01 | Transfer of patent right | ||
| TR01 | Transfer of patent right |
Effective date of registration: 20190306 Address after: 266000 No. 98 Xiangjiang Road, Huangdao District, Qingdao City, Shandong Province Patentee after: China Electronics Technology Instrument and Meter Co., Ltd. Address before: 266000 No. 98 Xiangjiang Road, Qingdao economic and Technological Development Zone, Shandong Patentee before: The 41st Institute of CETC |
|
| CP03 | Change of name, title or address | ||
| CP03 | Change of name, title or address |
Address after: 266555 No. 98 Xiangjiang Road, Huangdao District, Qingdao City, Shandong Province Patentee after: CLP kesiyi Technology Co.,Ltd. Address before: 266000 No. 98 Xiangjiang Road, Huangdao District, Qingdao City, Shandong Province Patentee before: CHINA ELECTRONIC TECHNOLOGY INSTRUMENTS Co.,Ltd. |