CN101800544A - Fractional frequency multimode multi-frequency phase locked loop frequency synthesizer - Google Patents
Fractional frequency multimode multi-frequency phase locked loop frequency synthesizer Download PDFInfo
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- CN101800544A CN101800544A CN 201010122452 CN201010122452A CN101800544A CN 101800544 A CN101800544 A CN 101800544A CN 201010122452 CN201010122452 CN 201010122452 CN 201010122452 A CN201010122452 A CN 201010122452A CN 101800544 A CN101800544 A CN 101800544A
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Abstract
The invention discloses a fractional frequency multimode multi-frequency phase locked loop frequency synthesizer, comprising a phase detection discriminator, a charge pump, a low pass filter, a voltage-controlled oscillator, a high speed divided-by-2 frequency divider, a divided-by-2 frequency divider, a delta-sigma modulation multimode frequency divider, a mixer and the high speed divided-by-2 frequency divider. The fractional frequency multimode multi-frequency phase locked loop frequency synthesizer adopts a simple structure to realize output coverage of four frequency ranges used by TD-SCDMA, GSM, WLAN 802.11a and WLAN 802.11b/g, namely 1.8GHz-2GHz, 800MHz-960MHz, 2.4GHz-2.5GHz and 5GHz-6GHz. The selection of a circuit structure and parameters meets the requirements of communication systems TD-SCDMA, GSM, WLAN802.11b/g and WLAN802.11 on channel and noise.
Description
Technical field
The present invention relates to a kind of phase-locked loop frequency integrator, particularly a kind of fractional frequency multimode multi-frequency phase locked loop frequency synthesizer of increment summation modulation.
Background technology
In the communication system applications in early days, normally only meet the communication system of single standard, but along with the develop rapidly of wireless communication technology, new technology and standard emerge in an endless stream, make isolated network be connected future communications use in meaning limited.The user more wishes can be by the multimode terminal in the hand, optionally inserting suitable network according to oneself demand communicates, realize flexible, convenient, unlimited communication of freely linking up, development in future trend will be the continuous fusion between various wireless technologys, should switch fast between promptly following various wireless technologys.
In recent years, the combination of short distance wireless technical such as RFID (radio-frequency (RF) identification), bluetooth and Cellular Networks technology occurred, and derived a series of new business.For example in Hong Kong, the first property asset management solution that has merged RFID and 3G technology is tried out in the cyberport, and has reached shortening property management personnel inspection and the effect of response time.In recent years, company, research institute etc. endeavoured the technology and the product of the fusion of and broadband wireless technology mobile with research and development both at home and abroad, and research covers WLAN (wireless local area network) and the 2G/3G seamless connection is one of focus of the integrated research of current wireless technology.On specific implementation, present numerous mobile phones and notebook manufacturer begin to develop energetically bimodulus even three mould mobile phones, and the notebook computer of compatible these wireless technologys, and have begun successful Application.
In the system of these compatible various radio communications, the local oscillator module there is higher requirement, promptly the local oscillation signal generator can provide and meet the signal that each agreement frequency range requires, and comprises technical requirements such as operating frequency, signal bandwidth and phase noise.
Summary of the invention
The objective of the invention is to design the local oscillation signal generator of the compatible WLAN of a kind of energy (WLAN (wireless local area network)) 802.11a/b/g, GSM (global system for mobile communications) and TD-SCDMA (TD SDMA) communication system.
To achieve these goals, technical scheme of the present invention is on the basis of as shown in Figure 1 traditional local oscillation signal generator, realized a kind of phase-locked loop frequency integrator structure of fractional frequency division multiband output by increasing frequency divider and frequency mixer, realize covering in 800MHz～6GHz frequency range the frequency output of multiband, satisfy the local oscillator requirement of communication systems such as WLAN 802.11a/b/g, GSM and TD-SCDMA.
The object of the present invention is achieved like this:
A kind of fractional frequency multimode multi-frequency phase locked loop frequency synthesizer, this frequency synthesizer comprises phase detection discriminator U1, charge pump U2, low pass filter U3, voltage controlled oscillator U4, high speed two-divider U5, two-divider U6, increment summation modulation multi-modulus frequency divider U7, frequency mixer U8 and high speed two-divider U9, described phase detection discriminator U1 has two inputs, one end is input IN end, the other end is connected with the output of increment summation modulation multi-modulus frequency divider U7, the input signal of IN end is a reference frequency signal, and the crystal oscillator outer by sheet provides.
The input of described charge pump U2 is connected with the output of phase detection discriminator U1, and the output of charge pump U2 is connected with the input of low pass filter U3.
The output of described low pass filter U3 is connected with the input of voltage controlled oscillator U4.
Two outputs of described voltage controlled oscillator U4 are that the OUT end is connected respectively with two inputs of high speed two-divider U5 with the OUTB end, and the signal of OUT end and OUTB end is a differential signal.
Two outputs of described high speed two-divider U5 are OUT1 end and OUT1B end, and the output signal of OUT1 end and OUT1B end is a differential signal.
The output OUT1B end of the input of described two-divider U6 and high speed two-divider U5 is connected, and the output of two-divider U6 is OUT2 end and OUT2B end, and the output signal of OUT2 end and OUT2B end is a differential signal.
The input of described increment summation modulation multi-modulus frequency divider U7 and the output OUT2B end of two-divider U6 are connected, and the input of output and phase detection discriminator U1 is connected.
The input of described frequency mixer U8 is that the OUT1 end is connected with the OUT1B end with the output OUT end of voltage controlled oscillator U4 and the output of OUTB end, high speed two-divider U5 respectively, the output of frequency mixer U8 is OUT3 end and OUT3B end, and the output signal of OUT3 end and OUT3B end is a differential signal.
The input of described high speed two-divider U9 is connected with the output OUT3 of frequency mixer U8 end, and the output of high speed two-divider U9 is OUT4 end and OUT4B end, and the output signal of OUT4 end and OUT4B end is a differential signal.
Among the present invention, the frequency range of supposing voltage controlled oscillator U4 is f
1～f
2, under the pll lock situation, the output signal frequency scope of high speed two-divider U5 is [f
1/ 2, f
2/ 2], the output signal frequency scope of two-divider U6 is [f
1/ 4, f
2/ 4], the output signal frequency scope of frequency mixer U8 is [1.5f
1, 1.5f
2], the output signal frequency scope of high speed two-divider U9 is [0.75f
1, 0.75f
2].
Fractional frequency multimode multi-frequency phase locked loop frequency synthesizer of the present invention, the operating frequency of its voltage controlled oscillator U4 is 3GHz～4GHz, then the output signal frequency of high speed two-divider U5 is 1.5GHz～2GHz, the output signal frequency of two-divider U6 is 750MHz～1GHz, the output signal frequency of frequency mixer U8 is 4.5GHz～6GHz, the output signal frequency of high speed two-divider U9 is 2.25GHz～3GHz, satisfies the frequency requirement that TD-SCDMA, GSM, WLAN 802.11a and WLAN 802.11/b/g use respectively.
The invention has the advantages that:
(1), the present invention is by on the basis of conventional phase locked loops frequency synthesizer, increase a frequency mixer U8 and three two-divider U5, U6, U9, adopt simple structure to realize that the frequency of four frequency ranges that TD-SCDMA, GSM, WLAN 802.11a and WLAN 802.11/b/g use covers.
(2), the present invention is by using loop parameter and Noise Estimation algorithm, guarantees that parameters such as phase noise and settling time satisfy the requirement of different agreement.
Description of drawings
Fig. 1 is existing fractional frequency-division phase-locked loop frequency synthesizer electrical schematic diagram
Fig. 2 is a fractional frequency multimode multi-frequency phase locked loop frequency synthesizer electrical schematic diagram of the present invention
Embodiment
Below; will the present invention is described further by specific embodiment; yet embodiment only is giving an example of alternative embodiment of the present invention, and its disclosed feature only is used for explanation and sets forth technical scheme of the present invention, and is not intended to limit the scope of the invention.
Consult Fig. 2, the circuit structure and the course of work of fractional frequency multimode multi-frequency phase locked loop frequency synthesizer of the present invention now is described in detail in detail.
The present invention includes phase detection discriminator U1, charge pump U2, low pass filter U3, voltage controlled oscillator U4, high speed two-divider U5, two-divider U6, increment summation modulation multi-modulus frequency divider U7, frequency mixer U8 and high speed two-divider U9.
Described phase detection discriminator U1 realizes the reference frequency f of IN end input
RefCarry out frequency and bit comparison mutually, reference frequency f with the OUT1 end of high speed two-divider U5 with the output signal of OUT1B end
RefThe 20MHz crystal oscillator outer by sheet provides.Frequency comparative result according to reference signal and high speed two-divider U5, the switch of the output signal control charge pump U2 of phase detection discriminator U1, produce the pulsating direct current signal through low pass filter U3 output back, this signal is the control signal of voltage controlled oscillator U4, the centre frequency of described voltage controlled oscillator U4 is 3.5GHz, frequency range is designed to 3GHz～4GHz, the differential signal of voltage controlled oscillator U4 output produces the differential signal of 1.5GHz～2GHz behind high speed two-divider U5 frequency division, consider design margin, this frequency range satisfies the requirement that TD-SCDMA uses.
Described increment summation modulation multi-modulus frequency divider U7 adopts increment summation adjustment technology, by adopting oversampling technique to reduce in-band noise, and can shift the noise that frequency divider is introduced onto high band from low-frequency range by the noise shaping function, use the loop filter filtering then, reach the purpose that reduces noise.The increment summation modulation multi-modulus frequency divider that the present invention adopts can satisfy the requirement of the strictest GSM channel width, also can satisfy the noise requirements of communication systems such as WLAN802.11a/b/g, GSM and TD-SCDMA.The frequency division scope of described increment summation modulation multi-modulus frequency divider U7 is 75～100, to satisfy the frequency range requirement of communication system such as WLAN 802.11a/b/g, GSM and TD-SCDMA under the pll lock condition.
The differential signal frequency that the output signal of described high speed two-divider U5 is exported behind two-divider U6 is 750MHz～1GHz, considers design margin, and this frequency range satisfies the frequency range requirement that GSM uses.
The output signal of the output signal of described voltage controlled oscillator U4 and high speed two-divider U5 is as the input signal of frequency mixer U8, produce the differential signal of 4.5GHz～6GHz at the output of frequency mixer U8, consider design margin, this frequency range satisfies the application requirements of WLAN 802.11a.
The output signal of described frequency mixer U8 produces the differential signal of 2.25GHz～3GHz behind high speed two-divider U9, consider design margin, and this frequency range satisfies the application requirements of WLAN 802.11b/g.
Among the present invention, the output of high speed two-divider U5, two-divider U6, frequency mixer U8 and high speed two-divider U9 produces respectively and satisfies TD-SCDMA, GSM, WLAN802.11a and the required local oscillator differential signal of WLAN 802.11b/g application.In zero intermediate frequency receive-transmit system structure, the output of high speed two-divider U5, two-divider U6, frequency mixer U8 and high speed two-divider U9 should be designed to orthogonal differential output according to system requirements.
Foregoing is exemplifying of specific embodiments of the invention, for the wherein not equipment of detailed description and structure, should be understood to take existing common apparatus in this area and universal method to be implemented.
Claims (1)
1. fractional frequency multimode multi-frequency phase locked loop frequency synthesizer, it is characterized in that: this frequency synthesizer comprises phase detection discriminator (U1), charge pump (U2), low pass filter (U3), voltage controlled oscillator (U4), high speed two-divider (U5), two-divider (U6), increment summation modulation multi-modulus frequency divider (U7), frequency mixer (U8) and high speed two-divider (U9), described phase detection discriminator (U1) has two inputs, one end is input IN end, the other end is connected with the output of increment summation modulation multi-modulus frequency divider (U7), the input signal of IN end is a reference frequency signal, and the crystal oscillator outer by sheet provides; The input of described charge pump (U2) is connected with the output of phase detection discriminator (U1), and the output of charge pump (U2) is connected with the input of low pass filter (U3); The output of described low pass filter (U3) is connected with the input of voltage controlled oscillator (U4); Two outputs of described voltage controlled oscillator (U4) are that the OUT end is connected respectively with two inputs of high speed two-divider (U5) with the OUTB end, and the signal of OUT end and OUTB end is a differential signal; Two outputs of described high speed two-divider (U5) are OUT1 end and OUT1B end, and the output signal of OUT1 end and OUT1B end is a differential signal; The output OUT1B end of the input of described two-divider (U6) and high speed two-divider (U5) is connected, and the output of two-divider (U6) is OUT2 end and OUT2B end, and the output signal of OUT2 end and OUT2B end is a differential signal; The input of described increment summation modulation multi-modulus frequency divider (U7) and the output OUT2B of two-divider (U6) end are connected, and an input of output and phase detection discriminator (U1) is connected; The input of described frequency mixer (U8) is that the OUT1 end is connected with the OUT1B end with the output OUT end of voltage controlled oscillator (U4) and the output of OUTB end, high speed two-divider (U5) respectively, the output of frequency mixer (U8) is OUT3 end and OUT3B end, and the output signal of OUT3 end and OUT3B end is a differential signal; The output OUT3 end of the input of described high speed two-divider (U9) and frequency mixer (U8) is connected, and the output of high speed two-divider (U9) is OUT4 end and OUT4B end, and the output signal of OUT4 end and OUT4B end is a differential signal.
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102025367A (en) * | 2010-08-31 | 2011-04-20 | 华东师范大学 | Third-order single ring sigma-delta modulator with configurable zero point |
| CN103248360A (en) * | 2013-05-16 | 2013-08-14 | 中国电子科技集团公司第四十一研究所 | Fractional-N PLL (phase locking loop) circuit and direct current frequency modulation method |
| CN106526582A (en) * | 2015-08-28 | 2017-03-22 | 德尔福技术有限公司 | Bi-static radar system |
| US11543509B2 (en) | 2015-08-28 | 2023-01-03 | Aptiv Technologies Limited | Bi-static radar system |
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|---|---|---|---|---|
| US5579184A (en) * | 1993-06-17 | 1996-11-26 | Nec Corporation | Playback clock signal generating circuit which uses a first and second phase lock loop |
| CN101547008A (en) * | 2009-04-30 | 2009-09-30 | 复旦大学 | Frequency synthesizer covering ultra wideband 4 to 5GHz and 6 to 9GHz frequency points |
| CN101662436A (en) * | 2008-08-27 | 2010-03-03 | 中国科学院微电子研究所 | Frequency synthesizer used in dual carrier OFDM UWB |
-
2010
- 2010-03-11 CN CN 201010122452 patent/CN101800544A/en active Pending
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5579184A (en) * | 1993-06-17 | 1996-11-26 | Nec Corporation | Playback clock signal generating circuit which uses a first and second phase lock loop |
| CN101662436A (en) * | 2008-08-27 | 2010-03-03 | 中国科学院微电子研究所 | Frequency synthesizer used in dual carrier OFDM UWB |
| CN101547008A (en) * | 2009-04-30 | 2009-09-30 | 复旦大学 | Frequency synthesizer covering ultra wideband 4 to 5GHz and 6 to 9GHz frequency points |
Non-Patent Citations (1)
| Title |
|---|
| 《IEEE JOURNAL OF SOLID-STATE CIRCUITS》 19930531 Tom A.D.Riley et al. Delta-Sigma Modulation in Fractional-N Frequency Synthesis 555页第2列第1段至第556页第1列倒数第1段以及附图4 1 第28卷, 第5期 2 * |
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102025367A (en) * | 2010-08-31 | 2011-04-20 | 华东师范大学 | Third-order single ring sigma-delta modulator with configurable zero point |
| CN103248360A (en) * | 2013-05-16 | 2013-08-14 | 中国电子科技集团公司第四十一研究所 | Fractional-N PLL (phase locking loop) circuit and direct current frequency modulation method |
| CN103248360B (en) * | 2013-05-16 | 2016-02-17 | 中国电子科技集团公司第四十一研究所 | A kind of fractional-N PLL circuit and direct current frequency modulation method |
| CN106526582A (en) * | 2015-08-28 | 2017-03-22 | 德尔福技术有限公司 | Bi-static radar system |
| CN106526582B (en) * | 2015-08-28 | 2022-10-04 | 安波福技术有限公司 | Double base Radar system |
| US11543509B2 (en) | 2015-08-28 | 2023-01-03 | Aptiv Technologies Limited | Bi-static radar system |
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Application publication date: 20100811 |