CN103247337B - 具有分段字线的热辅助闪存 - Google Patents
具有分段字线的热辅助闪存 Download PDFInfo
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- CN103247337B CN103247337B CN201310046386.5A CN201310046386A CN103247337B CN 103247337 B CN103247337 B CN 103247337B CN 201310046386 A CN201310046386 A CN 201310046386A CN 103247337 B CN103247337 B CN 103247337B
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- word line
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- memory
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Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/08—Address circuits; Decoders; Word-line control circuits
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D30/00—Field-effect transistors [FET]
- H10D30/60—Insulated-gate field-effect transistors [IGFET]
- H10D30/68—Floating-gate IGFETs
- H10D30/6891—Floating-gate IGFETs characterised by the shapes, relative sizes or dispositions of the floating gate electrode
- H10D30/6893—Floating-gate IGFETs characterised by the shapes, relative sizes or dispositions of the floating gate electrode wherein the floating gate has multiple non-connected parts, e.g. multi-particle floating gate
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/10—Programming or data input circuits
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/24—Bit-line control circuits
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/18—Bit line organisation; Bit line lay-out
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C8/00—Arrangements for selecting an address in a digital store
- G11C8/14—Word line organisation; Word line lay-out
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/20—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels
- H10B43/23—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels
- H10B43/27—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/30—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region
- H10B43/35—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region with cell select transistors, e.g. NAND
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D30/00—Field-effect transistors [FET]
- H10D30/01—Manufacture or treatment
- H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
- H10D30/0413—Manufacture or treatment of FETs having insulated gates [IGFET] of FETs having charge-trapping gate insulators, e.g. MNOS transistors
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D30/00—Field-effect transistors [FET]
- H10D30/60—Insulated-gate field-effect transistors [IGFET]
- H10D30/68—Floating-gate IGFETs
- H10D30/681—Floating-gate IGFETs having only two programming levels
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D64/00—Electrodes of devices having potential barriers
- H10D64/01—Manufacture or treatment
- H10D64/031—Manufacture or treatment of data-storage electrodes
- H10D64/037—Manufacture or treatment of data-storage electrodes comprising charge-trapping insulators
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D89/00—Aspects of integrated devices not covered by groups H10D84/00 - H10D88/00
- H10D89/10—Integrated device layouts
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Semiconductor Memories (AREA)
- Non-Volatile Memory (AREA)
- Read Only Memory (AREA)
Applications Claiming Priority (6)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US201261596886P | 2012-02-09 | 2012-02-09 | |
| US61/596,886 | 2012-02-09 | ||
| US201261603810P | 2012-02-27 | 2012-02-27 | |
| US61/603,810 | 2012-02-27 | ||
| US13/458,975 | 2012-04-27 | ||
| US13/458,975 US8824212B2 (en) | 2011-05-02 | 2012-04-27 | Thermally assisted flash memory with segmented word lines |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN103247337A CN103247337A (zh) | 2013-08-14 |
| CN103247337B true CN103247337B (zh) | 2017-06-09 |
Family
ID=47747405
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201310046386.5A Active CN103247337B (zh) | 2012-02-09 | 2013-02-05 | 具有分段字线的热辅助闪存 |
Country Status (5)
| Country | Link |
|---|---|
| EP (1) | EP2626903B1 (enExample) |
| JP (1) | JP6099419B2 (enExample) |
| KR (1) | KR102007272B1 (enExample) |
| CN (1) | CN103247337B (enExample) |
| TW (1) | TWI514387B (enExample) |
Families Citing this family (17)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US9666593B2 (en) | 2014-09-29 | 2017-05-30 | Sandisk Technologies Llc | Alternating refractive index in charge-trapping film in three-dimensional memory |
| JP2017011123A (ja) * | 2015-06-23 | 2017-01-12 | ルネサスエレクトロニクス株式会社 | 半導体装置および半導体装置の駆動方法 |
| TWI564893B (zh) * | 2015-06-30 | 2017-01-01 | 財團法人工業技術研究院 | 記憶體控制方法及其系統 |
| EP3381036B1 (en) * | 2015-11-25 | 2021-07-21 | Sunrise Memory Corporation | Three-dimensional vertical nor flash thin film transistor strings |
| US9570192B1 (en) * | 2016-03-04 | 2017-02-14 | Qualcomm Incorporated | System and method for reducing programming voltage stress on memory cell devices |
| US9773553B1 (en) * | 2016-08-19 | 2017-09-26 | Micron Technology, Inc. | Segmented memory and operation |
| US10014390B1 (en) | 2017-10-10 | 2018-07-03 | Globalfoundries Inc. | Inner spacer formation for nanosheet field-effect transistors with tall suspensions |
| US11538523B2 (en) * | 2018-08-17 | 2022-12-27 | Tetramem Inc. | Crossbar array with reduced disturbance |
| KR102766456B1 (ko) * | 2019-06-21 | 2025-02-12 | 에스케이하이닉스 주식회사 | 리드 디스터번스를 완화시킬 수 있는 비휘발성 메모리 장치 및 이를 이용하는 시스템 |
| US11557341B2 (en) * | 2019-12-27 | 2023-01-17 | Micron Technology, Inc. | Memory array structures and methods for determination of resistive characteristics of access lines |
| CN113946178B (zh) * | 2020-07-15 | 2023-04-28 | 上海江波龙微电子技术有限公司 | 存储器及其偏置电压产生电路、方法 |
| US12385788B2 (en) * | 2020-11-30 | 2025-08-12 | Stmicroelectronics S.R.L. | Thermographic sensor with thermal transistors driven by thermo-couples |
| US12094549B2 (en) * | 2021-09-01 | 2024-09-17 | Micron Technology, Inc. | Defect detection during erase operations |
| US12156472B2 (en) * | 2021-09-02 | 2024-11-26 | Micron Technology, Inc. | Power regeneration in a memory device |
| CN114093829A (zh) * | 2021-11-02 | 2022-02-25 | 中国科学院微电子研究所 | 一种存储单元、三维存储器及其操作方法 |
| US20240421032A1 (en) * | 2021-11-02 | 2024-12-19 | Institute of Microelectronics, Chinese Academy of Sciences | Memory cell, three-dimensional memory, and method of operating three-dimensional memory |
| US20240324225A1 (en) * | 2023-03-20 | 2024-09-26 | Ememory Technology Inc. | Storage transistor of charge-trapping non-volatile memory |
Family Cites Families (13)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100589569B1 (ko) * | 2001-07-17 | 2006-06-19 | 산요덴키가부시키가이샤 | 반도체 메모리 장치 |
| US6911704B2 (en) * | 2003-10-14 | 2005-06-28 | Advanced Micro Devices, Inc. | Memory cell array with staggered local inter-connect structure |
| US7315474B2 (en) | 2005-01-03 | 2008-01-01 | Macronix International Co., Ltd | Non-volatile memory cells, memory arrays including the same and methods of operating cells and arrays |
| US7301818B2 (en) * | 2005-09-12 | 2007-11-27 | Macronix International Co., Ltd. | Hole annealing methods of non-volatile memory cells |
| JP4907173B2 (ja) * | 2006-01-05 | 2012-03-28 | マクロニクス インターナショナル カンパニー リミテッド | 不揮発性メモリセル、これを有するメモリアレイ、並びに、セル及びアレイの操作方法 |
| US7382654B2 (en) | 2006-03-31 | 2008-06-03 | Macronix International Co., Ltd. | Trapping storage flash memory cell structure with inversion source and drain regions |
| US7391652B2 (en) * | 2006-05-05 | 2008-06-24 | Macronix International Co., Ltd. | Method of programming and erasing a p-channel BE-SONOS NAND flash memory |
| US7646664B2 (en) * | 2006-10-09 | 2010-01-12 | Samsung Electronics Co., Ltd. | Semiconductor device with three-dimensional array structure |
| KR20090097893A (ko) * | 2006-11-29 | 2009-09-16 | 램버스 인코포레이티드 | 작동열화를 반전시킬 가열회로가 내장된 집적회로 |
| US8344475B2 (en) * | 2006-11-29 | 2013-01-01 | Rambus Inc. | Integrated circuit heating to effect in-situ annealing |
| KR20090037690A (ko) | 2007-10-12 | 2009-04-16 | 삼성전자주식회사 | 비휘발성 메모리 소자, 그 동작 방법 및 그 제조 방법 |
| WO2011022123A1 (en) * | 2009-08-21 | 2011-02-24 | Rambus Inc. | In-situ memory annealing |
| KR101060899B1 (ko) * | 2009-12-23 | 2011-08-30 | 주식회사 하이닉스반도체 | 반도체 메모리 장치 및 이의 동작 방법 |
-
2013
- 2013-02-04 TW TW102104283A patent/TWI514387B/zh active
- 2013-02-05 CN CN201310046386.5A patent/CN103247337B/zh active Active
- 2013-02-06 KR KR1020130013601A patent/KR102007272B1/ko active Active
- 2013-02-06 EP EP13154198.9A patent/EP2626903B1/en active Active
- 2013-02-06 JP JP2013021507A patent/JP6099419B2/ja active Active
Also Published As
| Publication number | Publication date |
|---|---|
| TWI514387B (zh) | 2015-12-21 |
| CN103247337A (zh) | 2013-08-14 |
| TW201346913A (zh) | 2013-11-16 |
| JP2013168209A (ja) | 2013-08-29 |
| KR102007272B1 (ko) | 2019-08-05 |
| JP6099419B2 (ja) | 2017-03-22 |
| EP2626903B1 (en) | 2016-09-14 |
| EP2626903A1 (en) | 2013-08-14 |
| KR20130092472A (ko) | 2013-08-20 |
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