CN103246312B - The threshold voltage generative circuit of cmos fet pipe - Google Patents
The threshold voltage generative circuit of cmos fet pipe Download PDFInfo
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- CN103246312B CN103246312B CN201210590543.4A CN201210590543A CN103246312B CN 103246312 B CN103246312 B CN 103246312B CN 201210590543 A CN201210590543 A CN 201210590543A CN 103246312 B CN103246312 B CN 103246312B
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Abstract
A kind of cmos fet pipe threshold voltage generation circuit, described threshold voltage generative circuit comprises one the one P type image current mirror group, one first N-type field effect transistor M1, one second N-type field effect transistor M2, one first voltage follower AMP1, one second voltage follower AMP2, one first resistance R1, one second resistance R2, one the 2nd P type image current mirror group, one the 3rd P type image current mirror group, one N-type image current mirror group and one the 3rd resistance R3, described first N-type field effect transistor M1 and the second N-type field effect transistor M2 obtains respective gate source voltage, described first voltage follower AMP1, described first resistance R1, described second voltage follower AMP2 and described second resistance R2 is by gate source voltage VGS1, VGS2 is converted into two-way current signal, described 2nd P type image current mirror group, described 3rd P type image current mirror group, described N-type image current mirror group and described 3rd resistance R3 combine two-way current signal and generate high-precision threshold voltage.The present invention adopts simple circuit structure to achieve the extracted with high accuracy of cmos fet pipe threshold voltage.
Description
Technical field
The present invention relates to a kind of integrated circuit, be specifically related to a kind of threshold voltage generative circuit of cmos fet pipe.
Background technology
The threshold voltage of cmos fet pipe is the important parameter in cmos circuit design, and under specific process conditions, this threshold voltage is relevant to process corner, and has nonlinear negative temperature coefficient, and therefore under general situation, it there is no need to produce as independent voltage.But in some special applications, need to obtain this threshold voltage, these special applications comprise: judge the process corner residing for cmos fet pipe, generate voltage or the electric current of distinct temperature coefficient, generate ring oscillator of Low Drift Temperature clock etc.
The current programme generating cmos fet pipe threshold voltage is few, and the threshold voltage precision of these schemes or generation is not high enough, or circuit implementations is complicated especially, is difficult to the compromise realized between high precision and low cost.
Summary of the invention
The object of the invention is, a kind of threshold voltage generative circuit of cmos fet pipe is provided.Utilizing the saturation region current formula of cmos fet pipe, to flowing through same current but the gate source voltage of the different cmos fet pipe of size does computing, obtaining high-precision threshold voltage with easy circuit.
The technical solution used in the present invention is, a kind of threshold voltage generative circuit of cmos fet pipe, is characterized in that: described threshold voltage generative circuit comprises one the one P type image current mirror group, one first N-type field effect transistor M1, one second N-type field effect transistor M2, one first voltage follower AMP1, one second voltage follower AMP2, one first resistance R1, one second resistance R2, one the 2nd P type image current mirror group, one the 3rd P type image current mirror group, one N-type image current mirror group and one the 3rd resistance R3, described first N-type field effect transistor M1 and the second N-type field effect transistor M2 obtains respective gate source voltage VGS1, VGS2, described first voltage follower AMP1, gate source voltage VGS1 is converted into current signal by described first resistance R1, and gate source voltage VGS2 is converted into current signal by described second voltage follower AMP2 and described second resistance R2, described 2nd P type image current mirror group, described 3rd P type image current mirror group, described N-type image current mirror group and described 3rd resistance R3 combine two-way current signal and generate high-precision threshold voltage.
The grid of described first N-type field effect transistor M1 and source electrode are connected in the output terminal i1 of a described P type image current mirror group, and the grid of described second N-type field effect transistor M2 and source electrode are connected in the output terminal i2 of a described P type image current mirror group; The vip input end of described first voltage follower AMP1 is connected with the grid of described first N-type field effect transistor M1, and the vin input end of described first voltage follower AMP1 is connected with the input end i3 of the 2nd P type image current mirror group with one end of described first resistance R1 with the out of described first voltage follower AMP1; The other end of described first resistance R1 is connected to the ground; The vip input end of described second voltage follower AMP2 is connected with the grid of described second N-type field effect transistor M2, and the vin input end of described second voltage follower AMP2 is connected with the input end i5 of the 3rd P type image current mirror group with one end of described second resistance R2 with the out of described second voltage follower AMP2; The other end of described second resistance R2 is connected to the ground; The output terminal i6 of the 3rd P type image current mirror group is connected with the input end i7 of N-type image current mirror group; The output terminal i8 of N-type image current mirror group is connected with resistance R3 with the output terminal i4 of the 2nd P type image current mirror group.
A described P type image current mirror group comprises an input end i0, an output terminal i1 and an output terminal i2, described output terminal i0 is input current source, and the current mirror image ratio of described input end i0, described output terminal i1 and described output terminal i2 is: i0:i1:i2=1:1:1.
Described 2nd P type image current mirror group comprises an an input end i3 and output terminal i4, and the current mirror image ratio of described input end i3 and described output terminal i4 is: i3:i4=1:2.
Described 3rd P type image current mirror group comprises an an input end i5 and output terminal i6, and the current mirror image ratio of described input end i5 and described output terminal i6 is: i5:i6=1:1.
Described N-type image current mirror group comprises an an input end i7 and output terminal i8, and the current mirror image ratio of described input end i7 and described output terminal i8 is: i7:i8=1:1.
The present invention utilizes the saturation region current formula of cmos fet pipe, to flowing through same current but the gate source voltage of the different cmos fet pipe of size does computing, obtains high-precision threshold voltage with easy circuit.
Accompanying drawing explanation
Fig. 1 is the circuit structure diagram of threshold voltage generative circuit of the present invention.
In Fig. 1: a P type current mirror group, comprises an input end i0, two output terminal i1 and i2; N-type field effect transistor M1; N-type field effect transistor M2; Voltage follower AMP1; Voltage follower AMP2; Resistance R1; Resistance R2; 2nd P type current mirror group, comprises an input end i3, an output terminal i4; 3rd P type current mirror group, comprises an input end i5, an output terminal i6; N-type current mirror group, comprises an input end i7, an output terminal i8; Resistance R3.
Embodiment
Below in conjunction with accompanying drawing, the present invention is further elaborated.
See Fig. 1, the threshold voltage generative circuit of cmos fet pipe of the present invention comprises: a P type image current mirror group, N-type field effect transistor M1, N-type field effect transistor M2, voltage follower AMP1, voltage follower AMP2, resistance R1, resistance R2, the 2nd P type image current mirror group, the 3rd P type image current mirror group, N-type image current mirror group and resistance R3.
The grid of described N-type field effect transistor M1 and source electrode are connected in the i1 output terminal of a P type image current mirror group, and the grid of N-type field effect transistor M2 and source electrode are connected in the i2 output terminal of a P type image current mirror group; The vip input end of the first voltage follower AMP1 is connected with the grid of N-type field effect transistor M1, and the vin input end of the first voltage follower AMP1 is connected with the i3 input end of one end of resistance R1 with the 2nd P type image current mirror group with the out of the first voltage follower AMP1; The other end of resistance R1 is connected to the ground; The vip input end of the second voltage follower AMP2 is connected with the grid of N-type field effect transistor M2, and the vin input end of the second voltage follower AMP2 is connected with the i5 input end of one end of resistance R2 with the 3rd P type image current mirror group with the out of the second voltage follower AMP2; The other end of resistance R2 is connected to the ground; The i6 output terminal of the 3rd P type image current mirror group is connected with the i7 input end of N-type image current mirror group; The i8 output terminal of N-type image current mirror group is connected with resistance R3 with the i4 output terminal of the 2nd P type image current mirror group.
The current mirror image ratio of the i0 input end of the one P type image current mirror group, i1 output terminal and i2 output terminal is: i0:i1:i2=1:1:1.Regulate the value of input end electric current and regulate the breadth length ratio of N-type field effect transistor M1 and N-type field effect transistor M2, making N-type field effect transistor M1 and N-type field effect transistor M2 all be operated in saturation region, according to saturation region current formula, obtain respectively
The ratio of getting the breadth length ratio of N-type field effect transistor M1 and N-type field effect transistor M2 is 1:4, and by I
d_M1=I
d_M2substitute into, obtain
2×V
GS1-V
GS2＝V
THN
The i3 input end of the first voltage follower AMP1, resistance R1 and the 2nd P type image current mirror group forms complete voltage follower, and its output end voltage is V
bUF1.The vip input end of the first voltage follower AMP1 connects the grid of N-type field effect transistor M1, and the vin input end of the first voltage follower AMP1 is connected with out output terminal, and the voltage of its out output terminal equals the voltage V of vip input end
gS1, so V
bUF1=V
gS1.The i3 input end current value of the 2nd P type image current mirror group is
the i4 output end current value of the 2nd P type image current mirror group is
The i5 input end of the second voltage follower AMP2, resistance R2 and the 3rd P type image current mirror group forms complete voltage follower, and its output end voltage is V
bUF2.The vip input end of the second voltage follower AMP2 connects the grid of N-type field effect transistor M2, and the vin input end of the second voltage follower AMP2 is connected with out output terminal, and the voltage of its out output terminal equals the voltage V of vip input end
gS2, so V
bUF2=V
gS2.The i5 input end current value of the 3rd P type image current mirror group is
the i6 output end current value of the 3rd P type image current mirror group is
the i7 input end current value of N-type image current mirror group is
the i8 output end current value of N-type image current mirror group is
The i8 output terminal of N-type image current mirror group is connected with the i4 output terminal of the 2nd P type image current mirror group, and its combined electrical flow valuve is
the magnitude of voltage of output end voltage VTH_GEN is
If get R1=R2=R3 and substitute into 2 × V
gS1-V
gS2=V
tHN, then obtain
V
TH_GEN＝2×V
GS1-V
GS2＝V
THN
In sum, the cmos fet pipe threshold voltage generation circuit that the present invention proposes, adopt easy circuit structure, achieve the extraction to cmos fet pipe threshold voltage, the threshold voltage of generation has high-precision characteristic.
Claims (5)
1. a threshold voltage generative circuit for cmos fet pipe, is characterized in that: described threshold voltage generative circuit comprises one the one P type image current mirror group, one first N-type field effect transistor M1, one second N-type field effect transistor M2, one first voltage follower AMP1, one second voltage follower AMP2, one first resistance R1, one second resistance R2, one the 2nd P type image current mirror group, one the 3rd P type image current mirror group, one N-type image current mirror group and one the 3rd resistance R3, described first N-type field effect transistor M1 and the second N-type field effect transistor M2 obtains respective gate source voltage VGS1, VGS2, described first voltage follower AMP1, gate source voltage VGS1 is converted into current signal by described first resistance R1, and gate source voltage VGS2 is converted into current signal by described second voltage follower AMP2 and described second resistance R2, described 2nd P type image current mirror group, described 3rd P type image current mirror group, described N-type image current mirror group and described 3rd resistance R3 combine two-way current signal and generate high-precision threshold voltage, described N-type field effect transistor M1 and N-type field effect transistor M2 is all operated in saturation region,
The grid of described first N-type field effect transistor M1 and source electrode are connected in the output terminal i1 of a described P type image current mirror group, and the grid of described second N-type field effect transistor M2 and source electrode are connected in the output terminal i2 of a described P type image current mirror group; The vip input end of described first voltage follower AMP1 is connected with the grid of described first N-type field effect transistor M1, and the vin input end of described first voltage follower AMP1 is connected with the input end i3 of the 2nd P type image current mirror group with one end of described first resistance R1 with the out of described first voltage follower AMP1; The other end of described first resistance R1 is connected to the ground; The vip input end of described second voltage follower AMP2 is connected with the grid of described second N-type field effect transistor M2, and the vin input end of described second voltage follower AMP2 is connected with the input end i5 of the 3rd P type image current mirror group with one end of described second resistance R2 with the out of described second voltage follower AMP2; The other end of described second resistance R2 is connected to the ground; The output terminal i6 of the 3rd P type image current mirror group is connected with the input end i7 of N-type image current mirror group; The output terminal i8 of N-type image current mirror group is connected with resistance R3 with the output terminal i4 of the 2nd P type image current mirror group.
2. threshold voltage generative circuit as described in claim 1, it is characterized in that: a described P type image current mirror group comprises an input end i0, an output terminal i1 and an output terminal i2, described input end i0 is input current source, and the current mirror image ratio of described input end i0, described output terminal i1 and described output terminal i2 is: i0:i1:i2=1:1:1.
3. threshold voltage generative circuit as described in claim 1, is characterized in that: described 2nd P type image current mirror group comprises an an input end i3 and output terminal i4, and the current mirror image ratio of described input end i3 and described output terminal i4 is: i3:i4=1:2.
4. threshold voltage generative circuit as described in claim 1, is characterized in that: described 3rd P type image current mirror group comprises an an input end i5 and output terminal i6, and the current mirror image ratio of described input end i5 and described output terminal i6 is: i5:i6=1:1.
5. threshold voltage generative circuit as described in claim 1, is characterized in that: described N-type image current mirror group comprises an an input end i7 and output terminal i8, and the current mirror image ratio of described input end i7 and described output terminal i8 is: i7:i8=1:1.
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Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| GB2240442A (en) * | 1990-01-29 | 1991-07-31 | Mitsubishi Electric Corp | Threshold voltage generating circuit for integrated circuit |
| CN101630174A (en) * | 2008-12-31 | 2010-01-20 | 曹先国 | Matching constant current resource |
| CN203133655U (en) * | 2012-12-31 | 2013-08-14 | 成都锐成芯微科技有限责任公司 | Threshold voltage generating circuit for complementary metal-oxide-semiconductor transistor (CMOS) field-effect tube |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS57111618A (en) * | 1980-12-27 | 1982-07-12 | Citizen Watch Co Ltd | Constant voltage circuit |
| US7692453B2 (en) * | 2004-08-11 | 2010-04-06 | Atmel Corporation | Detector of differential threshold voltage |
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2012
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Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| GB2240442A (en) * | 1990-01-29 | 1991-07-31 | Mitsubishi Electric Corp | Threshold voltage generating circuit for integrated circuit |
| CN101630174A (en) * | 2008-12-31 | 2010-01-20 | 曹先国 | Matching constant current resource |
| CN203133655U (en) * | 2012-12-31 | 2013-08-14 | 成都锐成芯微科技有限责任公司 | Threshold voltage generating circuit for complementary metal-oxide-semiconductor transistor (CMOS) field-effect tube |
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Address after: 610041 floor 4, block A, 1 building 200, Tianfu five street, hi tech Zone, Chengdu, Sichuan. Patentee after: Chengdu Rui core micro Polytron Technologies Inc Address before: 610041 room 1705, G1 building, 1800 Yizhou Road, Chengdu high tech Zone, Sichuan. Patentee before: Chengdu Ruicheng Xinwei Technology Co., Ltd. |
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Denomination of invention: Threshold voltage generation circuit of CMOS (complementary metal oxide semiconductor) field-effect transistor Effective date of registration: 20190311 Granted publication date: 20160413 Pledgee: Agricultural Bank of China Limited by Share Ltd Chengdu Shuangliu Branch Pledgor: Chengdu Rui core micro Polytron Technologies Inc Registration number: 2019510000025 |
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Date of cancellation: 20210226 Granted publication date: 20160413 Pledgee: Agricultural Bank of China Limited by Share Ltd. Chengdu Shuangliu Branch Pledgor: CHENGDU ANALOG CIRCUIT TECHNOLOGY Inc. Registration number: 2019510000025 |