CN104166422B - A kind ofly export adjustable non-resistance non-bandgap reference source - Google Patents

Abstract

The invention belongs to Analogous Integrated Electronic Circuits technical field, be specifically related to a kind ofly export adjustable non-resistance non-bandgap reference source.Reference source of the present invention is by 5 PMOS: MP1, MP2, MP3, MS1, MS2,3 NMOS tube: MN1, MN2, MSC1 and a positive temperature voltage V _pTAT(PTAT, Proportional? To? Absolute? Temperature) circuit composition is produced.The non-resistance non-bandgap reference source that output of the present invention is adjustable, realizes adjustable benchmark and exports; The tail current source of reference source provides bias current for positive temperature voltage generation circuit, without the need to extra bias current generating circuit, power consumption is reduced, the V of positive temperature voltage generation circuit generation simultaneously _pTATact on reference source, mutually control; Because integrated circuit does not use BJT to manage and resistance, chip area is reduced greatly.The present invention is particularly useful for exporting adjustable non-bandgap reference source.

Description

A kind ofly export adjustable non-resistance non-bandgap reference source

Technical field

The invention belongs to Analogous Integrated Electronic Circuits technical field, be specifically related to a kind ofly export adjustable non-resistance non-bandgap reference source.

Background technology

Reference source has become indispensable in electronic system, is the basic comprising module in mimic channel and numerical model analysis electronic circuit.Important role is play in numerous application, such as the circuit application such as Power convert, A/D converter, oscillator, phaselocked loop.With one of current study hotspot, on-chip power supply converter is example, and reference source plays key player in its stable output procedure, reference source is used for the output of stabilized power source converter, it is to the output accuracy of power supply changeover device, and Power Supply Rejection Ratio, the parameters such as temperature coefficient play key effect.When the structure of power supply changeover device is tending towards maturation, study the lifting undoubtedly important role of more high performance reference source for circuit performance.

As everyone knows, the study hotspot of integrated circuit fields in benchmark has mostly concentrated on Resistance standard circuit all the time, but, the application of resistance exist process deviation large, expend the shortcomings such as chip area, noise coupling are large, this makes traditional Resistance standard that has not be suitable for low noise applications circuit; Cannot resistance be provided simultaneously in some techniques, add the limitation of Resistance standard.But the research of industry to high-performance non-resistance reference circuit aspect is extremely short of.Realize the Low Drift Temperature of non-resistance reference circuit, low PSRR, low-power consumption, very important research direction will be become.And the output of the non-resistance non-bandgap reference source proposed at present is fixing substantially, limit its range of application.

Summary of the invention

Object of the present invention is exactly export fixing problem for existing reference source, proposes a kind ofly to export adjustable non-resistance non-bandgap reference source.

Technical scheme of the present invention is, a kind ofly exports adjustable non-resistance non-bandgap reference source, it is characterized in that, this reference source by PMOS MP1, MP2, MP3, MS1, MS2, NMOS tube MN1, MN2, MNC1, electric capacity CS1 and positive temperature voltage generation circuit are formed; Wherein, the source electrode of MS1 connects supply voltage, its grounded-grid current potential, and its drain electrode connects the forward end of CS1; The negative end earthing potential of CS1; The source electrode of MS2 connects supply voltage, and its grid connects the drain electrode of MS1, and the drain electrode of MS2 connects the grid of MN1; The source electrode of MP3 connects supply voltage, and its grid connects the grid of MP1, and the drain electrode of MP3 connects the input end of positive temperature voltage generation circuit; The grid of the output termination MN1 of positive temperature voltage generation circuit; The grid of MNC1 connects the grid of MN1, its drain electrode and source grounding current potential; The source electrode of MP1 connects supply voltage, its drain electrode and gate interconnection, and its drain electrode connects the drain electrode of MN1; The source ground current potential of MN1; The source electrode of MP2 connects supply voltage, and its grid connects the grid of MP1; The drain electrode of MN2 and gate interconnection, the tie point that its drain electrode drains with MP2 as the output terminal of reference source, the source ground current potential of MN2.

Beneficial effect of the present invention is, realizes adjustable benchmark and exports; The tail current source of reference source provides bias current for positive temperature voltage generation circuit, without the need to extra bias current generating circuit, power consumption is reduced, the V of positive temperature voltage generation circuit generation simultaneously _pTATact on reference source, mutually control; Because integrated circuit does not use BJT to manage and resistance, chip area is reduced greatly.

Accompanying drawing explanation

Fig. 1 is the electrical block diagram of the adjustable non-resistance non-bandgap reference source of output of the present invention.

Embodiment

Below in conjunction with accompanying drawing, the present invention is described in detail

As shown in Figure 1, it is by 5 PMOS: MP1, MP2, MP3, MS1, MS2,3 NMOS tube for the non-resistance non-bandgap reference source configuration diagram that output of the present invention is adjustable: MN1, MN2, MNC1 and a positive temperature voltage V _pTAT(PTAT, ProportionalToAbsoluteTemperature) produces circuit composition.Concrete annexation is: the source electrode of MS1 meets supply voltage VIN, its grounded-grid current potential VSS, and its drain electrode connects the forward end of CS1; The negative end earthing potential VSS of CS1; The source electrode of MS2 meets supply voltage VIN, and its grid connects the drain electrode of MS1, and the drain electrode of MS2 connects the grid of MN1; The source electrode of MP3 meets supply voltage VIN, and its grid connects the grid of MP1, and the drain electrode of MP3 meets V _pTATproduce one end of circuit; V _pTATproduce the grid of the output termination MN1 of circuit; The grid of MNC1 connects the grid of MN1, its drain electrode and Source interconnect, the source ground current potential VSS of MNC1; The source electrode of MP1 meets supply voltage VIN, its drain electrode and gate interconnection, and its drain electrode connects the drain electrode of MN1; The source ground current potential VSS of MN1; The source electrode of MP2 meets supply voltage VIN, and its grid connects the grid of MP1; The drain electrode of MN2 and gate interconnection, the tie point that its drain electrode and MP2 drain is as the output V of reference source _rEF, the source ground current potential VSS of MN2.

Principle of work of the present invention is:

In the present invention, start-up circuit is made up of PMOS MS1, MS2 and electric capacity CS1.When chip powers on, MS1 conducting, the positive terminal voltage of electric capacity CS1 is 0, thus makes MS2 conducting, starts to charge to mos capacitance MNC1, and the grid voltage of MN1 slowly rises.When the grid voltage of MN1 rises to the threshold voltage equaling MN1, MN1 conducting, simultaneously MP1 also conducting.The electric current flowing through MN1 and MP1 is gone out by current mirror mirror image, and the current offset of whole circuit is set up.MS1 has electric current to flow through always and charges until CS1 electric capacity is charged to supply voltage VIN to CS1, when CS1 electric capacity power on pressure be elevated to make MS2 enter cut-off region time, thus started, start-up circuit cuts out, and does not affect the normal work of remainder circuit and also not current sinking.

In circuit of the present invention, MN1, MN2 are operated in saturation region, and MP1, MP2, MP3 are operated in subthreshold region.The V that the gate voltage of MN1 is produced by positive temperature voltage generation circuit _pTATcontrol, its current formula is as follows:

$I_{N1}=\frac{1}{2}{\mathrm{\μ}}_n{C}_{OX}{S}_{N1}{(V_{PTAT}-V_{THN1})}^2---\left(1\right)$

The leakage current of MN1, by after MP1 and MP2 mirror image, can obtain

$I_{N2}=I_{P2}=\frac{S_{P2}}{S_{P1}}{I}_{N1}=\frac{1}{2}{\mathrm{\μ}}_n{C}_{OX}\frac{S_{P2}}{S_{P1}}{S}_{N1}{(V_{PTAT}-V_{THN1})}^2---\left(2\right)$

The leakage current of MN1, by after MP1 and MP3 mirror image, can obtain

$I_{P3}=\frac{S_{P3}}{S_{P1}}{I}_{N1}---\left(3\right)$

The leakage current of MP3 provides tail current for positive temperature voltage generation circuit.Wherein, I _nirepresent NMOS tube M _nidrain current, I _pirepresent PMOS M _pidrain current, m _nelectron mobility, C _oXgate oxide current potential area capacitance, S _pirepresent PMOS M _pibreadth length ratio, S _nirepresent NMOS tube M _nibreadth length ratio, V _tHN1it is the threshold voltage of MN1 pipe.

Because MN2 pipe connects with diode form, the drain current that can obtain M2 pipe is

$I_{N2}=\frac{1}{2}{\mathrm{\μ}}_n{C}_{OX}{S}_{N2}{(V_{REF}-V_{THN2})}^2---\left(4\right)$

In conjunction with (2) formula and (4) Shi Ke get:

V _REF＝V _THN2+A(V _PTAT-V _THN1)(5)

Wherein, v _tHN2it is the threshold voltage of MN2 pipe.

Due to V _tH=V _tH0-a _vT(T-T ₀), wherein T is absolute temperature, V _tH0for T ₀threshold voltage during temperature, a _vTfor V _tHtemperature coefficient, after substituting into above-mentioned (5) formula, can obtain

$V_{REF}=(1-A)\[(V_{TH0}+{\mathrm{\α}}_{VT}{T}_0)+\frac{A}{1-A}{V}_{PTAT}-{\mathrm{\α}}_{VT}T\]---\left(6\right)$

From said reference voltage V _rEFformula is known, by regulating the output of the adjustable reference source of A.

Make V _pTAT=BT, B are the temperature coefficient of PTAT voltage, can make reference source temperature coefficient be zero condition as follows

$\frac{\∂V_{REF}}{\∂T}=A\·B-(1-A){\mathrm{\α}}_{VT}=0---\left(7\right)$

From above formula, by adjustment factor B, zero warm reference source can be realized.

In sum, the non-resistance non-bandgap reference source that the present invention proposes, reaches the feature that benchmark output valve is separated with temperature characterisitic, achieves adjustable benchmark and exports; The tail current source of reference source provides bias current for positive temperature voltage generation circuit, without the need to extra bias current generating circuit, power consumption is reduced, the V of positive temperature voltage generation circuit generation simultaneously _pTATact on reference source, mutually control; Because integrated circuit does not use BJT to manage and resistance, chip area is reduced greatly.

Claims (1)

1. export an adjustable non-resistance non-bandgap reference source, it is characterized in that, this reference source by PMOS MP1, MP2, MP3, MS1, MS2, NMOS tube MN1, MN2, MNC1, electric capacity CS1 and positive temperature voltage generation circuit are formed; Wherein, the source electrode of MS1 connects supply voltage, its grounded-grid current potential, and its drain electrode connects the forward end of CS1; The negative end earthing potential of CS1; The source electrode of MS2 connects supply voltage, and its grid connects the drain electrode of MS1, and the drain electrode of MS2 connects the grid of MN1; The source electrode of MP3 connects supply voltage, and its grid connects the grid of MP1, and the drain electrode of MP3 connects the input end of positive temperature voltage generation circuit; The grid of the output termination MN1 of positive temperature voltage generation circuit; The grid of MNC1 connects the grid of MN1, the drain electrode of MNC1 and source grounding current potential; The source electrode of MP1 connects supply voltage, its drain electrode and gate interconnection, and its drain electrode connects the drain electrode of MN1; The source ground current potential of MN1; The source electrode of MP2 connects supply voltage, and its grid connects the grid of MP1; The drain electrode of MN2 and gate interconnection, the tie point that its drain electrode drains with MP2 as the output terminal of reference source, the source ground current potential of MN2.