CN103246312A - Threshold voltage generation circuit of CMOS (complementary metal oxide semiconductor) field-effect transistor - Google Patents

Abstract

A threshold voltage generation circuit of a CMOS (complementary metal oxide semiconductor) field-effect transistor comprises a first P-type mirror current source set, a first N-type field-effect transistor M1, a second N-type field-effect transistor M2, a first voltage follower AMP1, a second voltage follower AMP2, a first resistor R1, a second resistor R2, a second P-type mirror current source set, a third P-type mirror current source set, an N-type mirror current source set, and a third resistor R3. The first N-type field-effect transistor M1 and the second N-type field-effect transistor M2 receive respective gate-to-source voltages. The gate-to-source voltages VGS2 and VGS2 are converted to two current signals by the first voltage follower AMP1, the first resistor R1, the second voltage follower AMP2 and the second resistor R2. The two current signals are combined into high-precision threshold voltage by the second P-type mirror current source set, the third P-type mirror current source set, the N-type mirror current and the third resistor R3. The threshold voltage of the CMOS field-effect transistor is precisely extracted through the simple circuit structure.

Description

The threshold voltage generative circuit of cmos fet pipe

Technical field

The present invention relates to a kind of integrated circuit, be specifically related to a kind of cmos fet pipe threshold voltage generation circuit.

Background technology

The threshold voltage of cmos fet pipe is the important parameter in the cmos circuit design, and under specific process conditions, this threshold voltage is relevant with process corner, and has nonlinear negative temperature coefficient, and therefore it there is no need to produce as independent voltage under general situation.But in some special applications, need obtain this threshold voltage, these special applications comprise: judge the residing process corner of cmos fet pipe, generate voltage or the electric current of distinct temperature coefficient, generate low temperature and float ring oscillator of clock etc.

The current programme that generates cmos fet pipe threshold voltage is few, and the threshold voltage precision of these schemes or generation is not high enough, or the circuit implementation is complicated especially, is difficult to realize the compromise between high precision and the low cost.

Summary of the invention

The objective of the invention is, a kind of cmos fet pipe threshold voltage generation circuit is provided.Utilize the saturation region current formula of cmos fet pipe, to flowing through same current but the gate source voltage of the different cmos fet pipe of size is done computing, obtained high-precision threshold voltage with easy circuit.

The technical solution used in the present invention is, a kind of cmos fet pipe threshold voltage generation circuit, it is characterized in that: described threshold voltage generative circuit comprises one the one P type image current mirror group, one first N-type field effect transistor M1, one second N-type field effect transistor M2, one first voltage follower AMP1, one second voltage follower AMP2, one first resistance R 1, one second resistance R 2, one the 2nd P type image current mirror group, one the 3rd P type image current mirror group, one N-type image current mirror group and one the 3rd resistance R 3, the described first N-type field effect transistor M1 and the second N-type field effect transistor M2 obtain gate source voltage separately, the described first voltage follower AMP1, described first resistance R 1, the described second voltage follower AMP2 and described second resistance R 2 are with gate source voltage VGS1, VGS2 is converted into the two-way current signal, described the 2nd P type image current mirror group, described the 3rd P type image current mirror group, described N-type image current mirror group and described the 3rd resistance R 3 combination two-way current signals also generate high-precision threshold voltage.

The grid of the described first N-type field effect transistor M1 and source electrode are connected in a described P type image current mirror group, and the grid of the described second N-type field effect transistor M2 and source electrode are connected in a described P type image current mirror group; The vip input end of the described first voltage follower AMP1 links to each other with the grid of the described first N-type field effect transistor M1, and the vin input end of the described first voltage follower AMP1 links to each other with the 2nd P type image current mirror group with an end of described first resistance R 1 with the out of the described first voltage follower AMP1; The other end of described first resistance R 1 links to each other with ground; The vip input end of the described second voltage follower AMP2 links to each other with the grid of the described second N-type field effect transistor M2, and the vin input end of the described second voltage follower AMP2 links to each other with the 3rd P type image current mirror group with an end of described second resistance R 2 with the out of the described second voltage follower AMP2; The other end of described second resistance R 2 links to each other with ground; Described the 2nd P type image current mirror group links to each other with described the 3rd resistance R 3 with described N-type image current mirror group with described the 3rd P type image current mirror group.

A described P type image current mirror group comprises an input end i0, an output terminal i1 and an output terminal i2, and described output terminal i0 is the input current source, and described input end i0, described output terminal i1 with the current mirror ratio of described output terminal i2 are: i0:i1:i2=1:1:1.

Described the 2nd P type image current mirror group comprises an input end i3 and an output terminal i4, and described input end i3 with the current mirror ratio of described output terminal i4 is: i3:i4=1:2.

Described the 3rd P type image current mirror group comprises an input end i5 and an output terminal i6, and described input end i5 with the current mirror ratio of described output terminal i6 is: i5:i6=1:1.

Described N-type image current mirror group comprises an input end i7 and an output terminal i8, and described input end i7 with the current mirror ratio of described output terminal i8 is: i7:i8=1:1.

The present invention utilizes the saturation region current formula of cmos fet pipe, to flowing through same current but the gate source voltage of the different cmos fet pipe of size is done computing, has obtained high-precision threshold voltage with easy circuit.

Description of drawings

Fig. 1 is the circuit structure diagram of threshold voltage generative circuit of the present invention.

Among Fig. 1: a P type current mirror group comprises an input end i0, two output terminal i1 and i2; N-type field effect transistor M1; N-type field effect transistor M2; Voltage follower AMP1; Voltage follower AMP2; Resistance R 1; Resistance R 2; The 2nd P type current mirror group comprises an input end i3, an output terminal i4; The 3rd P type current mirror group comprises an input end i5, an output terminal i6; N-type current mirror group comprises an input end i7, an output terminal i8; Resistance R 3.

Embodiment

The present invention is further elaborated below in conjunction with accompanying drawing.

See Fig. 1, cmos fet pipe threshold voltage generation circuit of the present invention comprises: a P type image current mirror group, N-type field effect transistor M1, N-type field effect transistor M2, voltage follower AMP1, voltage follower AMP2, resistance R 1, resistance R 2, the 2nd P type image current mirror group, the 3rd P type image current mirror group, N-type image current mirror group and resistance R 3.

The grid of described N-type field effect transistor M1 and source electrode are connected in the i1 output terminal of a P type image current mirror group, and the grid of N-type field effect transistor M2 and source electrode are connected in the i2 output terminal of a P type image current mirror group; The vip input end of the first voltage follower AMP1 links to each other with the grid of N-type field effect transistor M1, and the vin input end of the first voltage follower AMP1 links to each other with the i3 input end of the 2nd P type image current mirror group with an end of resistance R 1 with the out of the first voltage follower AMP1; The other end of resistance R 1 links to each other with ground; The vip input end of the second voltage follower AMP2 links to each other with the grid of N-type field effect transistor M2, and the vin input end of the second voltage follower AMP2 links to each other with the i5 input end of the 3rd P type image current mirror group with an end of resistance R 2 with the out of the second voltage follower AMP2; The other end of resistance R 2 links to each other with ground; The i6 output terminal of the 3rd P type image current mirror group links to each other with the i7 input end of N-type image current mirror group; The i8 output terminal of N-type image current mirror group links to each other with resistance R 3 with the i4 output terminal of the 2nd P type image current mirror group.

The i0 input end of the one P type image current mirror group, i1 output terminal with the current mirror ratio of i2 output terminal are: i0:i1:i2=1:1:1.Regulate the value of input end electric current and regulate N-type field effect transistor M1 and the breadth length ratio of N-type field effect transistor M2, make N-type field effect transistor M1 and N-type field effect transistor M2 all be operated in the saturation region, according to the saturation region current formula, obtain respectively

$I_{D\_\mathrm{<figure-callout\; id="1"\; label="M"\; filenames="HDA00002690041700011.png"\; state="\{\{state\}\}">M</figure-callout>}1}=\frac{1}{2}{u}_n{C}_{\mathrm{OX}}\&times;{\left(\frac{W}{L}\right)}_{{\mathrm{<figure-callout\; id="1"\; label="M"\; filenames="HDA00002690041700011.png"\; state="\{\{state\}\}">M</figure-callout>}}_1}\&times;{(V_{\mathrm{GS}1}-V_{\mathrm{THN}})}^2,$

$I_{D\_\mathrm{<figure-callout\; id="2"\; label="M"\; filenames="HDA00002690041700011.png"\; state="\{\{state\}\}">M</figure-callout>}2}=\frac{1}{2}{u}_n{C}_{\mathrm{OX}}\&times;{\left(\frac{W}{L}\right)}_{{\mathrm{<figure-callout\; id="2"\; label="M"\; filenames="HDA00002690041700011.png"\; state="\{\{state\}\}">M</figure-callout>}}_2}\&times;{(V_{\mathrm{GS}2}-V_{\mathrm{THN}})}^2,$ V wherein _THNThreshold voltage for the N-type field effect transistor.

The ratio of getting the breadth length ratio of N-type field effect transistor M1 and N-type field effect transistor M2 is 1:4, and with I _{D_M1}=I _{D_M2}Substitution obtains

2×V _GS1-V _GS2＝V _THN

The i3 input end of the first voltage follower AMP1, resistance R 1 and the 2nd P type image current mirror group constitutes complete voltage follower, and its output end voltage is V _BUF1The vip input end of the first voltage follower AMP1 connects the grid of N-type field effect transistor M1, and the vin input end of the first voltage follower AMP1 links to each other with the out output terminal, and the voltage of its out output terminal equals the voltage V of vip input end _GS1So, V _BUF1=V _GS1The i3 input end current value of the 2nd P type image current mirror group is

The i4 output end current value of the 2nd P type image current mirror group is $i4=\frac{2\&times;V_{\mathrm{GS}1}}{\mathrm{<figure-callout\; id="1"\; label="R"\; filenames="HDA00002690041700011.png"\; state="\{\{state\}\}">R</figure-callout>}1}.$

The i5 input end of the second voltage follower AMP2, resistance R 2 and the 3rd P type image current mirror group constitutes complete voltage follower, and its output end voltage is V _BUF2The vip input end of the second voltage follower AMP2 connects the grid of N-type field effect transistor M2, and the vin input end of the second voltage follower AMP2 links to each other with the out output terminal, and the voltage of its out output terminal equals the voltage V of vip input end _GS2So, V _BUF2=V _GS2The i5 input end current value of the 3rd P type image current mirror group is

The i6 output end current value of the 3rd P type image current mirror group is

The i7 input end current value of N-type image current mirror group is

The i8 output end current value of N-type image current mirror group is

The i8 output terminal of N-type image current mirror group links to each other with the i4 output terminal of the 2nd P type image current mirror group, and its combined electrical flow valuve is The magnitude of voltage of output end voltage VTH_ GEN is

$V_{\mathrm{TH}\_\mathrm{GEN}}=(\frac{2\&times;V_{\mathrm{GS}1}}{R1}-\frac{V_{\mathrm{GS}2}}{R2})\&times;R3$

If get R1=R2=R3 and substitution 2 * V _GS1-V _GS2=V _THN, then obtain

V _{TH_GEN}＝2×V _GS1-V _GS2＝V _THN

In sum, the cmos fet pipe threshold voltage generation circuit that the present invention proposes adopts easy circuit structure, has realized the extraction to cmos fet pipe threshold voltage, and the threshold voltage of generation has high-precision characteristic.

Claims (6)

1. cmos fet pipe threshold voltage generation circuit, it is characterized in that: described threshold voltage generative circuit comprises one the one P type image current mirror group, one first N-type field effect transistor M1, one second N-type field effect transistor M2, one first voltage follower AMP1, one second voltage follower AMP2, one first resistance R 1, one second resistance R 2, one the 2nd P type image current mirror group, one the 3rd P type image current mirror group, one N-type image current mirror group and one the 3rd resistance R 3, the described first N-type field effect transistor M1 and the second N-type field effect transistor M2 obtain gate source voltage separately, the described first voltage follower AMP1, described first resistance R 1, the described second voltage follower AMP2 and described second resistance R 2 are with gate source voltage VGS1, VGS2 is converted into the two-way current signal, described the 2nd P type image current mirror group, described the 3rd P type image current mirror group, described N-type image current mirror group and described the 3rd resistance R 3 combination two-way current signals also generate high-precision threshold voltage.

2. the threshold voltage generative circuit described in claim 1, it is characterized in that: the grid of the described first N-type field effect transistor M1 and source electrode are connected in a described P type image current mirror group, and the grid of the described second N-type field effect transistor M2 and source electrode are connected in a described P type image current mirror group; The vip input end of the described first voltage follower AMP1 links to each other with the grid of the described first N-type field effect transistor M1, and the vin input end of the described first voltage follower AMP1 links to each other with the 2nd P type image current mirror group with an end of described first resistance R 1 with the out of the described first voltage follower AMP1; The other end of described first resistance R 1 links to each other with ground; The vip input end of the described second voltage follower AMP2 links to each other with the grid of the described second N-type field effect transistor M2, and the vin input end of the described second voltage follower AMP2 links to each other with the 3rd P type image current mirror group with an end of described second resistance R 2 with the out of the described second voltage follower AMP2; The other end of described second resistance R 2 links to each other with ground; Described the 2nd P type image current mirror group links to each other with described the 3rd resistance R 3 with described N-type image current mirror group with described the 3rd P type image current mirror group.

3. the threshold voltage generative circuit described in claim 2, it is characterized in that: a described P type image current mirror group comprises an input end i0, an output terminal i1 and an output terminal i2, described output terminal i0 is the input current source, and described input end i0, described output terminal i1 with the current mirror ratio of described output terminal i2 are: i0:i1:i2=1:1:1.

4. the threshold voltage generative circuit described in claim 2, it is characterized in that: described the 2nd P type image current mirror group comprises an input end i3 and an output terminal i4, and described input end i3 with the current mirror ratio of described output terminal i4 is: i3:i4=1:2.

5. the threshold voltage generative circuit described in claim 2, it is characterized in that: described the 3rd P type image current mirror group comprises an input end i5 and an output terminal i6, and described input end i5 with the current mirror ratio of described output terminal i6 is: i5:i6=1:1.

6. the threshold voltage generative circuit described in claim 6, it is characterized in that: described N-type image current mirror group comprises an input end i7 and an output terminal i8, described input end i7 with the current mirror ratio of described output terminal i8 is: i7:i8=1:1.

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