CN103677051A - Reference source circuit - Google Patents

Abstract

The invention provides a reference source circuit comprising a reference current output end, a reference voltage output end, a reference current generation loop connected between an auxiliary power source and the reference current output end, and a reference voltage generation loop connected between the auxiliary power source and the reference voltage output end, wherein the reference voltage output end is connected with a ground terminal through a third resistor. The reference voltage generation loop is formed by connecting three branch circuits in parallel; the reference current generation loop is formed by connecting two branch circuits in parallel. The reference source circuit can output a reference voltage and a reference current at the same time, and is simple and well applicable to an analog-digital/digital-analog converter.

Description

A kind of reference source circuit

Technical field

The present invention relates to a kind of reference source circuit.

Background technology

Reference source is ingredient very important in contemporary Analogous Integrated Electronic Circuits, for voltage or the electric current with supply voltage, technique, temperature variation is provided not, it is widely used in mould-circuit such as number/D-A converter, is also most of sensors and voltage stabilizing power supply or driving source.

Yet traditional reference source is all an output reference voltage or output reference electric current only, cannot meet the demand of various digital to analog converters.

Summary of the invention

The present invention is directed to existing reference source can only output reference voltage or the defect of reference current, and the reference source circuit of a kind of output reference voltage simultaneously and reference current is provided, and is used to mould-number/D-A converter that reference voltage and bias current are provided.

The invention provides a kind of reference source circuit, there is reference current output terminal and reference voltage output end, and there is the reference current that is connected between accessory power supply and described reference current output terminal and generate loop, and being connected to the reference voltage generation loop between described accessory power supply and described reference voltage output end, described reference voltage output end is connected with earth terminal by the 3rd resistance.

Further, described reference voltage generates loop and comprises the first branch road, the second branch road and the 3rd branch road in parallel, wherein, described the first branch road comprises the first metal-oxide-semiconductor, the first triode and the first resistance being connected in series successively, the source electrode of described the first metal-oxide-semiconductor is connected to described accessory power supply, and described the first resistance is connected with described reference voltage output end; Described the second branch road comprises the second metal-oxide-semiconductor and second triode of series connection, and the source electrode of described the second metal-oxide-semiconductor is connected to described accessory power supply, and the emitter of described the second triode is connected with reference voltage output end; The grid of the grid of described the first metal-oxide-semiconductor and described the second metal-oxide-semiconductor is all connected to the first voltage bias end, and the base stage of described the first triode is connected with the base stage of described the second triode; Described the 3rd branch road comprises the 3rd metal-oxide-semiconductor and second resistance of series connection, and the source electrode of described the 3rd metal-oxide-semiconductor is connected to described accessory power supply, and described the 3rd resistance is connected with described reference voltage output end.

Further, described reference voltage generates loop and also comprises the second operational amplifier, the grid of the output terminal of described the second operational amplifier and described the 3rd metal-oxide-semiconductor is all connected to second voltage offset side, and two input ends of described the second operational amplifier are connected with the drain electrode of described the 3rd metal-oxide-semiconductor with the drain electrode of described the second metal-oxide-semiconductor respectively.

Further, described reference voltage generates loop and also comprises the first operational amplifier, the output terminal of described the first operational amplifier is connected with described the first voltage bias end, and two input ends of described the first operational amplifier are connected with the drain electrode of described the second metal-oxide-semiconductor with the drain electrode of described the first metal-oxide-semiconductor respectively.

Further, described reference current generates loop and comprises the 4th branch road and the 5th branch road, and wherein, described the 4th branch road comprises the 4th metal-oxide-semiconductor, and the source electrode of described the 4th metal-oxide-semiconductor is connected to described accessory power supply, and grid is connected with described second voltage offset side; Described the 5th branch road comprises the 5th metal-oxide-semiconductor, and the source electrode of described the 5th metal-oxide-semiconductor is connected to described accessory power supply, and grid is connected with described the first voltage bias end; The drain electrode of described the 4th metal-oxide-semiconductor is all connected with described reference current output terminal with the drain electrode of described the 5th metal-oxide-semiconductor.

Preferably, reference source circuit involved in the present invention, also comprise the first electric capacity and the second electric capacity, described the first electric capacity is connected between described accessory power supply and described the first voltage bias end, and described the second electric capacity is connected between described accessory power supply and described second voltage offset side.

Preferably, reference source circuit involved in the present invention, the breadth length ratio of described the first metal-oxide-semiconductor

the breadth length ratio of the second metal-oxide-semiconductor

breadth length ratio with the 5th metal-oxide-semiconductor

meet following condition:

${\left(\frac{W}{L}\right)}_1={\left(\frac{W}{L}\right)}_2=\frac{1}{2k}{\left(\frac{W}{L}\right)}_5,$

The breadth length ratio of described the 3rd metal-oxide-semiconductor breadth length ratio with the 4th metal-oxide-semiconductor

meet following condition:

${\left(\frac{W}{L}\right)}_3=\frac{1}{k}{\left(\frac{W}{L}\right)}_4,$

Wherein, k is predetermined value.

Preferably, reference source circuit involved in the present invention, described the first and second triodes are parasitic NPN pipe, the emitter area S of described the first triode ₁emitter area S with described the second triode ₂meet following condition:

S ₁＝N×S ₂，

Wherein, N is predetermined value.

Preferably, reference source circuit involved in the present invention, the resistance R of described the first resistance ₁resistance R with described the second resistance ₂meet following condition:

$2\ln N\×\frac{R_2}{R_1}\≈17.2.$

Reference source circuit of the present invention, simultaneously output reference voltage and reference current, and the size of reference voltage and reference current value resistance value in scale-up factor k and circuit determines, and circuit is simple, can be good at being applicable to mould-number/D-A converter.

Accompanying drawing explanation

Fig. 1 is the circuit diagram preferred embodiment of reference source circuit of the present invention.

Embodiment

Below in conjunction with accompanying drawing with preferred embodiment reference source circuit of the present invention is described in further detail.

Fig. 1 is the circuit diagram of the preferably embodiment of reference source circuit of the present invention.As shown in Figure 1, in this embodiment, reference source circuit comprises reference current output terminal and reference voltage output end, further comprises that reference voltage generates loop and reference current generates loop.

Wherein, this reference voltage output end reference voltage output end is by the 3rd resistance R 3 ground connection, for output reference voltage V _ref, reference current output terminal is for output reference electric current I _ref.

Reference voltage generates loop and has three branch roads parallel with one another, and the annexation of these three branch roads is as follows:

First route the one NMOS pipe M1, a NPN pipe T1 and the first resistance R 1 are in series, and the source electrode of a NMOS pipe M1 is connected to accessory power supply V _dD, drain electrode is connected with the collector of a NPN pipe T1, and the emitter of a NPN pipe T1 is connected with reference voltage output end by the first resistance R 1;

Second props up route the 2nd NMOS pipe M2, the 2nd NPN pipe T2 and is in series, and the source electrode of the 2nd NMOS pipe is connected to described accessory power supply V _dD, drain electrode is connected with the collector of the 2nd NPN pipe T2, base stage and the collector short circuit of the 2nd NPN pipe T2, and emitter is connected with reference source voltage output end;

Wherein, the grid of the grid of a NMOS pipe M1 and the 2nd NMOS pipe M2 is all connected to the first voltage bias end, and the base stage of a NPN pipe T1 is connected with the base stage of the 2nd NPN pipe T2.In addition, a NPN pipe T1 and the 2nd NPN pipe T2 are parasitic NPN pipe, and the emitter area S2 of the emitter area S1 of a NPN pipe T1 and the 2nd NPN pipe T2 meets: S ₁=N * S ₂;

The 3rd route the 3rd NMOS manages M3 and the second resistance R 2 series connection, and the source electrode of the 3rd NMOS pipe M3 is connected to auxiliary current source V _dD, the second resistance R 2 is connected with reference voltage output end.

In addition, this reference voltage generates loop and also comprises two operational amplifiers, and wherein the output terminal of the first operational amplifier A 1 is connected with the first voltage bias end, and two input ends are connected with the drain electrode of the 2nd NMOS pipe M2 with the drain electrode of a NMOS pipe M1 respectively.The grid of the output terminal of the second operational amplifier A 2 and the 3rd NMOS pipe M3 is all connected to the bigoted end of second voltage, and two input ends are connected with the drain electrode of the 3rd NMOS pipe with the drain electrode of the 2nd NMOS pipe M2 respectively.

The first operational amplifier A 1 equates the drain voltage of a NMOS pipe M1, the 2nd NMOS pipe M2, and make the electric current matched in a NMOS pipe M1, the 2nd NMOS pipe M2, simultaneously the output voltage of the first operational amplifier A 1 grid of a NMOS pipe M1, the 2nd NMOS pipe M2 and the 5th NMOS pipe M5 of setovering.

The second operational amplifier A 2 makes the voltage at the second resistance R 2 two ends equal the 2nd NPN pipe base stage of T2 and the voltage V of emitter _bE2.

Reference current generates loop and comprises the 4th branch road and the 5th branch road, and the 4th branch road comprises the 4th NMOS pipe M4, and the source electrode of the 4th NMOS pipe M4 is connected to accessory power supply V _dD, grid is connected with second voltage offset side.

The 5th branch road comprises the 5th NMOS pipe M5, and the source electrode of the 5th NMOS pipe M5 is connected to accessory power supply V _dD, grid is connected with the first voltage bias end.

The drain electrode of the 4th NMOS pipe is all connected with reference current output terminal with the drain electrode of the 5th NMOS pipe.

Wherein a NMOS manages the breadth length ratio of M1

the breadth length ratio of the 2nd NMOS pipe M2

breadth length ratio with the 5th NMOS pipe M5

meet following condition:

${\left(\frac{W}{L}\right)}_1={\left(\frac{W}{L}\right)}_2=\frac{1}{2k}{\left(\frac{W}{L}\right)}_5,$

The breadth length ratio of the 3rd NMOS pipe M3

breadth length ratio with the 4th NMOS pipe M4

meet following condition:

${\left(\frac{W}{L}\right)}_3=\frac{1}{k}{\left(\frac{W}{L}\right)}_4,$

Wherein, k is predetermined value.

Further, the reference source of the present embodiment also comprises that the first capacitor C 1 and the second capacitor C 2, the first capacitor C 1 are connected to accessory power supply V _dDand between the first voltage bias end, the second capacitor C 2 is connected to accessory power supply V _dDand between second voltage offset side.The first capacitor C 1 and the second capacitor C 2 are for providing frequency loop compensation.

According to above circuit, known in conjunction with Fig. 1, a NMOS pipe M1, the 2nd NMOS pipe M2 and the 5th NMOS pipe M5 form the first current mirror, and the 3rd NMOS pipe M3 and the 4th NMOS pipe M4 form the second current mirror.

Because the voltage at the second resistance R 2 two ends equals the 2nd NPN pipe base stage of T2 and the voltage V of emitter _bE2therefore, the drain current of the 3rd NMOS pipe M3

For a NPN pipe T1, the 2nd NPN pipe T2, have respectively in addition

the reverse saturation current of the NPN pipe emitter junction that wherein Is is unit area.

Therefore the pressure drop in the first resistance R 1 is:

$V_{\mathrm{BE}1}-V_{\mathrm{BE}2}=V_T\ln \left(\frac{I_{C1}}{I_S}\right)-V_T\ln \left(\frac{I_{C2}}{{\mathrm{NI}}_S}\right)=V_T\ln \left(\frac{I_{C1}}{I_S}\frac{{\mathrm{NI}}_S}{I_{C2}}\right)=V_T\ln N.$

According to a NMOS pipe M1, the 2nd NMOS pipe M2, form the first current mirror, thereby the current value on the first branch road and the second branch road is:

$I_{D1}=I_{D2}\≈\frac{V_{\mathrm{BE}1}-V_{\mathrm{BE}2}}{R_1}=\frac{V_T\ln N}{R_1},$ Ignore NPN pipe base current herein.

Therefore, the pressure drop in the 3rd resistance R 3 is

$V_{\mathrm{ref}}=R_3(I_{D1}+I_{D2}+I_{D3})=R_3(\frac{{2V}_T\ln N}{R_1}+\frac{V_{\mathrm{BE}}}{R_2})=\frac{R_3}{R_2}(V_{\mathrm{BE}}+2\ln N\×\frac{R_2}{R_1}\×V_T).$

In order to obtain the zero-temperature coefficient characteristic of output voltage, need to meet

thereby output voltage V _refsize only by the ratio of the 3rd resistance R 3 and the second resistance R 2, determined.

In like manner, a NMOS pipe M1, the 2nd NMOS pipe M2 and the 5th NMOS pipe M5 form the first current mirror, the drain current of the 5th NMOS pipe M5 due to the 3rd NMOS pipe M3 and the 4th NMOS pipe M4 formation current mirror, therefore the drain current of the 4th NMOS pipe

Therefore obtaining output current is:

$I_{\mathrm{ref}}=I_{D4}+I_{D5}=\frac{2k\ln N\×V_T}{R_1}+\frac{{\mathrm{kV}}_{\mathrm{BE}}}{R_2}=\frac{k}{R_2}(V_{\mathrm{BE}}+2\ln N\×\frac{R_2}{R_1}\×V_T).$

Equally, in order to obtain the zero-temperature coefficient characteristic of output current, need to meet

therefore, the ratio of scale-up factor k and R2 has determined output current I _refsize.

Therefore, utilize reference source circuit of the present invention, simultaneously output reference voltage and reference current, and the size of reference voltage and reference current value resistance value in scale-up factor k and circuit determines, and circuit is simple, can be good at being applicable to mould-number/D-A converter.

In addition; the present embodiment is only for illustrating a preferred embodiment of the present invention; protection scope of the present invention is not limited to the content in above-described embodiment; under the prerequisite that does not depart from purport, can there be many variations; for example; NPN pipe in this embodiment can be all types of triodes, such as positive-negative-positive triode etc.Again for example, the NMOS pipe in this embodiment can be all types of metal-oxide-semiconductors, such as PMOS pipe etc.

Claims (10)

1. a reference source circuit, it is characterized in that, this reference source circuit has reference current output terminal and reference voltage output end, and there is the reference current that is connected between accessory power supply and described reference current output terminal and generate loop, and being connected to the reference voltage generation loop between described accessory power supply and described reference voltage output end, described reference voltage output end is connected with earth terminal by the 3rd resistance.

2. reference source circuit according to claim 1, is characterized in that, described reference voltage generates loop and comprises the first branch road, the second branch road and the 3rd branch road in parallel, wherein,

Described the first branch road comprises the first metal-oxide-semiconductor, the first triode and the first resistance being connected in series successively, and the source electrode of described the first metal-oxide-semiconductor is connected to described accessory power supply, and described the first resistance is connected with described reference voltage output end;

Described the second branch road comprises the second metal-oxide-semiconductor and second triode of series connection, and the source electrode of described the second metal-oxide-semiconductor is connected to described accessory power supply, and the emitter of described the second triode is connected with reference voltage output end;

The grid of the grid of described the first metal-oxide-semiconductor and described the second metal-oxide-semiconductor is all connected to the first voltage bias end, and the base stage of described the first triode is connected with the base stage of described the second triode;

Described the 3rd branch road comprises the 3rd metal-oxide-semiconductor and second resistance of series connection, and the source electrode of described the 3rd metal-oxide-semiconductor is connected to described accessory power supply, and described the 3rd resistance is connected with described reference voltage output end.

3. reference source circuit according to claim 2, it is characterized in that, described reference voltage generates loop and also comprises the second operational amplifier, the grid of the output terminal of described the second operational amplifier and described the 3rd metal-oxide-semiconductor is all connected to second voltage offset side, and two input ends of described the second operational amplifier are connected with the drain electrode of described the 3rd metal-oxide-semiconductor with the drain electrode of described the second metal-oxide-semiconductor respectively.

4. reference source circuit according to claim 2, it is characterized in that, described reference voltage generates loop and also comprises the first operational amplifier, the output terminal of described the first operational amplifier is connected with described the first voltage bias end, and two input ends of described the first operational amplifier are connected with the drain electrode of described the second metal-oxide-semiconductor with the drain electrode of described the first metal-oxide-semiconductor respectively.

5. reference source circuit according to claim 2, is characterized in that, described reference current generates loop and comprises the 4th branch road and the 5th branch road, wherein,

Described the 4th branch road comprises the 4th metal-oxide-semiconductor, and the source electrode of described the 4th metal-oxide-semiconductor is connected to described accessory power supply, and grid is connected with described second voltage offset side;

Described the 5th branch road comprises the 5th metal-oxide-semiconductor, and the source electrode of described the 5th metal-oxide-semiconductor is connected to described accessory power supply, and grid is connected with described the first voltage bias end;

The drain electrode of described the 4th metal-oxide-semiconductor is all connected with described reference current output terminal with the drain electrode of described the 5th metal-oxide-semiconductor.

6. reference source circuit according to claim 3, it is characterized in that, also comprise the first electric capacity and the second electric capacity, described the first electric capacity is connected between described accessory power supply and described the first voltage bias end, and described the second electric capacity is connected between described accessory power supply and described second voltage offset side.

7. reference source circuit according to claim 5, is characterized in that, the breadth length ratio of described the first metal-oxide-semiconductor

the breadth length ratio of the second metal-oxide-semiconductor

breadth length ratio with the 5th metal-oxide-semiconductor

meet following condition:

${\left(\frac{W}{L}\right)}_1={\left(\frac{W}{L}\right)}_2=\frac{1}{2k}{\left(\frac{W}{L}\right)}_5,$

The breadth length ratio of described the 3rd metal-oxide-semiconductor

breadth length ratio with the 4th metal-oxide-semiconductor meet following condition:

${\left(\frac{W}{L}\right)}_3=\frac{1}{k}{\left(\frac{W}{L}\right)}_4,$

Wherein, k is predetermined value.

8. reference source circuit according to claim 2, is characterized in that, described the first and second triodes are parasitic NPN pipe, the emitter area S of described the first triode ₁emitter area S with described the second triode ₂meet following condition:

S ₁＝N×S ₂，

Wherein, N is predetermined value.

9. reference source circuit according to claim 8, is characterized in that, the resistance R of described the first resistance ₁resistance R with described the second resistance ₂meet following condition:

$2\ln N\×\frac{R_2}{R_1}\≈17.2.$

10. according to the reference source circuit described in any one in claim 2-9, it is characterized in that, described metal-oxide-semiconductor is NMOS pipe.