CN103227741B - 数据处理装置、输入控制装置和控制方法 - Google Patents

数据处理装置、输入控制装置和控制方法 Download PDF

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Publication number
CN103227741B
CN103227741B CN201310022120.7A CN201310022120A CN103227741B CN 103227741 B CN103227741 B CN 103227741B CN 201310022120 A CN201310022120 A CN 201310022120A CN 103227741 B CN103227741 B CN 103227741B
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data
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CN103227741A (zh
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原裕司
石川尚
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Canon Inc
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Canon Inc
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    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/40—Bus structure
    • G06F13/4063—Device-to-bus coupling

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  • Engineering & Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Multi Processors (AREA)
  • Bus Control (AREA)
CN201310022120.7A 2012-01-26 2013-01-22 数据处理装置、输入控制装置和控制方法 Expired - Fee Related CN103227741B (zh)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
JP2012014576 2012-01-26
JP2012-014576 2012-06-19
JP2012238359A JP6139857B2 (ja) 2012-01-26 2012-10-29 データ処理装置、入力制御装置、及び制御方法
JP2012-238359 2012-10-29

Publications (2)

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CN103227741A CN103227741A (zh) 2013-07-31
CN103227741B true CN103227741B (zh) 2016-09-28

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US (1) US9690740B2 (https=)
JP (1) JP6139857B2 (https=)
CN (1) CN103227741B (https=)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP6882681B2 (ja) * 2017-07-12 2021-06-02 富士通株式会社 情報処理システム、情報処理装置、及び情報処理システムの制御方法
US20190020586A1 (en) * 2017-07-14 2019-01-17 Qualcomm Incorporated Selective insertion of a deadlock recovery buffer in a bus interconnect for deadlock recovery
CN113590356B (zh) * 2021-07-29 2023-08-11 网易（杭州）网络有限公司 数据通信方法、装置和电子设备

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5613069A (en) * 1994-12-16 1997-03-18 Tony Walker Non-blocking packet switching network with dynamic routing codes having incoming packets diverted and temporarily stored in processor inputs when network ouput is not available
JP2006245790A (ja) * 2005-03-01 2006-09-14 Fujitsu Ltd リング型伝送システム
JP4869369B2 (ja) * 2009-03-13 2012-02-08 キヤノン株式会社 情報処理装置、情報処理方法およびプログラム
JP5538798B2 (ja) 2009-03-17 2014-07-02 キヤノン株式会社 データ処理装置およびデータ処理方法またはプログラム
JP5550261B2 (ja) 2009-05-29 2014-07-16 キヤノン株式会社 リングバスを用いたデータ処理装置、データ処理方法およびプログラム
JP5460156B2 (ja) 2009-07-14 2014-04-02 キヤノン株式会社 データ処理装置
JP5932242B2 (ja) 2011-05-20 2016-06-08 キヤノン株式会社 情報処理装置、通信方法、及びプログラム

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JP6139857B2 (ja) 2017-05-31
JP2013175156A (ja) 2013-09-05
US9690740B2 (en) 2017-06-27
US20130198431A1 (en) 2013-08-01
CN103227741A (zh) 2013-07-31

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Granted publication date: 20160928