CN103165476A - 集成电路封装以及封装方法 - Google Patents

集成电路封装以及封装方法 Download PDF

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Publication number
CN103165476A
CN103165476A CN2012105991410A CN201210599141A CN103165476A CN 103165476 A CN103165476 A CN 103165476A CN 2012105991410 A CN2012105991410 A CN 2012105991410A CN 201210599141 A CN201210599141 A CN 201210599141A CN 103165476 A CN103165476 A CN 103165476A
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chip
package module
metal level
package
rear side
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CN2012105991410A
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F·德赫
G·迈耶-贝格
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Infineon Technologies AG
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Infineon Technologies AG
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Priority claimed from US13/326,527 external-priority patent/US9105562B2/en
Application filed by Infineon Technologies AG filed Critical Infineon Technologies AG
Publication of CN103165476A publication Critical patent/CN103165476A/zh
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Abstract

本发明公开了集成电路封装以及封装方法。一种集成电路封装方法包括：由限定电路互连的连续建立层制造封装模块；在封装模块的顶侧上形成腔；将芯片的金属化后侧附着到金属层，所述芯片具有带有至少一个前部触点的前侧；将所述芯片布置在所述腔中，使得至少一个前部触点被电连接到封装模块的电路互连中的至少一个；以及将附着到芯片的金属层耦合到封装模块的顶侧上。

Description

集成电路封装以及封装方法
对相关申请的交叉引用
本申请是2011年5月9日提交的、顺序号为13/103,124的、现在未决的美国申请的部分继续申请，该申请的全部在此被结合以作参考。
技术领域
本公开涉及用于制造电路的装置和方法，并且更特别地涉及用于封装集成电路的装置和方法。
背景技术
集成电路(IC)芯片通常被结合到封装中。这种封装例如提供物理的和环境的保护以及热消散。而且，封装的芯片典型地提供电引线以允许与另外的部件相集成。
已经开发出几种IC封装技术。一种这样的技术例如在2006年7月27日提交的并于2007年2月1日公布为US2007/0025092A1的、顺序号为11/494,259的、Lee等人的美国专利申请“Embedded Actives and Discrete Passives in a CavityWithin Build-up Layers”中被描述，该申请的内容由此被全部结合以作参考。Lee等人尤其公开了所谓的芯片最后嵌入(chip-last)方法。
与芯片首先嵌入或芯片中间嵌入工艺形成对比，芯片最后嵌入方法是在完成所有建立层(build-up layer)工艺之后嵌入给定的芯片。该方法的优点现在是众所周知的，然而，芯片最后嵌入的封装不被认为适合于所有芯片类型。例如，对于具有后侧触点(back-side contact)的IC，以及对于其操作参数需要更高散热量的那些芯片，例如功率芯片和高性能逻辑芯片。
发明内容
在一个实施中，为了提供适合于各种各样的芯片类型(包括功率芯片、具有后侧触点的芯片、以及高性能逻辑芯片)的封装模块，一种集成电路封装方法包括：由限定电路互连的连续的建立层制造封装模块；在所述封装模块的顶侧上形成腔；将芯片的金属化后侧附着到金属层上，所述芯片具有带有至少一个前部触点的前侧；将所述芯片布置在所述腔中，使得前部触点的组被电连接到所述封装模块的电路互连中的一个或多个；以及将附着到所述芯片的所述金属层耦合到所述封装模块上。
类似地，在另一实施中，一种集成电路封装包括具有在其中形成的腔的封装模块。所述封装模块可以被形成为来自限定顶侧、底侧以及二者之间的电路互连的连续建立层的叠层。在芯片最后嵌入方法之后，所述腔可以被形成在所述封装模块的顶侧上。典型地，所述腔的形成暴露所述电路互连中的一个或多个，例如在所述腔的底部。芯片具有带有前部触点的组的前侧以及附着到金属层的金属化后侧，使得所述金属层覆盖所述芯片的后侧的至少一部分，以及所述封装模块的顶侧可以被布置在所述腔中，使得前部触点的所述组被电连接到所述封装模块的电路互连中的一个或多个。所述芯片被布置在所述腔中，使得前部触点的所述组被电连接到所述封装模块的电路互连中的一个或多个，并且所述金属层覆盖所述封装模块的顶侧的至少一部分。
在上面的实施中可以包括或者组合下列特征中的一个或多个。将芯片的金属化后侧附着到金属层上可以利用高温工艺来完成。将芯片的金属化后侧附着到金属层上可以利用扩散焊接工艺来完成。金属层可以是金属箔层。芯片的后侧可以是低欧姆触点。电流可以在低欧姆触点和芯片的前部触点的组之间垂直地流动。芯片可以是功率电子芯片。低欧姆触点可以例如通过与金属层的电连接被电连接到在封装模块中形成的一个或多个通路(via)。芯片可以是高性能逻辑芯片。金属层可以具有促进热扩散的导热特性。金属层可以被附着到热沉。芯片可以包括直通硅通路。金属层的全部或者部分可以通过隔离中间层被耦合到芯片的后侧和封装模块的顶侧。芯片可以被安装成反向安装配置。反向安装配置是其中芯片的金属化后侧面朝印刷电路板并且芯片的前侧背朝印刷电路板。
附图说明
为了进一步阐明本发明的上面的和其他的优点和特征，将参照在附图中示出的其特定实施例来提供本发明的更详细的描述。认识到的是，这些附图仅仅描绘本发明的典型实施例，并且因此不应被认为是限制本发明的范围。将通过使用附图、利用附加的特殊性和细节来描述和解释本发明，其中：
图1-3从剖面图示出用于制造示例性封装模块的示例性工艺流程；
图4示出带有具有后侧触点的芯片的示例性集成电路封装的剖面图；
图5示出具有顶层的示例性集成电路封装的剖面图；
图6示出具有热沉和/或金属箔层的示例性集成电路封装的剖面图；
图7-9示出具有顶侧封装触点的如图4-6中的示例性集成电路封装的剖面图；
图10-12示出具有顶侧垫(pad)和/或隔离中间层的如图4-6中的示例性集成电路封装的剖面图；
图13示出具有多个芯片的示例性集成电路封装的剖面图；
图14示出具有隔离的热扩散层的示例性集成电路封装的剖面图；
图15示出带有具有直通硅通路的芯片的示例性集成电路封装的剖面图；
图16和17示出具有在电镀的、溅射的、或结构化金属上的纳米金属或焊料以及其上可选的隔离热沉和/或金属箔层的后侧的示例性集成电路封装的剖面图；
图18-21从剖面图示出用于制造示例性封装模块的另一示例性工艺流程；
图22示出处于反向安装配置的示例性集成电路封装的剖面图；以及
图23-26示出处于反向安装配置的示例性集成电路封装的剖面图的各种另外的实施例。
具体实施方式
现在将参照附图，其中相同的结构将具有相同的附图标记。不用说，附图是本发明的示例性实施例的图示的和示意性的表示，并且不限制本发明，它们也不一定是按比例绘制的。
图1-3从剖面图示出用于制造示例性封装模块10的示例性工艺流程。用于集成电路封装的所述示例性工艺流程或方法可以被如下实施。
在图1中，封装模块2可以开始由限定顶侧3、底侧1和电路互连4的连续建立层(叠层)形成。这种电路互连4可以是以下面关于通路5描述的方式形成的通路，和/或包括例如嵌入式无源部件(例如电路布线、电容器、电阻器、和/或电感器)。例如，它可以包括例如由结构化金属形成的分层布线(routing)8。电路互连4可以使用标准高密度互连技术来制成，并且可以具有在封装模块2的底侧1上提供的与其电耦合的底侧垫6。此外，除了传统分层技术，建立分层工艺还可以包括在超薄型芯上沉积薄膜。
通路5还可以通过例如机械数字控制(NC)钻孔、激光钻孔、形成连续建立层、或者通过本领域已知的其他手段来形成在封装模块2中。在形成通路孔之后，通路5可以通过例如无电极电镀或者电解电镀来金属化。
焊球12可被提供成与通路5和/或电路互连4电连接，从而在集成电路封装10的封装模块2的底侧1上提供接触端，以用于连接例如到印刷电路(PC)板。
在图2中，针对封装模块2的形成来添加另外的连续建立层。该工艺导致将无源部件嵌入到封装模块2中。以这种方式，所述封装的所有层可以包含用于例如信号、功率和接地的布线的结构化金属。
在图3中，在封装模块2的顶侧3上形成腔14。除其他技术外，激光钻孔也可以被用来形成腔14。一旦形成腔14，则连接垫(如果不是已经存在的话)可以通过常规方法被添加到在腔14中暴露的电路互连4。正如下面参照图4讨论的那样，腔14应当优选地被形成为使得芯片16能够被布置在腔14中。
图4示出带有具有后侧触点的芯片16的示例性集成电路封装40的剖面图。这种芯片包括例如IGBT，通过所述IGBT，电流从芯片的后侧触点垂直地(即从后侧通过硅衬底到前侧)流到其前侧。具有前部触点7的组并且取决于芯片的类型而在后侧18上具有后侧触点20的芯片16被布置到腔14中，使得前部触点7被电连接到封装模块2的电路互连4中的一个或多个。芯片16的后侧18通常在晶片处理期间被金属化。因此，如在此所述的在封装期间对芯片的进一步处理被理解为不同的工艺和不同的所得到的层。芯片16的前部触点7可以在芯片的正常制造工艺期间形成，并且可以通过电路互连4被电连接到封装模块2的底侧1。芯片16和封装模块2之间的间隙(如果存在的话)可以例如利用填充材料22来填充。填充材料22还可以被用作未充满填充材料(未示出)，从而嵌入芯片。
其他配置可以包括，芯片16是高性能逻辑芯片。这种高性能逻辑芯片可以包括例如
Figure BSA00000854900600041
CoreTM、
Figure BSA00000854900600042
Phenom IITM或Z196TM。另一配置可以包括，芯片16是薄化的芯片。
图5示出具有顶层的示例性集成电路封装50的剖面图。例如通过电镀(正如例如在叠层材料的表面处理形成封装模块2之后)到如上面相对于集成电路封装10(图1-3)所讨论的封装模块2的顶侧3的至少一部分和芯片16的后侧18的至少一部分上来提供顶层24。可替换地，顶层可以是溅射的金属、在溅射之后电镀的、通过施加脏等离子而形成的金属层、或者在芯片和/或封装模块2的顶侧3的一些或全部上方喷射的油墨。典型地，顶层24可以被耦合到芯片16的后侧18，并且覆盖芯片16和封装模块2的顶侧的至少一部分。有利的是，顶层24可以是金属层，举例来说，例如铜或者结构化金属。取决于所使用的芯片的应用和类型，芯片16和顶层24之间的耦合可以与芯片16的后侧18建立热的和/或电的连接。
在其中顶层24与芯片16的后侧18之间建立电连接的实施中，顶层24可以有利地被定位成与一个或多个通路5电接触，从而建立从芯片16的后侧18到封装模块2的底侧1的电连接。特别是，对于具有后侧触点20的芯片，在触点20和底侧1之间的电连接因此被建立。
在使用中，集成电路封装50可以通过例如PC板(未示出)被连接到外部电路。通过在封装模块2的底侧1处建立的电连接而提供给芯片16的电流通过电路互连4流到芯片16的前部触点，并通过通路5流到后侧触点20。例如，芯片16可以是所谓的“功率芯片”或者具有低欧姆后侧触点的功率电子芯片。这种芯片可以利用垂直地流过芯片(例如在后侧18朝向前部触点7之间)的电流来进行操作。在这种情况下，后侧触点20典型地是低欧姆触点，其可以在芯片16的制造期间或者之后被形成在芯片16上。在这种情况下，当以图5的电路封装50的配置来使用时，在低欧姆后侧触点20和通路5之间的电接触允许上面在图1-3中所描述的基本集成电路封装10通过添加导电顶层24而与具有低欧姆后侧触点的功率芯片一起运行。
除了向集成电路封装50中的后侧电连接提供入口外，当与具有较低电流处理能力或电流要求的芯片相比时，在高性能应用中使用功率芯片也可能生成附加热。由于除了其传导电流的能力之外还为了扩散热而选择的材料的特性，顶层24中所使用的材料的仔细的选择可以有帮助。因此，诸如铜、铜合金、银、镍、以及具有高的热和/或电导率的类似材料特别适合用作顶层24。当以这种方式用于消散热时，芯片16和顶层24之间良好的热耦合是所期望的。通过最大化顶层24的表面积、以及例如暴露于周围空气的该面积的百分比，和/或通过增加顶层24的厚度以增加热质量和/或确保通过传导而遍及顶层24的高效热扩散，可以获得进一步的热消散效率。
在芯片16的操作期间生成的热没有被集成电路封装50充分地消散的情况下，可以添加附加热结构而不影响顶层24用作到后侧触点(例如芯片16的后侧触点20)的电连接的能力。因此，并且正如下面参照例如图6所描述的那样，顶层24可以被配置成充当电连接器和热扩散器这二者，从而产生电路封装60，其除了集成电路封装50的电特性之外还具有优秀的热特性。
尽管一些芯片(例如高性能逻辑芯片)可能不具有低欧姆后侧触点20，但是这种高性能逻辑芯片可能(类似于功率芯片)生成超过由该芯片或者由其封装所容易地消散的高温的高温。在这种情况下，可以从提供良好热扩散特性的材料(例如铜)中选择顶层24。因此，顶层24可以由促进上述功能的任何材料、特别是特定芯片16可能需要的具有高的电和/或热传导特性的材料制成。因此，无论是否需要到芯片的后侧的电接触，本封装配置向能够容纳具有各种各样的设计要求的芯片的封装提供与芯片最后嵌入方法一致的结构和方法。
如果顶层24由金属构成，则它可以例如利用任何合适类型的电镀金属、溅射金属、结构化金属、金属箔或者它们的组合来实施，而且，例如在金属箔的情况下，可以例如通过将顶层24粘合或者焊接到芯片16而被附着，以及例如通过粘合剂被附着到封装模块2的顶侧。也可以使用其他施加方法，例如用纳米膏、通过利用脏等离子的沉积、或者通过溅射或焊料。取决于配置，上述中的一个或多个可以被组合使用，例如考虑到材料的相互之间的亲和力。
脏等离子被称为具有载气的等离子，所述载气具有悬浮在其中的颗粒大小的金属粉末。在芯片16已被放置在封装模块2内之后形成具有足够的材料厚度和最少的附加处理的层以获得顶层24中，该方法特别有利。
如果顶层24被粘合，则可能期望的是，胶粘剂拥有高的电和/或热传导特性以便促进如前所述的与顶层24的电和/或热连接性的优点。这种胶粘剂的实例包括例如
Figure BSA00000854900600061
TS-333TM以及
Figure BSA00000854900600062
MT-815TM。相反，在期望隔离(热和/或电)的情况下，为了该目的而将选择不同的材料。
在其中顶层24可能利用焊料被附着的其他配置中，焊接可能包括易熔焊接。另一配置可能包括作为顶层24的纳米金属。在这种配置中，金属本身可能自然地作为其施加的一部分而被粘附为芯片16的后侧18上的顶层24，并且被粘附到封装模块2的顶侧。
通路5可以终止于焊球12，焊球12又可以被用来连接到外部电路，举例来说，例如印刷电路板。这允许低欧姆后侧触点20被连接到封装模块2的底侧1并从其连接到封装40外部的电路。另外的通路5会是有益的，例如在需要接地触点的逻辑芯片中，或者为了射频(RF)屏蔽的目的。类似地，通路5会是有益的，例如在接地功率芯片中。
为了平衡在例如高性能芯片中的电负载，多个通路5可以被连接到顶层24以分裂跨过多个通路5的电流。在另一应用中，通路5在被连接到如所述的低欧姆后侧触点34时，可以充当反馈回路的一部分。
如上所述，顶层24可以用作热扩散器，以代替封装模块2的后侧触点20和底侧1之间的电连接的一部分或者作为对其的添加。当顶层24的表面积典型地超过芯片16的后侧18的面积时，通过顶层24中的热扩散，来自芯片16的热消散的显著增加将发生，这取决于所使用的材料及其配置(例如厚度)。然而，在需要附加热消散的情况下，可以提供附加热结构。
图6示出具有热沉和/或金属箔层26的示例性集成电路封装60的剖面图。如所示，顶层24可以被直接地附着到热沉和/或金属箔层26从而提供与其的热接触。热沉和/或金属箔层26可以被附着，例如机械地或者利用纳米膏、胶粘剂、脏等离子(例如与电镀和焊料相组合)、或焊料(例如在溅射和电镀了5μm的铜之后)、热化合物或者易熔焊接而被粘附到顶层24。
在其中26用作热沉的实例中，它可以被设计成例如具有直鳍或针鳍，并由铜或铝或具有高热传导率的其他材料构成以提高其效率。而且，这种热沉优选地由周围空气很好地通风。借助顶层24的热扩散特性，例如当顶层24由铜形成时，热沉的效率被改进。
在其中26是金属箔层的实例中，它可以被耦合到顶层60上，并由例如铜构成。金属箔层26可以用来达到与热沉相同的目的，即，金属箔层可以用作用于消散热的装置，和/或还可以在高电流负载下有帮助，例如在层24和26一起工作以提供到芯片16的后侧触点20的电接触的情况下。
其他热沉方法也可被用于热沉和/或金属箔层26。例如，有源风扇可以在一组热沉鳍上吹送凉的外部空气。在另一实例中，热沉可以利用循环液体的装置来进行液体冷却。
图7-9示出具有顶侧封装触点28的如图4-6中的示例性集成电路封装(分别是70、80和90)的剖面图。在这种可替换方法中，顶侧3具有施加于其的触点，从而形成顶侧封装触点28。类似于图5和6，顶层24可以被直接地附着到顶侧封装触点28和后侧触点20。此外，可替换地或者另外，热沉和/或金属箔层26可以被附着到集成电路封装。
图10-12示出具有顶侧垫30和/或隔离中间层32的如图4-6中的示例性集成电路封装(分别是100、110和120)的剖面图。顶侧垫30可以被形成在封装模块2的顶侧3上。顶层24可以通过隔离中间层32被耦合到芯片16的后侧18和封装模块2的顶侧。隔离中间层可以将例如通路5的子集和与顶层24的直接电接触相隔离。这种布置可能是有用的，例如在芯片堆叠布置中，或者在隔离的通路35已被连接(例如通过如上面结合图1-3所公开的分层布线的各种配置)到另一设备或者将被保留以建立与顶层24不相关的其他连接的情况下。而且，可以有其上的金属构图，包括例如在顶层24、隔离中间层32、电路互连4的连接垫、前部触点7、通路5、和/或隔离通路35的一部分上。这种金属构图可以例如被采用以用于其间的电布线。
图13示出具有多个芯片36、34的示例性集成电路封装130的剖面图。也可以形成上面实施例的组合。例如，根据如在此所述的芯片最后嵌入方法，功率芯片36可以被封装，连同利用相同的芯片最后嵌入技术的逻辑芯片34。也就是，在封装模块2内可以形成两个或更多个腔。类以地，如上所述的两个或更多个芯片可以被布置在腔内，并且如前所述的被物理、电和/或热连接。在逻辑芯片加上功率芯片的配置中，顶层24的一部分可以被用于例如逻辑芯片34和低功率芯片36之间的电布线。可替换地，可以在封装模块2内进行电布线。作为另一可替换方案，集成电路封装130可以包括隔离中间层32，该隔离中间层32可以将芯片34与和顶层24的物理、电和/或热接触相隔离。
图14示出具有隔离热扩散层38的示例性集成电路封装140的剖面图。隔离热扩散层38是电隔离的并且导热。AIN填充的胶粘剂可以被施加例如以实现电隔离而传导热的功能。在期望将顶层24的部分与上层(举例来说，例如热沉和/或金属箔层26)电隔离的情况下，这种配置会是有利的。
图15示出带有具有直通硅通路(TSV)37的芯片的示例性集成电路封装150的剖面图。TSV37垂直地穿过芯片16，并且因此提供在后侧上的电连接。通过促进更高的三维密度和/或降低到后侧18的接触电阻，TSV可以有助于提高性能。TSV37可以可选地被直接地耦合到芯片16的前部触点7或者芯片16的内部电路(未示出)。TSV也可以被用在多个芯片配置中，例如上面参照图13描述的示例性集成电路封装130。
图16和17示出具有在电镀的、溅射的、或结构化金属上的纳米金属或焊料以及其上可选的隔离热沉和/或金属箔层26的后侧的示例性集成电路封装(分别是160和170)的剖面图。特别地，图16和17描绘了在顶层24、顶侧封装触点28、和热沉和/或金属箔层26中构造的结构化凹口39。结构化凹口39例如用作封装模块2的顶侧18上的电布线的一部分。这种布线例如可以被用来电连接堆叠的芯片41。施加印刷的金属结构的一些方法包括例如喷墨或者所谓的丝网或模版印刷。虽然这两种方法都可以被用来施加结构化金属，但是丝网印刷通常不大昂贵，而喷墨产生更薄的且更精细的间距的应用。
图18-21从剖面图示出用于制造示例性封装模块的另一示例性工艺流程。用于集成电路封装的所述示例性工艺流程或方法可以被如下实施。
在图18中，封装模块2以类似于在图1-3及其上面的伴随描述中所描述的工艺流程的方式来形成。特别地，封装部分180包括封装模块2，并且由限定顶侧3、底侧1和电路互连4的连续建立层(叠层)来制造。这种电路互连4可以是以上面关于通路5描述的方式形成的通路，和/或包括例如嵌入式无源部件(例如电路布线、电容器、电阻器、和/或电感器)。例如，它可以包括例如由结构化金属形成的分层布线8。电路互连4可以使用标准高密度互连技术来制成，并且可以具有在封装模块2的底侧1上提供的与其电耦合的底侧垫6。此外，除了传统分层技术，建立分层工艺还可以包括在超薄型芯上沉积薄膜。腔14被形成在封装模块2的顶侧3上。焊球12可以被提供成与通路5和/或电路互连4电连接，从而在集成电路封装10的封装模块2的底侧1上提供接触端，以用于连接例如到印刷电路(PC)板。
图19示出具有光结构化表面43的金属层45。光结构表面43可以被用来提供用于金属层45的结构，并且可以使用几种方法以实现提供用于金属层45的结构的目标。例如，如果光结构表面43是永久抗蚀剂，则它被层叠到金属层45上、利用适当的曝光设备来成像、显影并且然后从金属层45剥离。可替换地，激光直接结构化(LDS)可以被用来从金属层45中去除光结构表面43的所期望的部分。另一可替换方案可以包括利用聚酰亚胺(PI)来喷涂金属层45以作为光结构化表面43。在PI作为光结构化表面43被施加到金属层45之后，允许其变干并且然后曝光、显影和剥离。使用PI作为光结构化表面43可以在后续高温处理期间提供稳定性。作为另一可替换方案，光结构表面43可以被省略或者利用金属层45上的印刷焊料停止器(stop)来替代。
由光结构表面43提供的结构对于如下面相对于图20描述的精确处理是有用的。光结构化表面43的曝光优选精确到微米。一旦已经进行了光结构化表面43的所期望的曝光和处理，就将在金属层45上留下小框架。小框架42从剖面图被示出为没有光结构表面43的芯片区域44，而围绕芯片区域44的区域具有存在的光结构表面43。这种小框架例如可以是约100微米。所述小框架应当优选地匹配芯片16的尺寸和附着位置。
图20示出具有带有前部触点7的前侧以及后侧18的芯片16。芯片16例如是功率电子芯片和/或高性能逻辑芯片。芯片16的后侧18可以包括低欧姆触点。图20还描绘了已被附着到芯片16的后侧18以形成芯片部分190的金属层45。金属层45可以例如是金属箔层，并且可以具有促进热扩散的导热特性。而且，金属层45例如可能包含结构化凹口，并且还可以被附着到热沉以促进进一步的热扩散。
将芯片16附着到金属层45可能涉及高温工艺，例如在可能超过封装部分180的容限的温度下进行的扩散焊接。扩散焊接典型地在相对较高的温度下被执行以便薄化焊料。扩散焊接例如通常超过200摄氏度。芯片16和金属层45之间的扩散焊接优选地远程地并且在将芯片16布置到腔14中之前来执行。因此，封装模块2可能不需要被构造成耐受执行扩散焊接或其他高温工艺通常所需的相对较高的温度。
在附着期间将芯片16正确地定位到金属层45上时，光结构表面43会是有用的。在高温工艺(例如其中焊料流动和蒸发相对不可预测的扩散焊接)中，光结构表面43可能特别有用。通过将光结构表面43形成为如上面相对于图19所述的小框架，焊料流动和蒸发可以被限制在芯片16的附着位置。因此，光结构化表面43可以被用于到金属层45上的精确焊接。钻孔47也可被制成穿过金属层45，以便在如图21中所示的集成芯片部分190和封装部分180中提供用于光学对准的装置。
在图21中，芯片部分190与封装部分180相集成，使得芯片16被布置在腔14中。芯片16被布置在腔14中，使得前部触点7被电连接到封装模块2的电路互连4中的一个或多个，并且金属层45被耦合到封装模块2的顶侧3。金属层45可以通过可用于提供物理和/或电耦合的各种装置被耦合到封装模块2的顶侧3。可以使用X射线成像以便在附着期间相对于封装部分180正确地对准芯片部分190，这是由于即使通过金属层45，铜通路通常也应当是可见的。金属层45可以被耦合到封装模块2的顶侧3，例如使用胶粘剂或纳米膏。这样，集成电路封装200可以被配置成，例如使得电流可以在芯片16的后侧18上的低欧姆触点和芯片的前部触点的组之间垂直地流动。此外，芯片16的后侧18上的低欧姆触点可以例如通过金属层45被电连接到在封装模块中形成的一个或多个通路。因此，电流和/或信号传送(signaling)可以按照需要遍及如上面先前所述的集成电路封装200而被分配。
图22示出处于反向安装配置的示例性集成电路封装的剖面图。封装模块220可以根据上面的描述来构造，并且也如参照图21所描述的那样，但并非芯片16的有源侧面对所连接的PCB以及芯片16的后侧18背朝所连接的PCB，封装模块220被反向成使得，芯片16的有源侧背朝所连接的PCB，以及芯片16的后侧面朝所连接的PCB。因此，当被连接到PCB时，产生了从芯片16的后侧18到所连接的PCB的直接连接，并且芯片16的前部触点7通过通路被连接到所连接的PCB。两组连接路径，通过通路所连接的来自芯片16的后侧18和芯片16的前部触点7的直接连接，可以被配置成通过封装连接器49连接的两个布线层。
通过有机焊接保护(OSP)工艺对封装模块220进行处理，并且然后将封装模块220焊接到PCB上，封装连接器49可以被耦合到外部电路，例如PCB。封装连接器49可被采用在所有公开的实施例中以作为焊球12的替代品。此外，所有公开的实施例可被配置成使得，连接芯片16的后侧18的金属层被构造成使得，封装模块能够通过封装连接器49来安装。作为一个实例，封装连接器49可以例如利用参照图16所描述的实施例来采用。在这种配置中，图16将被安装成反向配置，使得芯片16的后侧18能够安装为向下面朝外部电路，例如PCB。焊球12在这种配置中可能不被需要，并且因此可以被去除。
图23-26示出处于反向安装配置的示例性集成电路封装的剖面图的各种另外的实施例。根据图17和22的描述，图23示出连接到封装模块230并集成到封装模块230的堆叠的芯片41。正如上面关于图22所描述的，并非芯片16的有源侧面对所连接的PCB以及芯片16的后侧18背朝所连接的PCB，封装模块230被反向成使得，芯片16的有源侧背朝所连接的PCB，以及芯片16的后侧面朝所连接的PCB。因此，当被连接到PCB时，产生了从芯片16的后侧18到所连接的PCB的直接连接，并且芯片16的前部触点7通过通路被连接到所连接的PCB。两组连接路径，通过通路所连接的来自芯片16的后侧18和芯片16的前部触点7的直接连接，可以被配置成通过封装连接器49连接的两个布线层。
根据上面的实施例，图24示出处于反向安装配置的封装模块240。此外，封装模块240包括热扩散器51，从而在封装模块240的两侧上实现热扩散。也就是，热沉和/或金属箔层26可以在封装模块240的触点侧上提供热扩散，而热扩散器51在封装模块240的另一侧上提供热扩散。热扩散器51可以至少部分地被电隔离。
根据上面的实施例，图25同样示出具有热扩散器51的处于反向安装配置的封装模块250。与图24相比，图25中的热扩散器51通过纳米膏53被附着到封装模块2。类似地，图26示出具有通过热胶粘剂55连接到封装模块2的热扩散器51的、处于反向安装配置的封装模块260。
本领域技术人员将认识到，可以形成上面的示例性实施例的组合。例如，集成电路封装10、40、50、60、70、80、90、100、110、120、130、140、150、160、170和210中的任何一个被配置成如图22-26所示的反向安装配置。作为另一实例，集成电路封装10、40、50、60、70、80、90、100、110、120、130、140、150、160和170中的任何一个可以实施图18-21中所示的工艺流程，特别是，芯片16可以被扩散焊接到金属层45，使得金属层45覆盖芯片16的后侧18的至少一部分。
本发明可以以其他特定形式来体现而不脱离其精神或本质特性。所描述的实施例应当在所有方面都被认为仅仅是说明性的，而不是限制性的。本发明的范围因此由所附权利要求而非由前述描述来指示。处于权利要求的等同物的含义和范围内的所有变化应当被包括在其范围内。

Claims (22)

1.一种集成电路封装方法，包括：
由限定电路互连的连续建立层制造封装模块；
在所述封装模块的顶侧上形成腔；
将芯片的金属化后侧附着到金属层上，所述芯片具有带有至少一个前部触点的前侧；
将所述芯片布置在所述腔中，使得至少一个前部触点被电连接到所述封装模块的电路互连中的至少一个；以及
将附着到所述芯片的所述金属层耦合到所述封装模块的顶侧上。
2.如权利要求1所述的集成电路封装方法，其中，将芯片的金属化后侧附着到金属层上是利用高温工艺完成的。
3.如权利要求1所述的集成电路封装方法，其中，将芯片的金属化后侧附着到金属层上是利用扩散焊接工艺完成的。
4.如权利要求1所述的集成电路封装方法，其中，所述金属层是金属箔层。
5.如权利要求1所述的集成电路封装方法，其中，所述芯片的后侧具有低欧姆触点。
6.如权利要求5所述的集成电路封装方法，其中，电流在所述低欧姆触点和所述芯片的至少一个前部触点之间垂直地流动。
7.如权利要求6所述的集成电路封装方法，其中，所述低欧姆触点被电连接到所述金属层，并且通过其被连接到在所述封装模块中形成的一个或多个通路。
8.如权利要求1所述的集成电路封装方法，其中，所述金属层具有导热特性。
9.如权利要求8所述的集成电路封装方法，还包括将所述金属层附着到热沉。
10.如权利要求1所述的集成电路封装方法，其中，所述芯片还包括直通硅通路。
11.如权利要求1所述的集成电路封装方法，其中，所述金属层通过隔离中间层被耦合到所述芯片的后侧或者所述封装模块的顶侧。
12.一种集成电路封装，包括：
由限定电路互连的连续建立层形成的封装模块；
在所述封装模块的顶侧上形成的腔；
具有前侧并且具有金属化后侧的芯片，所述前侧具有至少一个前部触点；以及
附着到所述芯片的后侧的至少一部分的金属层，其中所述芯片被布置在所述腔中，使得至少一个前部触点被电连接到所述封装模块的电路互连中的至少一个，并且所述金属层覆盖所述封装模块的顶侧的至少一部分。
13.如权利要求12所述的集成电路封装，其中，所述金属层是金属箔层。
14.如权利要求12所述的集成电路封装，其中，所述芯片的后侧具有低欧姆触点。
15.如权利要求14所述的集成电路封装，其中，电流在所述低欧姆触点和所述芯片的至少一个前部触点之间垂直地流动。
16.如权利要求14所述的集成电路封装，其中，所述低欧姆触点被电连接到所述金属层，并且通过其被连接到在所述封装模块中形成的一个或多个通路。
17.如权利要求12所述的集成电路封装，其中，所述金属层具有促进热扩散的导热特性。
18.如权利要求17所述的集成电路封装，其中，所述金属层被附着到热沉。
19.如权利要求12所述的集成电路封装，其中，所述芯片还包括直通硅通路。
20.如权利要求12所述的集成电路封装，其中，所述金属层通过隔离中间层被耦合到所述芯片的后侧或者所述封装模块的顶侧。
21.一种安装好的集成电路封装，包括：
印刷电路板，其能够让集成电路封装安装在其上；以及
在其上安装成反向安装配置的集成电路封装，所述集成电路封装包括：
由限定电路互连的连续建立层形成的封装模块；
在所述封装模块的顶侧上形成的腔；
具有前侧并且具有金属化后侧的芯片，所述前侧具有至少一个前部触点；以及
附着到所述芯片的后侧的至少一部分的金属层，其中所述芯片被布置在所述腔中，使得至少一个前部触点被电连接到所述封装模块的电路互连中的至少一个，并且所述金属层覆盖所述封装模块的顶侧的至少一部分；
其中反向安装配置是其中所述芯片的金属化后侧面朝所述印刷电路板并且所述芯片的前侧背朝所述印刷电路板。
22.一种安装好的集成电路封装，包括：
印刷电路板，其能够让集成电路封装安装在其上；以及
在其上安装成反向安装配置的集成电路封装，所述集成电路封装包括：
由限定电路互连的连续建立层形成的封装模块；
在所述封装模块的顶侧上形成的腔；
具有前侧并且具有后侧的芯片，所述前侧具有至少一个前部触点，所述芯片被布置在所述腔中，使得至少一个前部触点被电连接到所述封装模块的电路互连中的至少一个；以及
耦合到所述芯片的后侧的顶层，其覆盖所述芯片和所述封装模块的顶侧的至少一部分；
其中反向安装配置是其中所述芯片的金属化后侧面朝所述印刷电路板并且所述芯片的前侧背朝所述印刷电路板。
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