CN103151262A - Planar insulated gate bipolar transistor and preparation method thereof - Google Patents
Planar insulated gate bipolar transistor and preparation method thereof Download PDFInfo
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- CN103151262A CN103151262A CN2011104025451A CN201110402545A CN103151262A CN 103151262 A CN103151262 A CN 103151262A CN 2011104025451 A CN2011104025451 A CN 2011104025451A CN 201110402545 A CN201110402545 A CN 201110402545A CN 103151262 A CN103151262 A CN 103151262A
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Abstract
The invention provides a planar insulated gate bipolar transistor (IGBT) and a preparation method of the plane type IGBT, and belongs to the technical field of IGBTs. The preparation method includes the steps: (1) providing a semiconductor substrate; (2) preparing an epitaxial layer on a first face of the semiconductor substrate in an epitaxial growth mode; (3) preparing a grid and an emitter on a second face of the semiconductor substrate, wherein the plane type IGBT is formed by the grid and the emitter; (4) carrying out thinning on the epitaxial layer to form a collector region; and (5) metalizing the collector region to form a collator. The preparation method is low in cost, and the prepared plane type IGBT is good in device performance.
Description
Technical field
The invention belongs to insulated gate bipolar transistor (Insulated Gate Bipolar Transistor, IGBT) technical field, the plane IGBT that relates to the preparation method of plane IGBT and adopt the prepared formation of this preparation method relates in particular to that positive technique is completed in the front of Semiconductor substrate substantially and plane IGBT preparation method that back process is completed in the epitaxial loayer of Semiconductor substrate back side growth.
Background technology
IGBT is a kind of common power-type device, and it is one of high-current switch main flow device, is widely used in the high-voltage great-current situation, for example, is applied to operating voltage in the situation that 1200V.
In IGBT, according to the structure type of grid, IGBT can be divided into plane IGBT and groove-shaped IGBT, and architectural feature both and individual features thereof are known to those skilled in the art to be known.But, these two kinds of IGBT are in the process of preparation, include positive technique and back process, wherein, positive technique is mainly used to complete the preparation of grid (Gate, G) and the emitter (Emitter, E) of IGBT, back process is mainly used to complete the preparation of the collector electrode (Collector, C) of IGBT.
Normally, existing plane IGBT mainly forms by following two kinds of methods preparation.
The first is, completes positive technique on monocrystalline substrate, then to substrate back attenuate, the back side repeatedly Implantation to draw the formation collector electrode; This method does not rely on epitaxy technique, and energetic ion injects and annealing activation technology process but depend on, and the equipment cost that energetic ion injects is high, technical process realizes that cost is also higher; And the activity ratio of the doped source of the collector area that Implantation and annealing form is not high, and then causes the saturation characteristic of IGBT not good.
The second is, the thicker epitaxial loayer of transoid epitaxial growth on monocrystalline substrate, and complete positive technique on this epitaxial loayer, then at its back side to the silicon substrate attenuate and form collector electrode; This method forms by epitaxial loayer more than adopting epitaxy technique and mainly preparing the IGBT(resilient coating with epitaxial loayer), epitaxial loayer is thicker and to the performance requirement very high (for example defective number) of epitaxial loayer, usually cause IGBT degradation (for example, overvoltage ability to bear and overcurrent ability to bear are poor) or rate of finished products low because the quality of epitaxial loayer is good not.
In view of this, for improving the performance of plane IGBT, be necessary to propose a kind of new preparation method for plane IGBT.
Summary of the invention
One of purpose of the present invention is, improves the performance of plane IGBT.
Another purpose of the present invention is, reduces the preparation cost of plane IGBT.
For realizing above purpose or other purpose, the invention provides following technical scheme.
According to an aspect of of the present present invention, the preparation method of a kind of plane IGBT is provided, it is characterized in that, comprise the following steps:
Semiconductor substrate is provided;
Epitaxial growth epitaxial loayer on the first surface of described Semiconductor substrate;
Preparation forms grid and the emitter of described plane IGBT on second of described Semiconductor substrate;
Described epitaxial loayer is carried out attenuate to form collector region; And
Metallization is to form collector electrode on described collector region.
According to the preparation method of one embodiment of the present invention, wherein, described plane IGBT is plane type field cut-off IGBT; And
In described epitaxial growth steps, comprising:
Epitaxial growth is used to form the first epitaxial loayer of resilient coating on the first surface of described Semiconductor substrate; And
Epitaxial growth is used to form the second epitaxial loayer of collector region on described the first epitaxial loayer.
In the preparation method of described embodiment before, preferably, in described epitaxial loayer is carried out the step of attenuate, described the second epitaxial loayer is carried out attenuate.
In the preparation method of described embodiment before, preferably, described Semiconductor substrate is the N-type doping, and described the first epitaxial loayer is the N-type doping, and described the second epitaxial loayer is the doping of P type.
In the preparation method of described embodiment before, preferably, the doping content scope of described Semiconductor substrate is 1 * 10
9Ion/cm
3To 1 * 10
15Ion/cm
3
In the preparation method of described embodiment before, preferably, the doping content scope of described the first epitaxial loayer is 1 * 10
14Ion/cm
3To 1 * 10
22Ion/cm
3, the thickness range of described the first epitaxial loayer is 0.0001 micron to 100 microns.
In the preparation method of described embodiment before, preferably, the doping content scope of described the second epitaxial loayer is 1 * 10
14Ion/cm
3To 1 * 10
23Ion/cm
3, the thickness range of described the second epitaxial loayer is 1 micron to 600 microns.
In the preparation method of described embodiment before, preferably, described epitaxially grown temperature range is 1100 ℃ to 1240 ℃.
In the preparation method of described embodiment before, preferably, described current collection is the lamination layer structure of Al/Ti/Ni/Ag very; It is perhaps the lamination layer structure of Ti/Ni/Ag; It is perhaps the lamination layer structure of Al/V/Ni/Ag.
In the preparation method of described embodiment before, preferably, before epitaxial growth epitaxial loayer step, the first surface of described Semiconductor substrate is carried out polishing.
According to another aspect of the present invention, a kind of plane IGBT is provided, it forms by any method preparation that the above reaches.
Technique effect of the present invention is, adopt epitaxially grown way to form collector region at the back side of Semiconductor substrate, the process of having avoided in the traditional handicraft repeatedly energetic ion to inject, and relative cost is low and do not allow to be subject to the restriction of energetic ion injection device; And the positive technique of plane IGBT is to complete in Semiconductor substrate, and the quality of Semiconductor substrate is better than the quality of epitaxially grown semiconductor layer, therefore, can greatly improve the device performance (for example, the saturation characteristic of plane IGBT) of plane IGBT; The semiconductor layer of extension is mainly used to form collector region, and its quality requirement is lower, has also reduced requirement and the cost of epitaxy technique.Therefore, use the device performance of the plane IGBT that preparation method's cost of the present invention is low, preparation forms good.
Description of drawings
From following detailed description by reference to the accompanying drawings, will make above and other objects of the present invention and advantage more fully clear, wherein, same or analogous key element adopts identical label to represent.
Fig. 1 is the schematic flow sheet according to the plane IGBT preparation method of one embodiment of the invention.
Fig. 2 to Fig. 7 is the structural change schematic diagram when preparing plane IGBT according to method flow shown in Figure 1.
Embodiment
The below introduces is a plurality of some in may embodiment of the present invention, aims to provide basic understanding of the present invention, is not intended to confirm key of the present invention or conclusive key element or limits claimed scope.Easily understand, according to technical scheme of the present invention, do not changing under connotation of the present invention other implementation that one of ordinary skill in the art can propose mutually to replace.Therefore, following embodiment and accompanying drawing are only the exemplary illustrations to technical scheme of the present invention, and should not be considered as of the present invention all or be considered as restriction or restriction to technical solution of the present invention.
In the accompanying drawings, for the sake of clarity, exaggerated the thickness in layer and zone, and the mellow and full shape facility that waits that causes due to etching does not illustrate in the accompanying drawings.
Herein, the directional terminology such as " back side ", " front ", "up" and "down" are that the z coordinate direction with respect to the definition in accompanying drawing defines, with respect to the IGBT device cell, the direction of emitter, the relative collector electrode of grid is defined as the positive direction of z coordinate, and the z coordinate is simultaneously perpendicular to the substrate surface for the preparation of this IGBT.And, be to be understood that, these directional terminology are relative concepts, they be used for respect to description and clarification, the variation in the orientation that it can be placed according to the IGBT device cell and correspondingly changing.In addition, the direction on the raceway groove in the cross section of IGBT device cell is defined as the x coordinate direction, is also horizontal direction.
Figure 1 shows that the schematic flow sheet according to the plane IGBT preparation method of one embodiment of the invention; Fig. 2 is to the structural change schematic diagram that Figure 7 shows that when preparing plane IGBT according to method flow shown in Figure 1.Describe this preparation method embodiment in detail in conjunction with Fig. 1 to Fig. 7.
At first, step 110 provides the N-monocrystalline substrate.
As shown in Figure 2, the crystal orientation of N-monocrystalline substrate 300 is preferably＜and 100 〉, its doping content is 1 * 10
9Ion/cm
3To 1 * 10
15Ion/cm
3Set in scope, for example, its doping content can be 6 * 10
14Ion/cm
3The two sides of N-monocrystalline substrate 300 is front 302 and the back side 301, and it is used for respectively completing positive technique and the back process of plane IGBT.
Further, step S120 is at the back side of N-monocrystalline substrate epitaxial growth N+ epitaxial loayer.
As shown in Figure 3, adopt epitaxy technique, at the back side of N-monocrystalline substrate 300 301 growth one deck N+ epitaxial loayers 310, be doping of the same type between N+ epitaxial loayer 310 and N-monocrystalline substrate 300, therefore, it is the epitaxial growth of homotype (identical conduction type, be identical doping type), and with respect to the epitaxial growth of transoid, the doping content of N+ epitaxial loayer 310 etc. are easily controlled.Preferably, the doping content of N+ epitaxial loayer 310 is 1 * 10
14Ion/cm
3To 1 * 10
22Ion/cm
3Set (for example, 5 * 10 in scope
18Ion/cm
3), its thickness range is 0.0001 micron to 100 microns (for example 5 microns); During epitaxial growth N+ epitaxial loayer 310, the temperature range of the epitaxial furnace growth in process conditions is 1100 ℃ to 1240 ℃.
N+ epitaxial loayer 310 finally can be used for forming the resilient coating (Buffer Layer) of plane IGBT.Preferably, in this step 120, before epitaxial growth, comprise the step of the back side of N-monocrystalline substrate 300 being carried out single-sided polishing, accurately to carry out epitaxial growth.
Further, step S130, epitaxial growth P+ epitaxial loayer on the N+ epitaxial loayer.
As shown in Figure 4, adopt epitaxy technique, continue transoid growth formation P+ epitaxial loayer 320a on N+ epitaxial loayer 310.Preferably, the doping content of P+ epitaxial loayer 320a is 1 * 10
14Ion/cm
3To 1 * 10
23Ion/cm
3Set (for example, 7 * 10 in scope
19Ion/cm
3), its thickness range is 1 micron to 600 microns (for example, 20 microns); During epitaxial growth P+ epitaxial loayer 320a, its concrete technology condition is epitaxial furnace growth in the temperature range of 1100 ℃ to 1240 ℃.
Because this P+ epitaxial loayer 320a forms collector electrode (C), the performance impact less of the quality of this epitaxial loayer (such as defective number etc.) to plane IGBT, and, most P+ epitaxial loayer 320a is needing attenuate to remove in step thereafter, therefore, the P+ epitaxial loayer 320a that this epitaxial step growth is formed is also low with respect to the quality requirement of the epitaxial loayer of the second method in background technology, also is conducive to reduce costs.
Further, step S140 completes positive technique and forms grid and the emitter of IGBT with preparation in the front of N-monocrystalline substrate.
As shown in Figure 5, form N-drift (Drift) district of plane IGBT with N-monocrystalline substrate 300, in N-monocrystalline substrate 300 composition doping formation P+ tagmas, front 351, further the composition doping forms N+ emitter region 352 on P+ tagma 351, in this example, two N+ emitter regions 352 are connected in an emitter 355 jointly, and emitter 355 forms by metallization process.Gate dielectric layer 353 and grid 354 are formed on 351 surfaces, P+ tagma, and gate dielectric layer 353 and grid 354 roughly in same " plane " upper distribution or with respect to P+ tagma 351 flatly distributions, therefore, are called plane IGBT.From forming P+ tagma 351 in the front of N-monocrystalline substrate to forming grid 354 and emitter 355, be referred to as positive technique, by positive technique, the main body of plane IGBT basically forms.
It will be appreciated that, the concrete front processing step of plane IGBT or positive technical process the concrete structure that forms not limited by illustrated embodiment of the present invention, it can adopt in prior art and disclose or any positive technique of announcement and the structure of formation thereof, even can adopt improved positive technique or its formed structure in the future.
Further, step S150 implements reduction process to the P+ epitaxial loayer.
As shown in Figure 6, such as reduction process such as can adopting polishing, attenuate is carried out to form P+ collector region 320 in the back side of P+ epitaxial loayer 320a.The doping content of P+ collector region 320 is equally 1 * 10
14Ion/cm
3To 1 * 10
23Ion/cm
3Set (for example, 7 * 10 in scope
19Ion/cm
3), its thickness range is 1 micron to 100 microns (for example, 5 microns).Therefore, most P+ epitaxial loayer 320a is thinned removal in this embodiment.
Further, step S160, back face metalization is to form collector electrode.
As shown in Figure 7, depositing metal layers also metallizes to form collector electrode 330 on the surface of P+ collector region 320.In a preferred embodiment, collector electrode 330 is the lamination layer structure of Al/Ti/Ni/Ag, and Al, Ti, Ni, Ag from top to bottom arrange successively (not shown) is set; In another preferred embodiment, collector electrode 330 is the lamination layer structure of Ti/Ni/Ag, and Ti, Ni, Ag from top to bottom arrange successively (not shown) is set; In an embodiment also, collector electrode 330 is the Al/V(vanadium)/lamination layer structure of Ni/Ag, Al, V, Ni, Ag from top to bottom arrange successively (not shown) are set.
So far, preparation method's process embodiment illustrated in fig. 1 finishes substantially, thereby preparation has formed the plane IGBT of embodiment as shown in Figure 7.As shown in Figure 7, need to prove, the unit cellular of a plurality of plane IGBT is shared collector electrode 330 in parallel jointly, and resistance is less.
In plane IGBT embodiment illustrated in fig. 7, adopt twice epitaxially grown way to form N-resilient coating and collector region, the process of having avoided in the traditional handicraft repeatedly energetic ion to inject, relative cost is low and do not allow to be subject to the restriction of energetic ion injection device; Especially, the positive technique of plane IGBT is to complete in the Semiconductor substrate as an example of monocrystalline silicon example, and the quality of Semiconductor substrate is better than the quality of epitaxially grown semiconductor layer, therefore, can greatly improve the device performance (for example, the saturation characteristic of plane IGBT) of plane IGBT; And the semiconductor layer of extension is mainly used to form collector region, and its quality requirement is relatively low, has also reduced requirement and the cost of epitaxy technique.
The plane IGBT of the described embodiment of Fig. 7, plane type field cut-off (Field Stop) IGBT, N+ epitaxial loayer 310 is higher with respect to the doping content of the N-drift layer that substrate forms, and according to Poisson's equation, electric field strength is stopped rapidly in this N+ epitaxial loayer 310.Need to understand is that preparation method of the present invention can also be applied to the preparation of the plane IGBT of other embodiment, for example, does not comprise the IGBT of non-cut-off type of N+ epitaxial loayer 310.
Above example has mainly illustrated the preparation method of plane IGBT of the present invention and has used this preparation method formed.Although only the some of them embodiments of the present invention are described, those of ordinary skills should understand, and the present invention can be within not departing from its purport and scope implements with many other forms.Therefore, the example of showing and execution mode are regarded as illustrative and not restrictive, in the situation that do not break away from spirit of the present invention as defined in appended each claim and scope, the present invention may be contained various modifications and replacement.
Claims (11)
1. the preparation method of a plane insulated gate bipolar transistor, is characterized in that, comprises the following steps:
Semiconductor substrate is provided;
Epitaxial growth epitaxial loayer on the first surface of described Semiconductor substrate;
Preparation forms grid and the emitter of described plane insulated gate bipolar transistor on second of described Semiconductor substrate;
Described epitaxial loayer is carried out attenuate to form collector region; And
Metallization is to form collector electrode on described collector region.
2. preparation method as claimed in claim 1, is characterized in that, described plane insulated gate bipolar transistor is plane type field cut-off insulated gate bipolar transistor; And
In described epitaxial growth steps, comprising:
Epitaxial growth is used to form the first epitaxial loayer of resilient coating on the first surface of described Semiconductor substrate; And
Epitaxial growth is used to form the second epitaxial loayer of collector region on described the first epitaxial loayer.
3. preparation method as claimed in claim 2, is characterized in that, in described epitaxial loayer is carried out the step of attenuate, described the second epitaxial loayer carried out attenuate.
4. preparation method as claimed in claim 2, is characterized in that, described Semiconductor substrate is the N-type doping, and described the first epitaxial loayer is the N-type doping, and described the second epitaxial loayer is the doping of P type.
5. preparation method as claimed in claim 4, is characterized in that, the doping content scope of described Semiconductor substrate is 1 * 10
9Ion/cm
3To 1 * 10
15Ion/cm
3
6. preparation method as claimed in claim 4, is characterized in that, the doping content scope of described the first epitaxial loayer is 1 * 10
14Ion/cm
3To 1 * 10
22Ion/cm
3, the thickness range of described the first epitaxial loayer is 0.0001 micron to 100 microns.
7. preparation method as claimed in claim 4, is characterized in that, the doping content scope of described the second epitaxial loayer is 1 * 10
14Ion/cm
3To 1 * 10
23Ion/cm
3, the thickness range of described the second epitaxial loayer is 1 micron to 600 microns.
8. preparation method as claimed in claim 1, is characterized in that, described epitaxially grown temperature range is 1100 ℃ to 1240 ℃.
9. preparation method as claimed in claim 1, is characterized in that, described current collection is the lamination layer structure of Al/Ti/Ni/Ag very; It is perhaps the lamination layer structure of Ti/Ni/Ag; It is perhaps the lamination layer structure of Al/V/Ni/Ag.
10. preparation method as claimed in claim 1, is characterized in that, before epitaxial growth epitaxial loayer step, the first surface of described Semiconductor substrate carried out polishing.
11. plane insulated gate bipolar transistor that forms according to the preparation of method as described in any one in claim 1 to 10.
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Cited By (3)
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| CN104992969A (en) * | 2015-07-14 | 2015-10-21 | 株洲南车时代电气股份有限公司 | Semiconductor device having buffer layer and manufacturing method thereof |
| CN105023836A (en) * | 2014-04-25 | 2015-11-04 | 国家电网公司 | Buffer layer manufacture method on back of power member |
| CN114864396A (en) * | 2022-04-13 | 2022-08-05 | 湖南楚微半导体科技有限公司 | Wafer back metallization method and wafer back metallization structure |
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| CN105023836A (en) * | 2014-04-25 | 2015-11-04 | 国家电网公司 | Buffer layer manufacture method on back of power member |
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Application publication date: 20130612 |