CN103137682A - 具有改进击穿电压性能的高电子迁移率晶体管结构 - Google Patents
具有改进击穿电压性能的高电子迁移率晶体管结构 Download PDFInfo
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- CN103137682A CN103137682A CN2012104849174A CN201210484917A CN103137682A CN 103137682 A CN103137682 A CN 103137682A CN 2012104849174 A CN2012104849174 A CN 2012104849174A CN 201210484917 A CN201210484917 A CN 201210484917A CN 103137682 A CN103137682 A CN 103137682A
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Abstract
一种高电子迁移率晶体管(HEMT)包括硅衬底、位于硅衬底上方的非故意掺杂的氮化镓(UID GaN)层。该HEMT进一步包括位于UID GaN层上方的施主供应层、位于施主供应层上方的栅极结构、漏极和源极。该HEMT进一步包括位于施主供应层上方的栅极结构和漏极之间的具有位于施主供应层中的一个或多个电介质插塞部和顶部的介电层。本发明还提供一种用于制造HEMT的方法。本发明还提供了具有改进击穿电压性能的高电子迁移率晶体管结构。
Description
相关申请交叉参考
本申请要求于2011年11月29日提交的第61/564,650号美国临时专利申请的优先权,其全部内容结合于此作为参考。
技术领域
该公开通常涉及半导体电路制造工艺,更具体地说,涉及基于III族和V族(III-V)化合物半导体的晶体管。
背景技术
由于III族-V族化合物半导体(也称为III-V化合物半导体)(诸如,氮化镓(GaN)及其相关合金)在电力电子器件和光电子器件中具有发展前景的应用,最近几年它们是研究热点。许多III-V化合物半导体的大带隙和高电子饱和速度也使得它们在高温、高电、和高速度电力电子的应用中成为极好的选择。使用III-V化合物半导体的可能的电子器件的特别实例包括高电子迁移率晶体管(HEMT)和其他异质结双极晶体管。
在操作期间,HEMT在栅极边缘周围形成大表面电场,从而影响位于栅极结构和漏极之间的漂移区中的耗尽区曲线。尽管大电场是HEMT用于电力应用中的一个优势,但是,操作期间耗尽区的分布对用于HEMT的击穿电压产生负面影响。当对HEMT的栅极施加负偏压时,耗尽区曲线直接形成在栅极下方并且引起围绕栅极边缘的大表面电场集中。栅极周围的电场集中降低了击穿电压。
为了提高击穿电压,有时在位于栅极结构和漏极之间的钝化层上方或者紧接钝化层上方的栅极结构添加金属场极板。场极板调节表面电场分布并且增强击穿电压。然而,人们继续探索具有用于基于III-V化合物半导体的晶体管的高击穿电压的新结构及其形成方法。
发明内容
为了解决现有技术中所存在的缺陷,根据本发明的一方面,提供了一种高电子迁移率晶体管(HEMT),包括:硅衬底;非故意掺杂氮化镓(UIDGaN)层,位于所述衬底上方;施主供应层,位于所述UID GaN层上方;栅极结构、漏极和源极,位于所述施主供应层上方,所述栅极结构设置在所述漏极和所述源极之间;以及介电层,在所述栅极结构和所述漏极之间位于所述施主供应层上方,所述介电层具有位于所述施主供应层中的一个或多个第一部分以及位于所述一个或多个第一部分和所述施主供应层上方的第二部分;其中,所述一个或多个第一部分中的至少一个紧邻所述栅极。
在该HEMT中,所述介电层包括氧化锌、氧化锆、氧化铪或氧化钛。
在该HEMT中,所述介电层包括氧化硅、氮化硅、氮氧化硅、掺碳氧化硅、掺碳氮化硅或掺碳氮氧化硅。
在该HEMT中,所述施主供应层位于所述介电层的所述一个或多个第一部分下方的部分的厚度为至少15纳米。
在该HEMT中,所述施主供应层位于所述介电层的所述一个或多个第一部分下方的部分的厚度至少为所述施主供应层直接位于所述介电层的所述第二部分下方的部分的厚度的40%。
在该HEMT中,所述介电层的所述一个或多个第一部分是一个第一部分,并且所述第一部分的面积为所述施主供应层的漂移区的面积的约5%至约20%。
在该HEMT中,所述一个或多个第一部分中的所述至少一个邻近栅极边缘。
在该HEMT中,从上往下看时,所述介电层的所述一个或多个第一部分为四边形。
在该HEMT中,所述介电层的所述一个或多个第一部分和所述施主供应层围绕所述介电层的所述一个或多个第一部分的部分形成棋盘图案。
在该HEMT中,所述介电层的所述一个或多个第一部分覆盖所述施主供应层在所述栅极结构和所述漏极之间的部分的约40%至约75%。
在该HEMT中,所述介电层的所述一个或多个第一部分中的最大一个最接近所述栅极。
在该HEMT中,所述施主供应层包括非掺杂氮化铝或非掺杂氮化铝镓。
在该HEMT中,所述介电层的所述一个或多个第一部分的厚度为约3纳米至约10纳米。
根据本发明的另一方面,提供了一种方法,包括:提供硅衬底;在所述硅衬底上方外延生长氮化镓(GaN)层;在所述GaN层上方外延生长施主供应层;在所述施主供应层上形成源极和漏极;在所述施主供应层上形成位于所述源极和所述漏极之间的栅极结构;将所述施主供应层的漂移区的一部分等离子体蚀刻到小于施主供应层厚度的60%的深度;以及在所述施主供应层上方沉积介电层。
在该方法中,所述GaN层包括非故意掺杂氮化镓,所述施主供应层包括AlxGa(1-X)N,其中,x介于0.1和1之间。
在该方法中,在所述施主供应层上形成源极和漏极包括:在所述施主供应层上方沉积多个金属层;覆盖所述施主供应层的源极区和漏极区;将所述多个金属层蚀刻为源极和漏极;去除所述源极和所述漏极上方的覆盖物;以及对所述源极和所述漏极进行退火。
在该方法中,在所述施主供应层的露出部分上方沉积介电层包括:在所述硅衬底上方沉积介电层;图案化光刻胶以暴露所述栅极结构、所述源极和所述漏极;以及去除所述栅极结构、所述源极和所述漏极上方的所述介电层。
在该方法中,所述介电层是选自由氧化锌、氧化锆、氧化铪、氧化钛、氧化硅、氮化硅、氮氧化硅、掺碳氧化硅、掺碳氮化硅以及掺碳氮氧化硅所组成的组中的一层或多层。
在该方法中,所述等离子体蚀刻包括将所述衬底暴露于氯基等离子体蚀刻剂。
在该方法中,以约每分钟1纳米的速率进行所述等离子体蚀刻。
附图说明
为了更完整的理解本发明及其优点,结合附图所进行的以下描述作为参考,其中:
图1A是根据本发明的多个实施例的高电子迁移率晶体管(HEMT)结构的截面图;
图1B是图1A的HEMT的一部分的放大图;
图2A至图2D是根据本发明的多个实施例的从图1A的观察面110观看的图1A的HEMT结构的一部分的俯视图;
图3A至图3C是根据本发明的某些实施例的用于形成HEMT结构的方法的流程图;
图4A至图4E是根据本发明的多个方法实施例处于多个形成阶段中的HEMT的截面图;以及
图5是根据本发明的多个实施例模拟的峰值表面电场作为HEMT结构上的位置函数的曲线图。
具体实施方式
下面,详细讨论本发明的实施例的制造和使用。然而,应该理解,本发明提供了许多可以在各种具体环境中实现的可应用的创造性概念。所讨论的具体实施例仅仅示出了制造和使用本发明的具体方式,而不用于限制本发明的范围。
本发明提供了用于基于III族V族(以下称为III-V)半导体的晶体管的新结构以及用于形成该结构的方法。在通篇描述中,术语“III-V化合物半导体”指的是包括至少一个III族元素和一个V族元素的化合物半导体材料。术语“III-N化合物半导体”指的是V族元素为氮的III-V化合物半导体。公开了制造本发明的示例性实施例的示例性阶段。本领域技术人员应该认识到,也可以在所描述的阶段之前或之后,进行其他制造步骤。可以讨论能够替换一些示例性阶段的其他制造阶段。本领域技术人员会认识到,可以使用其他替换阶段或步骤。在本发明的各个附图和所有的示例性实施例中,相同的参考标号用于指定相同的元件。
本发明提供了用于形成具有高击穿电压的基于III-V化合物半导体的晶体管的结构和方法。图1A示出了根据本发明多个实施例的功率晶体管器件100的实例。图1B示出了图1A的功率晶体管器件100的一部分的放大图。功率晶体管100可以是高电子迁移率晶体管(HEMT)。
HEMT 100形成在硅衬底101上方。使用外延工艺在硅衬底101上方生长许多层。这些层包括氮化铝层的可选成核层(未示出)、可选缓冲层(未示出)、以及可以在缓冲层上方生长的块状氮化镓层109。块状氮化镓(GaN)层109是用于HEMT 100的沟道层。
HEMT 100包括位于块状GaN层109顶部的有源层111。在沟道层109上生长有源层111,也称为施主供应层(donor-supply layer)。在沟道层109和施主供应层111之间限定界面。二维电子气(2-DEG)的载流子沟道113位于该界面处。在至少一个实施例中,施主供应层111是氮化铝镓(AlGaN)层。该AlGaN层具有公式AlxGa(1-x)N,其中,x在约0.1和1.0之间变化。该AlGaN层的厚度在约5纳米至约50纳米的范围内。在其他实施例中,施主供应层111可以包括AlGaAs层或AlInP层。
在AlGaN层111和GaN层109之间存在带隙不连续性。由于压电效应产生的AlGaN层111中电子落入GaN层109,从而在GaN层109中产生高迁移率导电电子的薄层113。该薄层113被称为二维电子气(2-DEG),从而形成载流子沟道(也称为载流子沟道113)。该2-DEG的薄层113位于AlGaN层111和GaN层109的界面处。因此,由于GaN层109未掺杂或未故意掺杂,所以载流子沟道具有高电子迁移率,并且电子可以自由移动而不与杂质碰撞或大幅减少了与杂质的碰撞。
源极部件115和漏极部件117设置在AlGaN层111上,并且被配置成与载流子沟道113电连接。源极部件115和漏极部件117中的每一个均包括相应的金属间化合物。该金属间化合物可以内嵌在AlGaN层111中并且可以进一步内嵌在GaN层109的顶部。在一个实例中,金属间化合物包括Al、Ti或Cu。在另一个实例中,金属间化合物包括AlN、TiN、Al3Ti或AlTi1N。
HEMT 100还包括在源极部件115和漏极部件117之间设置在AlGaN层111上的栅极结构119。栅极结构119包括导电材料层,导电材料层用作被设置为用于电压偏置并与载流子沟道113电耦合的栅电极。在多个实例中,导电材料层可以包括难熔金属或其化合物,例如,钨(W)、氮化钛(TiN)和钽(Ta)。导电材料层中其他通常使用的金属包括镍(Ni)和金(Au)。栅极结构可以包括一层或多层。
根据本发明的多个实施例,介电层104在栅极结构119和漏极117之间覆盖施主供应层111的漂移区107。介电层104包括电介质插塞部和位于电介质插塞部上方的顶部。图1B示出了靠近栅极结构119的漂移区107中的HEMT 100的一部分的放大图。介电层104包括第一部103(也称为电介质插塞部103)和第二部105(也称为顶部105)。电介质插塞部103内嵌在施主供应层111中并且具有高度123。电介质插塞部103下方的施主供应层111具有厚度125,该厚度小于块状施主供应层的厚度121。介电层104的顶部105具有相对恒定的厚度。
虽然图1B示出了一个电介质插塞103,但是介电层104可以包括一个或多个电介质插塞103。电介质插塞103的高度123可以为约3nm至约10nm。在一些情况下,电介质插塞103的高度可以取决于施主供应层111的厚度121。在一些实施例中,电介质插塞103下方的施主供应层厚度125为施主供应层111其他部分的厚度121的至少40%。在其他实施例中,施主供应层厚度125至少为约15纳米。因此,如果块状施主供应层厚度121为25纳米,则通过首先保证电介质插塞下方的施主供应层厚度125为至少15纳米,电介质插塞高度123可以小于约10纳米。在另一个实例中,如果块状施主供应层厚度121为50纳米,则电介质插塞厚度123可以达到约30纳米,或者达到块状施主供应层厚度的约60%。通常,电介质插塞103下方的施主供应层111具有足够的厚度来避免操作期间影响载流子沟道113导电能力。然而,电介质插塞的电介质插塞高度123应该足以影响栅极结构119周围的表面电场。
在其他实例中,电介质插塞高度123取决于HEMT 100的电气性质和外形尺寸。例如,当块状氮化镓层109厚并且漂移区107比栅极结构119和源极115之间的区域大得多时,可以使用短电介质插塞103,例如,小于块状施主供应层厚度的40%。在这些情况中,击穿电压必然高,并且对表面电场较小的调节可能就足够了。另一方面,在块状氮化镓层109薄时或者体块层(bulk layer)的材料具有低Ec值时,电介质插塞103较高,例如,达到块状施主供应层厚度的约60%。操作期间,当漏极经受高电压时,所形成的耗尽区可以延伸越过薄的氮化镓层109并且与下面的衬底相互作用。当栅极结构119和漏极117之间(漂移区107)的距离小时,采用相似的原理。操作期间,当漏极经受高电压时,耗尽区曲线可以延伸越过短漂移区107。因此,可以使用较高的电介质插塞103来有效地调节表面电场。
在图1B中,示出了位于与栅极结构119相距距离127处的电介质插塞103。该距离127可以介于0到几微米之间,并且在一些实施例中可以是负值。在某些实施例中,电介质插塞邻接栅极结构边缘。在另一些实施例中,电介质插塞甚至可以略微位于栅极结构边缘下方。距离127不大于电介质插塞103的宽度以提供调节栅极结构边缘处的表面电场的良好有效性。
在具有在其中蚀刻的凹腔的施主供应层111上方沉积介电层104。可以在形成源极、漏极和栅极结构之前或之后进行蚀刻。然而,通常在形成栅极结构之后沉积介电层104,从而避免去除用于栅极结构119的一部分介电层104的额外步骤。介电层104可以是二氧化硅、氮化硅、氮氧化硅、掺碳二氧化硅、掺碳氮化硅、掺碳氮氧化硅、氧化锌、氧化锆、二氧化铪或氧化钛。使用诸如化学汽相沉积(CVD)的已知工艺来沉积介电层。
图2A至图2D是根据本发明多个实施例的多个电介质插塞的俯视图。沿着线110截取图1A的HEMT 100的俯视图。线110将介电层104分成顶部105和电介质插塞103。
图2A示出漂移区207中的全部的四个电介质插塞203。如图2A所示,四个电介质插塞203分散在栅极结构219和漏极217之间,但是可以使用更少或更多的电介质插塞。每个电介质插塞203均具有宽度。在图2A中,紧接栅极结构219的电介质插塞203具有最大宽度。其他电介质插塞203具有相同的宽度。
根据某些实施例,最宽的电介质插塞203最靠近栅极结构119。虽然本发明不需要降低晶体管100的击穿电压,但是具有最靠近栅极结构119的较宽的电介质插塞导致较大地降低击穿电压。
在一些实施例中,电介质插塞203具有相同的宽度,并且等间距间隔开。在使用多个电介质插塞的实例中,电介质插塞的宽度和没有被任何电介质插塞占据的并且紧邻电介质插塞的漂移区207的宽度的比率可以介于约3∶1到约1∶3之间,例如,图2A中的宽度225与宽度227的比率。在另一些实施例中,全部电介质宽度的总和可以为整个漂移区207宽度的约40%至约75%。
图2A中,部件均具有相同的长度,使得宽度决定面积。然而,电介质插塞不必具有相同的长度、形状或尺寸。整个电介质插塞的面积可以为整个漂移区207面积的约40%至约75%。
图2B示出了棋盘图案的电介质插塞203。该设计可以通过贯穿漂移区207配置电介质插塞203来使表面电场平稳(smooth)。电介质插塞面积与没有被电介质插塞203占据的漂移区207的相邻面积的比率介于约3∶1到约1∶3之间。如图2B所示,该比率为约1∶1。在一些实施例中,电介质插塞203的尺寸不相同。
图2C示出梯形的电介质插塞203。梯形的电介质插塞203具有较短宽度和较长宽度。图2D示出仅具有一个电介质插塞203的俯视图。在仅使用一个电介质插塞203的实例中,电介质插塞面积占漂移区总面积的百分比为约5%到约20%。在使用多于一个电介质插塞的其他实施例中,电介质插塞总面积可以为漂移区总面积的约40%至约75%。
图2A至图2D中所示的多个电介质插塞仅为实例。电介质插塞可以是诸如图2A至图2D所示的四边形的多边形。电介质插塞的截面可以多于四条边或者电介质插塞可以是圆形的或不规则的。
图3A至图3C为示出形成本发明的HEMT的方法的多个操作的工艺流程图。结合图4A至图4E来描述图3A至图3C,其中,图4A至图4E示出了处于多个制造阶段中的部分制造的HEMT。图3A示出了工艺流程300,该工艺流程描述了根据本发明多个实施例的制造HEMT的操作。在第一操作301中,提供了硅衬底。图4A至图4E示出了硅衬底401。注意,图中的各个元件没有按比例绘制。虽然通常在不同于硅衬底的衬底(诸如,蓝宝石和碳化硅)上制造HEMT,但是,本文中所公开的方法和结构是特定的硅制造工艺和基于硅的结构。
参照图3A,在操作303中,在硅衬底上方外延生长未掺杂的氮化镓(u-GaN)的体块层。在图4A至图4E中示出了该u-GaN层作为硅衬底401上方的层409。在硅衬底401上方外延生长未掺杂的氮化镓的体块层409,其可以包括诸如成核层和/或缓冲层的插入层。氮化镓的体块层409不包括任何掺杂物,但是可以包括无意中包含在薄膜中的污染物或杂质。氮化镓的体块层可以称为非故意掺杂的氮化镓(UID GaN)层。UID氮化镓的厚度可以约为0.5微米至约1微米。该UID GaN层在高温条件下生长。该工艺可以是金属有机CVD(MOCVD)、金属有机物汽相外延(MOVPE)、等离子体增强CVD(PECVD)、远程等离子体增强CVD(RP-CVD)、分子束外延(MBE)、氢化物汽相外延(HVPE)、氯化物汽相外延(C1-VPE)以及液相外延(LPE)。金属有机物汽相外延(MOVPE)使用含镓前体和含氮前体。含镓前体包括三甲基镓(TMG)、三乙基镓(TEG)或其他合适的化学物质。含氮前体包括氨(NH3)、三甲基铝(TMA)、苯肼或其他合适的化学物质。
参照图3A,在操作305中,在UID GaN层上方生长施主供应层。在图4A到4E中示出了施主供应层作为UID GaN层409上方的层411。可以通过使用含铝前体、含镓前体和含氮前体的MOVPE在GaN层409上外延生长施主供应层411。含铝前体包括TMA、TEA(三乙基铝)或其他合适的化学物质。含镓前体包括TMG、TEG或其他合适的化学物质。含氮前体包括氨、叔丁胺(tertiarybutylamine,TBAm)、苯肼或其他合适的化学物质。
施主供应层411和UID GaN层409之间带隙的不连续性在两层411和409之间的界面处形成载流子沟道413。载流子沟道413也称为二维电子气(2-DEG),其中,当晶体管导通时,电子具有高迁移率。
参照图3A,在操作307中,在施主供应层上形成源极和漏极。图4B示出施主供应层411上的源极415和漏极417。在一些实施例中,源极415和漏极417是金属间化合物或者合金。可以通过在施主供应层411上方或者完全或部分地在施主供应层411的空腔中构建图案化金属层来形成金属间化合物。然后,可以对图案化金属层进行退火,使得金属层、施主供应层411以及任选的GaN层409发生反应以形成金属间化合物。由于退火,金属间化合物中的金属元素可以扩散到施主供应层411和GaN层409中。金属间化合物与位于施主供应层411和GaN层409的界面处的载流子沟道413相接触。金属间化合物可以改善电连接并且在源极/漏极部件和载流子沟道413之间形成欧姆接触件。在一个实例中,金属间化合物形成在施主供应层411的空腔中以及围绕空腔的一部分施主供应层中,使得金属间化合物跟踪施主供应层411的轮廓并且具有不平坦顶面。在另一个实例中,金属间化合物覆盖施主供应层411的一部分。
图3B进一步将操作307分成详细的子操作。在操作321中,在施主供应层上方沉积许多金属层,这些金属层可以包括在施主供应层中蚀刻的用于源极和漏极的开口。金属层可以包括钛、铝和铜。在一个实例中,金属层是钛、铝和钛叠层。使用物理汽相沉积(PVD)工艺沉积金属层。在腔室中紧接包含要沉积的金属的靶子(target)形成等离子体。等离子体中的离子轰击靶子,使得金属粒子溅射开。溅射金属粒子沉积在衬底上以形成金属层。金属层与施主供应层的表面拓扑结构一致。
在操作323中,覆盖金属层的源极区和漏极区。在一些实施例中,光刻工艺用于覆盖要保护的金属层。沉积光刻胶并将光刻胶暴露在能改变光刻胶性质的光图案中。根据光刻胶的类型,通过将光刻胶显影来去除被暴露的部分或者未被暴露的部分,在金属层上仅留下光刻胶的一些部分。在随后的处理中,将覆盖物用作掩模。也可以使用诸如图案化硬掩模的其他材料。应该首先沉积硬掩模、对其进行图案化、并对其进行蚀刻以限定源极和漏极。
在操作325中,蚀刻金属层。操作323中的掩模或光刻胶为保护源极和漏极不被去除的蚀刻掩模。使用等离子体的干蚀刻去除未被保护的金属层,向下到达施主供应层。合适的等离子体蚀刻技术包括反应离子蚀刻(RIE)、电感耦合等离子体(ICP)蚀刻。根据位于下层的施主供应层上方的金属蚀刻剂的选择性,可以对金属层进行略微过蚀刻以确保清洁表面。
在操作327中,去除源极和漏极上方的覆盖物。如果覆盖物是光刻胶,则去除工艺为灰化和剥离。如果覆盖物是硬掩模,则去除工艺可以包括用与操作325的不同的等离子体蚀刻剂进行蚀刻。这里,部分制造的结构类以于图4B的结构。此后,在操作329中,源极和漏极可以在快速热退火(RTA)工艺中进行热退火。热退火可以生成金属间化合物或合金。在一个实施例中,在大约800到900摄氏度并在惰性环境中制造合金。在另一个实施例中,在氮环境中制造含氮的金属间化合物。其他退火环境包括用于产生一些导电氧化物的氧环境和外界环境。如所描述的,对源极和漏极进行退火也可以导致金属层与来自施主供应层的下层材料的相互作用。产物可以是包括来自下层材料的源极和漏极。实际上,在一些实施例中,由于一些金属扩散到施主供应层中并且来自施主供应层的一些铝、镓和氮扩散到源极和漏极中,所以源极和/或漏极的尺寸增大。
再次参照图3A,在操作309中,在源极和漏极之间形成栅极结构。类似于源极/漏极形成工艺,在多个步骤中形成栅极结构。根据一些实施例,可以首先通过光刻工艺来限定栅极结构,或者可以首先保护源极/漏极。然后,在施主供应层上方用CVD工艺或金属CVD工艺沉积栅极材料。如所描述的,栅极材料可以包括钨(W)、氮化钛(TiN)、和钽(Ta)中的一种或多种。然后,蚀刻掉多余的栅极材料,从而获得图4C的结构。图4C的结构在施主供应层411上方包括位于源极415和漏极417之间的栅极结构419。
再次参照图3A,在操作311中,蚀刻漂移区中施主供应层的一部分。可以首先沉积光刻胶层和进行图案化,以保护源极/漏极、栅极结构、以及施主供应层的不被蚀刻的部分。蚀刻图案可以是图2A至图2D的多个结构中的一个,或者是根据本发明的创造性概念由本领域技术人员所讨论或设计的其他结构。仔细地选择蚀刻工艺和蚀刻剂材料来防止过蚀刻施主供应层,从而会导致HEMT操作不正确并且改变HEMT的电性能。如上所述,不去除施主供应层的一部分或者至少指定厚度的施主供应层。因此,使用慢蚀刻工艺来控制蚀刻的量。在一些实施例中,在等离子体中使用氯基蚀刻剂(chlorine-based etchant)来以大约每分钟1纳米的速率进行蚀刻。在该低速下,可以精确地控制蚀刻量。在其他实施例中,可以使用具有趋于使蚀刻速率降低的工艺参数的氟基蚀刻剂(fluorine-based etchant)。例如,可以在腔室中减少等离子体的功率和压力。图4D示出了在施主供应层411的漂移区中具有开口415的部分制造的HEMT。尽管仅示出一个开口415,但是多个实施例包括结合图2A至图2D所讨论的至少一个开口的任意数目。
一旦开口或空腔形成在施主供应层中,就去除保护源极/漏极、栅极结构和施主供应层的部分的光刻胶。在操作313中,在施主供应层上方沉积介电层。图3C很详细地示出了该操作313。在操作331中在硅衬底上方沉积介电层。电介质填充图3A的操作311中蚀刻的开口并且完全覆盖源极和栅极结构之间以及栅极结构和漏极之间的施主供应层。介电层还形成在源极/漏极和栅极结构上方。介电层可以是氧化硅、氮化硅、氮氧化硅、掺碳氧化硅、掺碳氮化硅、掺碳氮氧化硅、氧化锌、氧化锆、氧化铪或者氧化钛。使用诸如,化学汽相沉积(CVD)的已知工艺来沉积介电层。
在操作333中,沉积并图案化光刻胶以暴露源极、漏极和栅极结构。在操作335中,通过蚀刻工艺去除源极、漏极和栅极结构上方的介电层,从而生成图4E的结构。介电层404在源极415和栅极结构419之间以及栅极结构419和漏极417之间形成施主供应层411上方。值得注意的是,尽管示出了平面的介电层404,但是根据介电层404的厚度,介电层的顶面可以具有盘状,其靠着金属结构的边缘比中间部分厚。在一些实施例中,介电层404可以沉积为超过金属结构(415、419和417)的高度,然后,使用化学机械抛光(CMP)工艺向下对其进行平坦化来达到相同的高度。然后,如果要求介电层的厚度小于金属结构的厚度,则可以通过对介电层404进一步进行等离子体蚀刻来获得平坦的顶部介电层404。形成基础的HEMT结构之后,随后的操作包括使用本领域已知的半导体工艺和设计沉积接触件、金属互连件的第一层以及金属间介电(IMD)材料。
图5是根据本发明的多个实施例模拟峰值表面电场作为HEMT结构上的位置函数的曲线图。根据沿着穿过HEMT的线的距离(从距离0处的源极的远边穿过距离约1.5和2之间的栅极结构到达距离12.5处的漏极的远边)绘制以伏特每厘米为单位的电场。该仿真模拟-5伏的栅极电压和600伏的漏极偏压。峰值对应于最靠近漏极的栅极结构边缘。线501是用于没有本文所公开的电介质插塞的HEMT的仿真结果。线501的峰值电场约为6E6V/cm。线503是在栅极结构和漏极之间具有一个电介质插塞的HEMT的仿真结果。线503的峰值电场约为3.6E6V/cm,减少了大约40%。该仿真结果示出了本文所公开的电介质插塞确实能降低HEMT中的峰值表面电场。虽然峰值电场值会根据仿真中所模仿的结构而变化,但是电介质插塞的相对作用是清楚的。
本发明的实施例可以具有多种变型例。例如,电介质插塞可以包括多于一种的材料,诸如,氮化镓层上方的氧化镍层。本发明的某些实施例具有几种有益的特征。使用多种掺杂种类允许细调电介质插塞,并进而细调击穿电压,同时最小化对其他电性能(诸如,最大正向电流或漏电流)的不利影响。
尽管已经详细地描述了本发明及其优点,但应该理解,可以在不背离所附权利要求限定的本发明主旨和范围的情况下,做各种不同的改变、替换和更改。而且,本申请的范围并不仅限于本说明书中描述的工艺、机器、制造、材料组分、装置、方法和步骤的特定实施例。作为本领域普通技术人员应理解,通过本发明,用于执行与根据本发明所采用的所述相应实施例基本相同的功能或获得基本相同结果的工艺、机器、制造、材料组分、装置、方法或步骤根据本发明可以被使用。因此,所附权利要求应该包括在这样的工艺、机器、制造、材料组分、装置、方法或步骤的范围内。
Claims (10)
1.一种高电子迁移率晶体管(HEMT),包括:
硅衬底;
非故意掺杂氮化镓(UID GaN)层,位于所述衬底上方;
施主供应层,位于所述UID GaN层上方;
栅极结构、漏极和源极,位于所述施主供应层上方,所述栅极结构设置在所述漏极和所述源极之间;以及
介电层,在所述栅极结构和所述漏极之间位于所述施主供应层上方,所述介电层具有位于所述施主供应层中的一个或多个第一部分以及位于所述一个或多个第一部分和所述施主供应层上方的第二部分;
其中,所述一个或多个第一部分中的至少一个紧邻所述栅极。
2.根据权利要求1所述的HEMT,其中,所述介电层包括氧化锌、氧化锆、氧化铪或氧化钛。
3.根据权利要求1所述的HEMT,其中,所述介电层包括氧化硅、氮化硅、氮氧化硅、掺碳氧化硅、掺碳氮化硅或掺碳氮氧化硅。
4.根据权利要求1所述的HEMT,其中,所述施主供应层位于所述介电层的所述一个或多个第一部分下方的部分的厚度为至少15纳米。
5.根据权利要求1所述的HEMT,其中,所述施主供应层位于所述介电层的所述一个或多个第一部分下方的部分的厚度至少为所述施主供应层直接位于所述介电层的所述第二部分下方的部分的厚度的40%。
6.根据权利要求1所述的HEMT,其中,所述介电层的所述一个或多个第一部分是一个第一部分,并且所述第一部分的面积为所述施主供应层的漂移区的面积的约5%至约20%。
7.根据权利要求1所述的HEMT,其中,所述一个或多个第一部分中的所述至少一个邻近栅极边缘。
8.根据权利要求1所述的HEMT,其中,从上往下看时,所述介电层的所述一个或多个第一部分为四边形。
9.根据权利要求1所述的HEMT,其中,所述介电层的所述一个或多个第一部分和所述施主供应层围绕所述介电层的所述一个或多个第一部分的部分形成棋盘图案。
10.一种方法,包括:
提供硅衬底;
在所述硅衬底上方外延生长氮化镓(GaN)层;
在所述GaN层上方外延生长施主供应层;
在所述施主供应层上形成源极和漏极;
在所述施主供应层上形成位于所述源极和所述漏极之间的栅极结构;
将所述施主供应层的漂移区的一部分等离子体蚀刻到小于施主供应层厚度的60%的深度;以及
在所述施主供应层上方沉积介电层。
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