CN103107104A - 一种倒装芯片的制作方法 - Google Patents

一种倒装芯片的制作方法 Download PDF

Info

Publication number
CN103107104A
CN103107104A CN2011103576546A CN201110357654A CN103107104A CN 103107104 A CN103107104 A CN 103107104A CN 2011103576546 A CN2011103576546 A CN 2011103576546A CN 201110357654 A CN201110357654 A CN 201110357654A CN 103107104 A CN103107104 A CN 103107104A
Authority
CN
China
Prior art keywords
chip
temperature
manufacture method
flip
flip chip
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN2011103576546A
Other languages
English (en)
Inventor
金鹏
李宁
施建根
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Peking University Shenzhen Graduate School
Nantong Fujitsu Microelectronics Co Ltd
Original Assignee
Peking University Shenzhen Graduate School
Nantong Fujitsu Microelectronics Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Peking University Shenzhen Graduate School, Nantong Fujitsu Microelectronics Co Ltd filed Critical Peking University Shenzhen Graduate School
Priority to CN2011103576546A priority Critical patent/CN103107104A/zh
Publication of CN103107104A publication Critical patent/CN103107104A/zh
Pending legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/1012—Auxiliary members for bump connectors, e.g. spacers
    • H01L2224/10122—Auxiliary members for bump connectors, e.g. spacers being formed on the semiconductor or solid-state body to be connected
    • H01L2224/10125—Reinforcing structures
    • H01L2224/10126—Bump collar
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/113—Manufacturing methods by local deposition of the material of the bump connector
    • H01L2224/1133—Manufacturing methods by local deposition of the material of the bump connector in solid form
    • H01L2224/11334—Manufacturing methods by local deposition of the material of the bump connector in solid form using preformed bumps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/114—Manufacturing methods by blanket deposition of the material of the bump connector
    • H01L2224/11444—Manufacturing methods by blanket deposition of the material of the bump connector in gaseous form
    • H01L2224/1145—Physical vapour deposition [PVD], e.g. evaporation, or sputtering
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/114—Manufacturing methods by blanket deposition of the material of the bump connector
    • H01L2224/1146—Plating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/1147—Manufacturing methods using a lift-off mask
    • H01L2224/1148—Permanent masks, i.e. masks left in the finished device, e.g. passivation layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/118—Post-treatment of the bump connector
    • H01L2224/11848—Thermal treatments, e.g. annealing, controlled cooling
    • H01L2224/11849—Reflowing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/1301—Shape
    • H01L2224/13012—Shape in top view
    • H01L2224/13014—Shape in top view being circular or elliptic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13101—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of less than 400°C
    • H01L2224/13105—Gallium [Ga] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16238—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bonding area protruding from the surface of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8112—Aligning
    • H01L2224/81136—Aligning involving guiding structures, e.g. spacers or supporting members
    • H01L2224/81138—Aligning involving guiding structures, e.g. spacers or supporting members the guiding structures being at least partially left in the finished device
    • H01L2224/81141—Guiding structures both on and outside the body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8119—Arrangement of the bump connectors prior to mounting
    • H01L2224/81191—Arrangement of the bump connectors prior to mounting wherein the bump connectors are disposed only on the semiconductor or solid-state body

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Wire Bonding (AREA)

Abstract

本发明涉及一种生成凸起并在凸起界定区域内使用合金Ga-In制作凸点的倒装芯片制作方法。所述倒装芯片的制作方法包括：在芯片上生长凸起；在凸起界定的区域内放入合金Ga-In薄片，升高温度使薄片重熔，材料布满整个界定区域中底部；在一定温度和压力下芯片凸点与布线板电极精确对位压接，经固化实现芯片的倒装。本发明由于界定区域的凸起位置固定，使得凸点定位精度高，并且凸点节距可以达到25μm。本发明不需要高温环境，能有效避免因高温而造成的器件失效现象，尤其适合某些特殊器件封装，如热敏器件、光电器件。

Description

一种倒装芯片的制作方法
技术领域
本发明涉及一种倒装芯片方法，更具体地涉及在芯片上围绕电极生成凸起，在其界定区域内用合金Ga-In形成凸点，并施以一定压力附着到布线板电极上的倒装芯片制作方法。
背景技术
将芯片固定或物理连接到基板上称为键合。键合的方法主要有：芯片键合、引线键合和倒装芯片键合。倒装芯片键合是在芯片的连接焊盘上形成凸点并直接连接到PCB基板的工艺。倒装芯片技术有明显的优点：封装密度最高；具有良好的电和热性能；可靠性好；成本低。该技术在电子产品方面可实现朝向更小器件发展，因此人们对倒装芯片引起了很大关注。
图1所示为传统倒装芯片凸点的结构，其组成包括：芯片1、钝化层2、铝焊盘3、凸点下金属层UBM(Under-Bump Metallurgy)4、凸点5。芯片凸点5是在原芯片铝布线电极焊区或重新布局的新焊区上形成的。为达到凸点金属5与铝焊盘3及钝化层2良好的粘附性，又要防止凸点金属5与铝焊盘3生成不希望有的金属间化合物，一般应先在凸点金属下制备有粘附层、扩散阻挡层和导电层的多层金属化层4。典型的粘附金属有Cr、Ti、Ni、TiN等，扩散阻挡层金属有W、Mo、Ni等，导电金属则常用Au、Cu、Pb/Sn等，这种多种金属化层常采用溅射、蒸发、化学镀、电镀等方法来完成。凸点金属5的制作材料多为Au、Cu、Pb/Sn、In或它们的组合。形成凸点5的方法主要有电镀法、化学镀法、钉头凸点形成法、模板印刷焊料法及热注射焊料法等。在这些凸点中，Pb/Sn焊料凸点因具有突出优点而备受重视。由于它是半球形，在倒装焊时随着焊料熔化可自对准定位，能控制Pb/Sn焊料的塌陷程度及凸点高度，所以又称为可控塌陷芯片连接技术(C4)。金凸点主要用于LCD驱动元件的TAB(tape automated bonding)和COG(chip on glass)实装，前者通过金凸点与电镀锡的引脚实现金属间键合，后者通过各向异性导电膜(ACF)实现Au凸点与LCD的ITO膜的连接。
传统的倒装芯片结构在焊料熔化，相邻凸点键合时，彼此容易出现短路现象，因此凸点的大小及间距受到限制。
发明内容
为解决上述问题，本发明的目的是提供一种倒装芯片方法，该方法可以有效的解决凸点键合时容易产生短路现象的问题，并实现较小的压点节距。
本发明的另一个目的是为倒装芯片提供一种新型材料，该金属材料粘附性好，熔点较低，在倒装片压接互联的过程中不需要很高温度，从而避免芯片受高温损伤。
为达到上述目的，本发明通过下面的实施方式实现。
本发明的实施方式包括：在芯片上生长围绕电极的凸起，凸起材料可以为硅胶、AB胶、黑胶的一种。在凸起界定的区域内放入合金Ga-In薄片，合金成分的摩尔比例范围为：In 18.5％-100％，Ga 81.5％-0％，在高于对应成分的Ga-In合金熔点温度的条件下使薄片重熔，在低于对应成分熔点温度的条件下将芯片凸点与布线板电极精确对位，对每个芯片施以持续15秒，2-10kg压力进行压接。在凸起材料固化温度的条件下，实现倒装芯片的固化。
附图说明
图1为传统倒装芯片凸点的结构示意图；
图2为本发明的倒装芯片实施方法的流程图；
图3为布有电极的芯片的剖视图；
图4为在芯片上生成凸起的剖视图与凸起分布的俯视图；
图5为在芯片上生成底层金属UBM的剖视图；
图6为在凸起界定的区域内放入Ga-In薄片的剖视图；
图7为Ga-In薄片在凸起界定的区域内重熔的剖视图；
图8为布线板电极与芯片凸点对位压接的剖视图；
图9为对倒装芯片进行固化的剖视图。
具体实施方式
下面结合附图对本发明的技术方案作进一步描述。
图2为本发明的倒装芯片实施方法的流程图。如图2所示，本发明的倒装芯片实施方法包括：在芯片电极周围形成凸点(S11)，在芯片电极上形成凸点下金属层UBM(S12)，在芯片凸起的界定范围放入Ga-In合金薄片(S13)，在一定温度下重熔金属薄片(S14)，芯片与布线板的对位压接(S15)，对倒装芯片进行固化(S16)。
图3为芯片6上布有电极7的剖视图，电极的节距可以达到25-50μm。
图4左图为在芯片6上生成凸起8(S11)的剖视图，凸起8的制作方法有蒸发沉积、电镀、模板印刷等工艺，凸起8的制作材料有硅胶、AB胶、黑胶。这几种材料的共同优点是粘结能力强。凸起8将作为接下来倒装芯片制作过程中凸点材料的阻挡装置，用于界定凸点10的成型区域。其中，凸起8的宽度和高度以及凸起8的间距可以根据芯片电极7而改变。图4右图为芯片上凸起8分布的俯视图。凸起8的平面形状可以是圆形、方形、多边形等，本发明中凸起8的形状为圆形。
图5为在芯片上生成凸起下金属层UBM 9(S12)的剖视图。凸起下金属层9的制作方法有溅射、蒸发、化学镀、电镀等工艺。
图6为在凸起界定的区域内放入合金Ga-In薄片10(S13)的剖视图。Ga-In薄片10以相同剂量放入凸点的界定区域。Ga-In易被氧化，因此S13、S14、S15、S16中任一步骤都要在真空中进行操作。
图7为Ga-In薄片10在凸起界定的区域内重熔(S14)的剖视图。重熔温度设为高于对应成分的Ga-In熔点温度，Ga-In薄片10在这样的温度下在凸起界定的区域内重熔，布满整个界定区域中底部。
图8为布线板11的电极12与芯片6的凸点8对位压接(S15)的剖视图。在低于对应成分的Ga-In熔点温度下，将布线板11的电极12与芯片6的凸点8精确对位，通过合金Ga-In的粘附力保持相对位置，对每个芯片施加2-10kg的压力，持续时间15秒，实现其压接。
图9为对倒装芯片进行固化(S16)的剖视图。在相应凸点材料的固化温度下，实现倒装芯片的固化。
以上内容是结合具体的实施方式对本发明所作的进一步详细说明，不能认定本发明的具体实施只局限于这些说明。对于本发明所属技术领域的普通技术人员来说，在不脱离本发明构思的前提下，还可以做出若干简单推演或替换，都应当视为属于本发明的保护范围。

Claims (8)

1.一种倒装芯片方法，其特征在于包括：在芯片上生长围绕电极的凸起；在芯片电极上生成凸点下金属层UBM；在凸起界定的区域内放入Ga-In薄片，升高温度使薄片重熔，材料布满整个界定区域中底部；在一定温度和压力下芯片凸点与布线板电极精确对位压接，经固化实现芯片的倒装。
2.如权利要求1所述的方法，其特征在于，在基板上生长凸起的方法包括：蒸发沉积、电镀或丝网印刷中的一种，所述凸起的制作材料包括：硅胶、AB胶、黑胶中的一种。
3.如权利要求1所述的方法，其特征在于，所述凸起的形状包括圆形、方形或多边形中的任一种。
4.如权利要求1所述的方法，其特征在于，生成凸点下金属层UBM的方法包括：溅射、蒸发、化学镀、电镀中的一种。
5.如权利要求1所述的方法，其特征在于，合金Ga-In中两种金属成分的摩尔比例范围为：In 18.5％-100％，Ga 81.5％-0％，所对应的Ga-In熔点为30℃-156.6℃，Ga-In薄片重熔温度为高于对应成分的Ga-In熔点的温度，在这样的温度下薄片重熔并布满整个界定区域的中底部。
6.如权利要求1所述的方法，其特征在于，将Ga-In薄片材料放入凸起界定区域内。
7.如权利要求1所述的方法，其特征在于，在低于该成分的Ga-In熔点温度下，使芯片凸点与布线板电极精确对位，对每个芯片施加2-10kg的压力，持续时间5-25秒，实现其粘附。
8.如权利要求1所述的方法，其特征在于，在低于凸起材料Tg点的温度条件下实现倒装芯片的固化。
CN2011103576546A 2011-11-11 2011-11-11 一种倒装芯片的制作方法 Pending CN103107104A (zh)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN2011103576546A CN103107104A (zh) 2011-11-11 2011-11-11 一种倒装芯片的制作方法

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN2011103576546A CN103107104A (zh) 2011-11-11 2011-11-11 一种倒装芯片的制作方法

Publications (1)

Publication Number Publication Date
CN103107104A true CN103107104A (zh) 2013-05-15

Family

ID=48314863

Family Applications (1)

Application Number Title Priority Date Filing Date
CN2011103576546A Pending CN103107104A (zh) 2011-11-11 2011-11-11 一种倒装芯片的制作方法

Country Status (1)

Country Link
CN (1) CN103107104A (zh)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103658899A (zh) * 2013-12-04 2014-03-26 哈尔滨工业大学深圳研究生院 一种单一取向Cu6Sn5金属间化合物微互连焊点结构的制备及应用方法
CN112186086A (zh) * 2019-06-17 2021-01-05 成都辰显光电有限公司 微型发光二极管芯片的键合方法

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1242106A (zh) * 1996-12-27 2000-01-19 西玛茨有限公司 突点焊接的半导体成像器件
US20020100973A1 (en) * 2000-06-08 2002-08-01 Salman Akram Collar positionable about a periphery of a contact pad and around a conductive structure secured to the contact pads, semiconductor device components including same, and methods for fabricating same
CN101437971A (zh) * 2006-05-08 2009-05-20 美国铟泰公司 用以降低金属间化合物厚度和金属及合金氧化的合金组合物和技术
CN101625986A (zh) * 2008-07-08 2010-01-13 南茂科技股份有限公司 芯片封装结构制程
WO2011030150A1 (en) * 2009-09-08 2011-03-17 Astron Advanced Materials Limited Soldering process using electrodeposited indium and/or gallium, and article comprising an intermediate layer with indium and/or gallium

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1242106A (zh) * 1996-12-27 2000-01-19 西玛茨有限公司 突点焊接的半导体成像器件
US20020100973A1 (en) * 2000-06-08 2002-08-01 Salman Akram Collar positionable about a periphery of a contact pad and around a conductive structure secured to the contact pads, semiconductor device components including same, and methods for fabricating same
CN101437971A (zh) * 2006-05-08 2009-05-20 美国铟泰公司 用以降低金属间化合物厚度和金属及合金氧化的合金组合物和技术
CN101625986A (zh) * 2008-07-08 2010-01-13 南茂科技股份有限公司 芯片封装结构制程
WO2011030150A1 (en) * 2009-09-08 2011-03-17 Astron Advanced Materials Limited Soldering process using electrodeposited indium and/or gallium, and article comprising an intermediate layer with indium and/or gallium

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103658899A (zh) * 2013-12-04 2014-03-26 哈尔滨工业大学深圳研究生院 一种单一取向Cu6Sn5金属间化合物微互连焊点结构的制备及应用方法
CN103658899B (zh) * 2013-12-04 2016-04-13 哈尔滨工业大学深圳研究生院 一种单一取向Cu6Sn5金属间化合物微互连焊点结构的制备及应用方法
CN112186086A (zh) * 2019-06-17 2021-01-05 成都辰显光电有限公司 微型发光二极管芯片的键合方法

Similar Documents

Publication Publication Date Title
US8101866B2 (en) Packaging substrate with conductive structure
US8450859B2 (en) Semiconductor device mounted structure and its manufacturing method
US8232192B2 (en) Process of bonding circuitry components
EP1796155A1 (en) Bump forming method and solder bump
EP1830399A1 (en) Resin composition for flip-chip packaging and resin composition for forming bump
US10147691B2 (en) Semiconductor structure and manufacturing method thereof
CN102456660A (zh) 堆叠式半导体封装件及其制造方法和半导体器件
CN101083238A (zh) 带有弹性导电凸块的微电子元件及其制造方法
US8779300B2 (en) Packaging substrate with conductive structure
CN101567355B (zh) 半导体封装基板及其制法
TW201314805A (zh) 半導體封裝結構銲帽凸塊與其製作方法
TWI230425B (en) Bumping process for light emitting diode
CN103107104A (zh) 一种倒装芯片的制作方法
CN101425489A (zh) 微电子封装中焊料凸点连接金属化层及应用
US9159687B2 (en) Solder bump for ball grid array
CN108493121B (zh) 一种解决双面电路晶元焊料短路的载板制作及封装方法
CN101360388B (zh) 电路板的电性连接端结构及其制法
TW200845251A (en) Bump structure for semiconductor device
CN210296353U (zh) 一种三维立体集成封装结构
CN102437063A (zh) 一种液态凸点倒装芯片的制作方法
CN110970457B (zh) 一种Micro-LED芯片及其制备方法、显示装置
CN103811442A (zh) 基板的连接结构及其制法
US20160329269A1 (en) Chip package structure and manufacturing method thereof
KR100744149B1 (ko) 은 범프를 이용한 반도체 패키지 구조 및 형성 방법
JP2014075317A (ja) 導電接続シート、半導体装置および電子機器

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
WD01 Invention patent application deemed withdrawn after publication
WD01 Invention patent application deemed withdrawn after publication

Application publication date: 20130515