CN103098211B - 多层存储阵列 - Google Patents
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Abstract
一种多层交叉存储阵列包括多个层(514)。每个层(514)包括一组平行的顶部线,与一组平行的顶部线相交叉的一组平行的底部线,以及被布置在一组平行的顶部线和一组平行的底部线之间的交叉位置的存储元件(200、216)。来自层(514)之一的一组平行的顶部线是层(514)中相邻层的一组平行的底部线。
Description
政府利益声明
本发明是在政府支持下完成的。政府拥有本发明的一些权利。
背景技术
随着数字数据的使用增加,对更快、更小和更有效的存储结构的需求也增加。一种近来开发出的存储结构是交叉存储阵列。交叉存储阵列包括与第二组平行导线相交叉的第一组导线。在第一组导线和第二组导线之间的交叉位置,放置被配置为存储数字数据的可编程存储元件。
传统上,建造更高密度的存储阵列是通过减小导线宽度和存储元件的尺寸来实现的。然而,更小的导线宽度和更小的存储元件导致更昂贵和更复杂的制造过程。
一种建造更高密度存储阵列的方法是在第三维度上堆叠交叉阵列。然而,在通常的用于制造交叉阵列的光刻工艺中,堆叠交叉阵列需要更多掩模。使用的掩模越多,在第三维度上堆叠存储阵列会越昂贵。
附图说明
附图图示本发明中描述的原理的各个实施例并且是说明书的一部分。所图示的实施例仅是示例,而不限制权利要求的范围。
图1是根据本发明中描述的原理的一个示例示出说明性交叉阵列的示意图。
图2A是根据本发明中描述的原理的一个示例示出说明性底部有向存储元件及其伴随电路图的图。
图2B是根据本发明中描述的原理的一个示例示出说明性顶部有向存储元件及其伴随电路图的图。
图3A是根据本发明中描述的原理的一个示例示出图2A的底部有向装置的说明性电流与电压关系的图。
图3B是根据本发明中描述的原理的一个示例示出图2B的顶部有向装置的说明性电流与电压关系的图。
图4是根据本发明中描述的原理的一个示例示出多层存储阵列中的交叉点的说明性立体图的图。
图5是根据本发明中描述的原理的一个示例示出多层存储阵列中的交叉点的说明性侧视图的图。
图6是根据本发明中描述的原理的一个示例示出说明性的在多层存储阵列中存取数据的方法的流程图。
在所有附图中,相同的附图标记表示相似但不一定相同的元件。
具体实施方式
如上所述,一种建造更高密度存储阵列的方法是在第三维度中堆叠交叉阵列。然而,在通常的用于制造交叉阵列的光刻工艺中,堆叠交叉阵列需要更多掩模。使用的掩模越多,在第三维度中堆叠存储阵列会越昂贵。
鉴于该问题和其它问题,本说明书公开了在光刻制造工艺中使用较少掩模的多层存储阵列。根据特定的说明性示例,在多层存储阵列中,来自两个相邻层的存储元件共享这两个层之间的导线。另外,除存储数据以外,这些存储元件被配置为像二极管一样工作。二极管允许一个方向的电流,同时抑制电流在相反方向的流动。如下文将更详细地描述的,这些存储元件的类二极管特性允许在没有来自相同层和相邻层中的未选存储元件的负面影响的情况下访问目标存储元件。
通过使用包含本发明中描述的原理的方法和系统,实现了在光刻制造工艺中需要较少掩模的多层存储阵列。具体地,该多层存储阵列将仅需要N+1个掩模,而不是2*N个掩膜,其中N是掩模数量。这允许以低成本生产高密度多层存储阵列。
在下面的描述中,为了进行说明,阐述多个具体细节来提供本系统和方法的全面理解。然而,将对本领域技术人员而言显而易见的是,本装置、系统和方法可以在没有这些具体细节的情况下实践。说明书中对“实施例”、“示例”或类似语言的引用指的是,关于该实施例或该示例描述的特定特征、结构或特性至少包含在这个实施例中,而不一定包含在其它实施例中。在说明书各处,短语“在一个实施例中”或类似短语的不同实例不一定全部都指同一实施例。
在整个本说明书和所附权利要求中,形成交叉存储阵列的导线被称为“行线”和“列线”。这些词语不表示特定方向。相反,它们表示相对于彼此的方向。
现在参考附图,图1是示出说明性交叉存储阵列(100)的示意图。根据特定说明性示例,交叉阵列(100)包括一组行线(102),该组行线(102)通常是平行的。另外,一组列线(104)通常垂直于行线(102)并且与行线(102)相交叉。在行线(108)和列线(110)之间的交叉位置,布置可编程存储元件(106)。
根据特定说明性示例,可编程存储元件(106)可以是忆阻装置。忆阻装置表现过去电刺激的“存储器”。例如,忆阻装置可以包括包含移动掺杂物的忆阻基体材料。这些掺杂物能够在基体中移动来动态改变忆阻装置的电操作。
掺杂物的运动可以通过施加像在适合的基体上的施加电压这样的编程条件来诱导。编程电压产生穿过忆阻基体的相对高的电场并改变掺杂物的分布。在去掉电场以后,掺杂物的位置和特性保持稳定直到施加另一编程电场。例如,通过改变忆阻基体中的掺杂物构成,可以改变装置的电阻。忆阻装置通过施加低读取电压来读取,低读取电压允许检测到忆阻装置的内电阻而不产生足够的导致显著掺杂物运动的电场。因此,忆阻装置的状态在长时间段后并经过多个读取周期仍可以保持稳定。
根据特定说明性示例,交叉阵列(100)可以用来形成非易失性存储阵列。每个可编程存储元件(106)用来代表数据的一个或多个比特。尽管图1中示出单独的行线(108)和列线(110)具有矩形截面,但是交叉还可以具有方形、圆形、椭圆形或更复杂的截面。导线还可以具有许多不同的宽度、直径、宽高比和/或偏心率。交叉可以是纳米线、亚微级线、微级线或具有更大尺寸的线。
在一些实例中,存储元件可以通过存储元件的电极之间的通路与行线(102)和列线连接。这些通路可以经过在存储元件和导线之间放置的层间介电材料。介电材料抑制电流的流动。
根据特定说明性示例,交叉结构(100)可以集成到互补金属氧化物半导体(CMOS)电路或其它传统计算机电路中。每条单独的位线可以通过通路(112)连接至CMOS电路。通路(112)可以表现为通过在制造交叉结构时使用的各个基板材料的导电路径。该CMOS电路能够向忆阻装置提供附加功能,例如输入/输出功能、缓冲、逻辑、组态或其它功能。多个交叉阵列能够在CMOS电路上方形成,以建造多层电路。
行线(102)和列线(104)可以充当字线和位线。字线用来存取位的整个字,位线用来存取字中的特定位。字是为处理目的而被组合在一起的一组位。例如,处理器体系结构通常被设计为处理字而非单独的位。
如上文所述,交叉阵列中的存储元件可以是忆阻存储元件。忆阻存储元件抑制固有的非线性行为。该非线性行为允许忆阻存储元件模拟二极管的行为。为了选择交叉阵列中的存储元件,选择连接至该存储元件的行线和列线。通过向这些线施加电压来选择线。在实际的交叉阵列中,没有选择装置或晶体管防止电流非特意地经过具有低电阻的替代路径。这些替代路径被称为潜通路(sneak path)。忆阻存储元件的类二极管特性能够防止存储阵列中的潜通路。
图2A和2B图示存储元件(例如图1的106)的两种可能构造。图2A是示出说明性顶部有向存储元件(200)及其伴随电路图(218)的图。顶部有向存储元件(200)是允许电流从底部电极(208)向顶部电极(202)流动并抑制电流从顶部电极(202)向底部电极(208)流动的存储元件。在整个本说明书以及在所附权利要求中,词语“顶部”和“底部”不表示特定位置,而是相对于彼此的位置。
根据一个说明性示例,顶部有向存储元件(200)包括与忆阻基体(214)电接触和物理接触的顶部电极(202)和底部电极(208)。忆阻基体(214)包括两个分离的区域:非故意掺杂的半导体区域(204)和高掺杂区域(206)。
词语“忆阻基体”描述由具有电子半导体性的材料或名义上电绝缘的材料构成的薄膜,还描述弱离子导体。忆阻基体(214)能够传输和容纳充当掺杂物的离子,以控制电子通过忆阻存储元件(200)的流动。基本工作模式是施加电场(漂移场),电场可以超过使离子能够穿越忆阻装置在忆阻基体(214)中运动的有效阈值。电场足够大,以使离子种类经由离子传输在忆阻基体(214)中传输。离子种类具体地选自充当忆阻基体(214)的电子掺杂物的那些离子,并且因此将基体的导电性从高阻态改变成低阻态。此外,选择忆阻基体(214)和掺杂物种类,使得掺杂物在忆阻基体(214)中的漂移是可能但不那么容易的。这确保忆阻装置保持在其被设置的任何状态下相当长的时间,在室温下可能许多年。因此,忆阻存储元件(200)是非易失性的。非易失性的装置是在接收功率或不接收功率的情况下保持其状态的装置。
基体材料可以是通常小于200nm厚的薄膜,并且在很多情况下是纳米晶或非结晶的。掺杂物种类在这样的纳米结构化的材料中的迁移率大大地高于在块结晶材料中的迁移率,因为扩散能够通过晶界、孔隙或通过非结晶材料中的局部结构缺陷发生。此外,由于膜是如此薄,所以将足够的掺杂物漂移到薄膜的局部区域内或漂移出薄膜的局部区域以显著改变薄膜的导电性所需的时间量是相对快速的。纳米级的忆阻装置的另一优点是能够由相对小的施加电压产生大的电场。
电子通过基体材料的输送经常受到电子的量子力学隧道效应控制。当半导体性的基体材料在具有电极的结处的近距离上实质是本征的时,隧穿势垒是高和宽的,这促使忆阻装置处于高阻态。当将相当数量的掺杂物种类注入到本征半导体的一部分内或者分散到本征半导体的一部分中时,隧穿势垒的宽度或许和高度被带电种类的电势减弱。这导致元件导电率的升高,将忆阻存储元件(200)置于低阻态。
半导体性区域(204)具有非常少的掺杂物并且防止电流在两个电极(202、208)之间流动。高掺杂区域(206)是导电的并且用作掺杂物的源,该掺杂物能够移动到半导体性区域(204)中以改变忆阻基体(214)的整体导电性。
忆阻基体材料可以包括多种金属氧化物,例如二氧化钛、氧化钒、氧化钽、氧化镍、氧化铪、氧化锆、氧化铜和氧化铁。忆阻基体材料还可以包括三氧化物(tertiary oxide),例如氧化钛锶(SrTiO3)。电极(202、208)可以由多种导电材料构成,导电材料包括但并不限于金属、金属合金、金属复合材料、纳米结构的金属材料、重掺杂的半导体或其它适合的导电材料。电极可以是非还原性导电材料,以便不干预忆阻基体(214)材料的氧化物。
可以施加编程电压,以改变忆阻存储元件(200)的状态。编程电压产生电场,电场不仅促进掺杂物从高掺杂区域(206)移动至本征半导体性区域(204)中,而且促进在氧化忆阻材料中经由电还原过程产生一些本地掺杂物,例如氧空位(oxygen vacancy)。
在忆阻基体(214)上施加的极性和电压差根据许多因素变化,因素包括但不限于材料特性、几何形状、掺杂物种类、温度和其它因素。例如,当离子带正电荷时,离子被正电压势排斥并被吸引到负电压势。
根据一个说明性示例,在顶部电极(202)和底部电极(208)之间施加正电压差。这将半导体性区域(204)和高掺杂区域(206)之间的界面推向底部电极(208)。这是因为带正电荷的掺杂物会进一步从半导体性区域(204)扩散到高掺杂区域(206)中,这增加了隧穿势垒的宽度。这使得顶部有向存储元件(200)更具有电阻性并且降低了电流的流动。另外,半导体性区域(204)和顶部电极(202)之间的结充当二极管(210)。等效电路图(218)示出与电阻(212)串联的二极管(210)。
当从顶部电极(202)至底部电极(208)施加负电压差时,氧空位掺杂物进一步移动至半导体性区域中并离开底部电极(208)。这减少了本征层的厚度,因此减少了隧穿势垒的宽度。这减少了顶部有向存储元件(200)的电阻并提高了电流的流动。
图2B是示出说明性底部有向存储元件(216)及其伴随电路图的图。底部有向存储元件(216)类似于顶部有向存储元件(200)。差别在于高掺杂区域(206)和半导体性区域(214)的位置是互换的。
在图2B中,当相对于底部电极(208)向顶部电极施加负电压时,半导体性区域(204)和高掺杂区域(206)之间的界面向顶部电极(202)移动。这促使存储元件(216)更具有电阻性并且抑制了电流的流动。
当相对于底部电极(208)向顶部电极(202)施加正电压时,底部有向存储元件(216)于是变成不那么具有电阻性。这允许电流通过存储元件(216)的流动。另外,半导体性区域(204)和底部电极(208)之间的结表现得像二极管(210)。该二极管在电路图(220)中示出。
图3A是示出图2A的顶部有向存储元件的说明性电流与电压关系的图。从图(300)中可以看出,当在顶部电极到底部电极之间施加正电压V,正电流I将流过存储元件。作为约定,正电流表示电流从顶部电极(例如图2的202)向底部电极(例如图2的208)流动。当将零电压或较小电压施加在底部有向存储元件上时,可忽略的电流量将流过存储元件。
图3B是示出图2B的底部有向存储元件的说明性电流与电压关系的图。横轴表示电压(304),竖轴表示电流(302)。从图(308)中可以看出,当在顶部电极和底部电极之间施加负电压-V,负电流-I流过存储元件。作为约定,负电流表示电流从存储元件的底部电极向顶部电极流动。当施加零电压或更高电压时,可忽略的电流量流过存储元件。
图4是示出多层存储阵列中的交叉点(400)的说明性立体图的图。根据特定说明性示例,底部有向存储元件(404)被放置在第一线(406)和与第一线(406)相对垂直的第二线(408)之间。另外,顶部有向存储元件(402)被放置在第二线和与第二线(408)大体垂直的第三线之间。
具体地,底部有向存储元件的底部电极与第一线(406)电接触。另外,底部有向存储元件(404)的顶部电极和顶部有向存储元件(402)的底部电极都与第二线(408)电接触。另外,顶部有向存储元件(402)的顶部电极与第三线(410)电接触。
第一线(406)、第二线(408)和第三线(410)每条线代表一组平行线之一。在一个示例中,第一线(406)和第三线可以对应于位线,第二线(408)可以对应于字线。
根据一个示例,为了访问阵列中的特定存储元件,在特定存储元件上施加电压。待访问的存储元件将被称为目标存储元件。为了在目标存储元件上施加电压,将电压切换到与目标存储元件的顶部电极连接的线上和与目标存储元件的底部电极连接的线上。
为访问目标存储元件而在该目标存储元件上施加的电压电平的幅度取决于是想要读取目标存储元件的状态还是想要写入目标存储元件的状态。为了读取目标存储元件的状态,通常施加较低电压,以便不改变目标存储元件的状态。为了写入目标存储元件的状态,施加较高电压,以如上所述改变高掺杂区域(例如图2的206)和半导体性区域(例如图2的204)之间界面的位置。
根据一个说明性示例,为了访问底部有向存储元件(404),在存储元件(404)上施加电压V。为了导致在存储元件(404)上施加正电压V,将电压V/2(412)施加至与底部有向存储元件(404)的顶部电极连接的第二线(408)。另外,将电压-V/2(414)施加至与底部有向存储元件(404)的底部电极连接的第一线(406)。这将在底部有向存储元件(404)上导致电压降V。如果第三线(410)未被施加电压,那么顶部有向存储元件(402)仅仅看见电压-V/2。顶部有向存储元件(402)的类二极管特性防止电流形成通过多层阵列的这一层的潜通路。
为了访问顶部有向存储元件(402),在存储元件(404)上施加电压-V。为了导致在存储元件(404)上施加电压-V,将电压-V/2(414)施加至与顶部有向存储元件(402)的顶部电极连接的第三线(410)。另外,将电压V/2(412)施加至与顶部有向存储元件的底部电极连接的第二线(408)。这会在顶部有向存储元件(404)的顶部电极和底部电极之间导致电压降-V。
根据特定的说明性示例,可以对多个存储元件同时进行写入。这能够通过向一条线施加V/2并且沿该条线向多个存储元件施加-V/2来实现。例如,第二线(408)可以充当字线。向第二线(408)施加电压V/2。向与第一线(406)平行延伸的线施加电压-V/2。在第二线(408)和被施加-V/2的第一线(406)之间连接的每个底部有向存储元件(404)将受到影响。该过程被称为平行写入。
图5是示出多层存储阵列(500)中的一个交叉点的说明性侧视图的图。根据特定说明性示例,多个层可以被堆叠在彼此上方。每个层(514)将与相邻层(514)共享由行线(506)和/或列线(508)组成的层。行线(506)指在一个方向延伸的导电引线,列线(508)指在大体与行线垂直的方向上延伸的导电引线。行线(506)和列线(508)可以通过通路(510)与寻址电路(512)连接。
层1(514-1)包括一组底部有向存储元件(502)。因此,在每个交叉点处,底部有向存储元件(502)被放置在列线(508-1)和行线(506-1)之间。于是,电流能够从与列线(508-1)连接的顶部电极和与行线(506-1)连接的底部电极穿越底部有向存储元件(502)流动。在向行线(506)和列线(508)施加正常工作电压电平时,抑制电流从底部电极流向顶部电极。这防止来自层2(514-2)的各种电压和电流干预层1(514-1)的存储元件(502)。
层2包括一组顶部有向存储元件(504)。因此,允许电流从与列线(508-2)连接的底部电极和与行线(506-1)连接的顶部电极流动。在向行线(506)和列线(508)施加正常工作电压电平时,抑制电流在与层2(514-2)相关联的行线(506-1)和列线(508-2)之间流动。这防止来自层1(514-1)的各种电压和电流干预层2(514-2)的存储元件(504)。
层3(514-3)和层4(514-4)延续了在层1(514-1)和层2(514-2)之间展示的图案。层3(514-3)包括连接在列线(508-2)和行线(506-2)之间的一组底部有向存储元件(502)。层4(514-4)包括连接在行线(506-2)和列线(508-3)之间的一组顶部有向存储元件(504)。
通过在多层存储阵列中的相邻层之间共享相同的导体,在制造过程中使用减少的一组掩模。因此,制造过程不那么昂贵并且可以生产更高密度的存储阵列。通过每一连续层对顶部有向存储元件(504)和底部有向存储元件进行轮换,对一个层使用的读取/写入操作将不会负面地影响相邻层。
图6是示出用于形成多层存储阵列的说明性方法(500)的流程图。根据特定的说明性示例,该方法包括:用与存储阵列相关联的寻址电路,在被布置在第一组平行线和第二组平行线之间的第一存储元件上施加(框602)电压,第二组平行线与第一组平行线相交叉;以及用与存储阵列相关联的寻址电路,在被设置在第二组平行线和第三组平行线之间的第二存储元件上施加(框604)电压,第三组平行线与第二组平行线相交叉。
总之,通过使用包含本发明中描述的原理的方法和系统,实现了在相邻层之间共享多组导线的多层存储阵列。每一连续层对顶部有向存储元件和底部有向存储元件的轮换,确保了对一个层使用的读取/写入操作将不会负面影响相邻层。多层存储阵列使用减少的一组导电引线降低了制造成本并产生了更高密度的存储阵列。
提供上面的描述仅为了说明和描述包含所描述原理的实施例和实施例。本说明书不意味着是详尽的或者不意味着将这些原理局限于所公开的任何准确形式。鉴于上面的教导,许多修改和改变是可能的。
Claims (13)
1.一种多层存储阵列(500),包括:
多个层(514),每个层包括:
一组平行的顶部线,
与所述一组平行的顶部线相交叉的一组平行的底部线,以及
存储元件(200、216),设置在所述一组平行的顶部线和所述一组平行的底部线组之间的交叉位置;
其中,来自所述层(514)之一的一组平行的顶部线也是所述层(514)中相邻层的一组平行的底部线,
其中所述存储元件(200、216)是包括忆阻基体(214)的忆阻存储元件,所述忆阻基体(214)包括半导体性区域(204)和与所述半导体性区域(204)形成界面的高掺杂区域(206),其中所述高掺杂区域(206)是导电的并且用作能移动到所述半导体性区域(204)中的掺杂物的源。
2.根据权利要求1所述的存储阵列,其中所述忆阻存储元件包括金属氧化物材料。
3.根据权利要求1所述的存储阵列,其中所述存储元件(200、216)抑制电流在一个方向上的流动。
4.根据权利要求3所述的存储阵列,其中来自所述层(514)之一的所述存储元件(200、216)中的每个存储元件抑制电流在一个方向上流动,在所述层(514)中相邻层中的所述存储元件(200、216)中的每个存储元件抑制电流在与所述一个方向相反的方向上流动。
5.根据权利要求1所述的存储阵列,其中在所述存储元件两端的电极包括非还原性导电材料。
6.根据权利要求1所述的存储阵列,其中为了访问所述层(514)之一的存储元件(200、216),电压被施加至来自所述一组平行的顶部线的第一线和来自所述一组平行的底部线的第二线,所述顶部线和所述底部线连接至所述存储元件。
7.根据权利要求1所述的存储阵列,其中施加至来自所述层(514)之一的存储元件的电压的极性在将所述电压至所述层(514)中相邻层中的存储元件时被颠倒。
8.根据权利要求1所述的存储阵列,其中沿着相同线的多个存储元件(200、216)同时被访问。
9.一种存储系统,包括:
寻址电路;以及
多层交叉存储阵列(500),包括:
与第二组平行线相交叉的第一组平行线,第一组存储元件(200)被设置在所述第一组平行线和所述第二组平行线之间的交叉位置,
与所述第二组平行线相交叉的第三组平行线,第二组存储元件(216)被设置在所述第二组平行线和所述第三组平行线之间的交叉位置;
其中所述第一组存储元件(200)抑制第一方向上的电流,所述第二组存储元件(216)抑制与所述第一方向相反的第二方向上的电流,
其中所述第一组存储元件(200)和所述第二组存储元件(216)是包括忆阻基体(214)的忆阻存储元件,所述忆阻基体(214)包括半导体性区域(204)和与所述半导体性区域(204)形成界面的高掺杂区域(206),其中所述高掺杂区域(206)是导电的并且用作能移动到所述半导体性区域(204)中的掺杂物的源。
10.根据权利要求9所述的系统,其中所述忆阻存储元件包括金属氧化物材料。
11.根据权利要求9所述的系统,其中在所述第一组存储元件(200)和所述第二组存储元件(216)两端的电极包括非还原性导电材料。
12.根据权利要求9所述的系统,其中为了访问所述第一组存储元件(200),第一电压被选择性地施加至所述第一组平行线和所述第二组平行线。
13.一种在多层存储阵列中访问数据的方法,所述方法包括:
用与所述存储阵列相关联的寻址电路,在被布置在第一组平行线和第二组平行线之间的第一存储元件(200)上施加电压,所述第二组平行线与所述第一组平行线相交叉;以及
用与所述存储阵列相关联的所述寻址电路,在被布置在所述第二组平行线和第三组平行线之间的第二存储元件(216)上施加电压,所述第三组平行线与所述第二组平行线相交叉;
其中所述第一存储元件(200)抑制第一方向上的电流,所述第二存储元件(216)抑制与所述第一方向相反的第二方向上的电流,
其中所述第一存储元件(200)和所述第二存储元件(216)是包括忆阻基体(214)的忆阻存储元件,所述忆阻基体(214)包括半导体性区域(204)和与所述半导体性区域(204)形成界面的高掺杂区域(206),其中所述高掺杂区域(206)是导电的并且用作能移动到所述半导体性区域(204)中的掺杂物的源。
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KR101448412B1 (ko) | 2014-10-07 |
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US20130114329A1 (en) | 2013-05-09 |
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US9293200B2 (en) | 2016-03-22 |
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