CN103094317B - The domain structure of the high withstand voltage field effect transistor of isolated form - Google Patents
The domain structure of the high withstand voltage field effect transistor of isolated form Download PDFInfo
- Publication number
- CN103094317B CN103094317B CN201110340126.XA CN201110340126A CN103094317B CN 103094317 B CN103094317 B CN 103094317B CN 201110340126 A CN201110340126 A CN 201110340126A CN 103094317 B CN103094317 B CN 103094317B
- Authority
- CN
- China
- Prior art keywords
- region
- field plate
- drain region
- conduction type
- drift
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Abstract
The invention discloses the high withstand voltage field effect transistor of a kind of isolated form, extend in the drift region in drain region by silicon substrate substrate and encase whole source region, form the substrate in source region and the isolation of silicon substrate substrate, the substrate electric potential that can realize field effect transistor can not affect by the current potential of silicon substrate substrate, independently adds current potential.The present invention also provides the domain structure of the high withstand voltage field effect transistor of a kind of isolated form, comprise drain region, source region, drift region, drain region, drift region, source region polysilicon field plate and grid and drain region polysilicon field plate, source region polysilicon field plate and grid and drain region polysilicon field plate are U-shaped closing structure, and drain region polysilicon field plate is positioned at the inside of source region polysilicon field plate and grid, utilize the structure in whole encirclement drain region, source region, bottom U-shaped internal layer, circular arc place adopts substrate+injection+doped region, drift region composition isolation pressure ring simultaneously, avoid this place's high-voltage outside, low pressure current potential is interior, power line is concentrated affects puncture voltage, device area is reduced while height is withstand voltage.
Description
Technical field
The present invention relates to semiconductor integrated circuit field, particularly the high withstand voltage field effect transistor of a kind of isolated form and domain structure.
Background technology
The high withstand voltage N-type field effect transistor of the non-isolation type that the withstand voltage field effect transistor of height used at present is normally formed on P-type silicon substrate substrate 301, cross section as shown in Figure 2, P-type silicon substrate substrate 301 carries out N-type injection and is formed with N-type drift region 302, source region is positioned at outside N-type drift region 302, and the substrate P type trap 303 of field effect transistor is connected together with P-type silicon substrate substrate 301.N+ active area 307, drift region, drain region 403 is drawn, and forms drain region 401, and generate in drift region, drain region 403 and have an oxygen isolation 305, the below of field oxygen isolation 305 is formed with the P type doped region 304 different from drift region, drain region 403 ion implantation type.Source is formed by N+ active area 306, and the substrate P type trap 303 of field effect transistor draws active area, P+ active area 308, N+ 306 and P+ active area 308 connects together with metal, forms source region 402.Source region is also formed with P type doped region for 402 times, and the P type doping 304 that field, drain region oxygen is isolated under 305 keeps certain distance.Above field, drain region oxygen isolation 305, be coated with polysilicon field plate 309, this field plate and grid polycrystalline silicon are that same polysilicon forms grid, and cover on the P type doped region in P type doped region, drain region 304 and source region.Field oxygen isolation 305 near drain region is coated with polysilicon 310, connects together with the N+ active area 307 that metallic aluminium 312 and drain region 401 are drawn, form drain region field plate.On Metal field plate 311 limit in source region, with a certain distance from placing another root Metal field plate 313, Metal field plate 313 and grid polycrystalline silicon connect together.
As shown in Figure 1, source region polysilicon field plate and grid 309 are non-occluded configuration to the surface plate graph structure of above-mentioned non-isolation type field effect transistor, and the cross section at B-B and C-C place is as Fig. 2 structure.
The substrate of the high withstand voltage field effect transistor of above-mentioned non-isolation type cannot be opened with silicon substrate substrate isolation, in some circuit design, require that source region just cannot use when connecing certain potentials, and said structure cannot realize.In raising is withstand voltage, in the high withstand voltage field-effect tube structure of existing non-isolation type, drift region position A-A cross section, drain region shown in Fig. 1 adopts structure shown in Fig. 3, namely P-type silicon substrate substrate 301 and N-type drift region 302 are carried out withstand voltage, owing to being that complete PN junction exhausts withstand high pressures, in order to provide enough depletion region enough withstand voltage to bear, the P type substrate regional compare of needs is large, and the area of whole device can be caused bigger than normal.
Summary of the invention
The technical problem to be solved in the present invention is to provide one
The technical problem to be solved in the present invention is to provide the domain structure of the high withstand voltage field effect transistor of a kind of isolated form, can provide high withstand voltage, reduce the area in high withstand voltage region simultaneously, the high withstand voltage field effect transistor of the isolated form simultaneously formed can realize the substrate of field effect transistor and the isolation of silicon substrate substrate, solves in some circuit design and needs source region to connect the application of certain potentials.
For solving the problems of the technologies described above, the technical scheme of the high withstand voltage field effect transistor domain structure of isolated form of the present invention is: comprise drain region, source region, drift region, drain region, drift region, source region polysilicon field plate and grid polycrystalline silicon and drain region polysilicon field plate, described source region polysilicon field plate, grid polycrystalline silicon and drain region polysilicon field plate are closed polygonized structure, and drain region polysilicon field plate is positioned at the inside of source region polysilicon field plate and grid polycrystalline silicon, described drain region is positioned at closed drain region polysilicon field plate, drift region, drain region is at source region polysilicon field plate and between grid polycrystalline silicon and drain region polysilicon field plate, source region is positioned at outside closed source region polysilicon field plate and grid polycrystalline silicon, described source region and drain region are positioned at drift region, source region and silicon substrate substrate are by separated drift regions,
Described source region polysilicon field plate and grid polycrystalline silicon are the U-shaped structure of inside and outside bilayer, and inside and outside bilayer is connected by circular arc field plate; Described drain region polysilicon field plate is also the U-shaped structure of inside and outside bilayer, and inside and outside bilayer is connected by circular arc field plate, and drain region polysilicon field plate is inside and outside source region polysilicon field plate and grid polycrystalline silicon between double-deck U-shaped structure;
The field effect transistor at circular arc place bottom the U-shaped internal layer being positioned at source region polysilicon field plate and grid polycrystalline silicon and drain region polysilicon field plate, the well region with the first conduction type is formed in described silicon substrate substrate, well region is drawn by the 3rd active area with the first conduction type, source is formed by second active area with the second conduction type, second active area is connected with the 3rd active area and forms source region, is formed with second doped region with the first conduction type below source region, the silicon substrate substrate with the first conduction type is formed the drift region that has second conduction type contrary with the first conduction type, described drift region comprises drift region, drain region, drift region, described drain region is drawn by first active area with the second conduction type and is formed drain region, generate in drift region, drain region and have an oxygen isolation, the below of field oxygen isolation forms first doped region with the first conduction type, a segment distance is had between first doped region and the second doped region, described drift region is positioned at below source region and drain region, one end of field oxygen isolation is positioned on the drift region below drain region, the other end is positioned on the drift region below source region, first doped region is positioned at outside the drift region below drain region away from the one end in drain region, and be connected with silicon substrate substrate, described source region is positioned at the inside of drift region, and well region and the second doped region are positioned at the drift region below source region, and pass through separated drift regions between silicon substrate substrate, the oxygen isolation below, field not injecting drift region is formed with multiple isolation pressure ring, described isolation pressure ring comprises the 3rd doped region with the first conduction type and the drift region with the second conduction type, and the 3rd doped region isolates with field oxygen and is connected, below drift region and to isolate between pressure ring be silicon substrate substrate.Spacing between described isolation pressure ring is 1um ~ 20um.
Be positioned at the U-shaped outer field field effect transistor of source region polysilicon field plate and grid polycrystalline silicon and drain region polysilicon field plate and except the field effect transistor of the U-shaped internal layer at circular arc place bottom U-shaped internal layer be:
The silicon substrate substrate with the first conduction type is formed the drift region that has second conduction type contrary with the first conduction type, described drift region comprises drift region, drain region, drift region, described drain region is drawn by first active area with the second conduction type and is formed drain region, generate in drift region, drain region and have an oxygen isolation, the below of field oxygen isolation forms first doped region with the first conduction type; The well region with the first conduction type is formed in described silicon substrate substrate, well region is drawn by the 3rd active area with the first conduction type, source is formed by second active area with the second conduction type, second active area is connected with the 3rd active area and forms source region, be formed with second doped region with the first conduction type below source region, the second doped region and field oxygen isolation under the first doped region between have a segment distance; Described source region is positioned at the inside of drift region, and well region and silicon substrate substrate are by separated drift regions.
Further, the oxygen isolation of described field is coated with source region polysilicon field plate above the one end in source region, described source region polysilicon field plate and grid polycrystalline silicon are that same polysilicon forms grid, its one end covers the first doped region on the region in source region, and the other end covers the second doped region on the region of drift region, drain region; The oxygen isolation of described field is coated with drain region polysilicon field plate above the one end in drain region, and described drain region polysilicon field plate is connected with the first active area by Metal field plate; Be provided with Metal field plate with Metal field plate at a distance of a segment distance place, described Metal field plate is connected with grid polycrystalline silicon.
Described first conduction type is P type, and the second conduction type is N-type, or described first conduction type is N-type, and the second conduction type is P type.
Beneficial effect of the present invention is:
1. the high withstand voltage field effect transistor of isolated form of the present invention can realize the substrate of field effect transistor and the substrate isolation of silicon substrate, and the current potential of the substrate of field effect transistor can not affect by the current potential of silicon substrate substrate, independently add current potential;
2. in domain structure of the present invention, utilize whole encirclement drain region, source region, and use circular sliding slopes around the corner, also increase multiple high withstand voltage isolation pressure ring, can provide far above the withstand voltage field effect transistor of height puncture withstand voltage, avoid this place's high-voltage outside, low pressure current potential is interior, the problem affecting puncture voltage concentrated by power line, ensures to bear height withstand voltage while reduction device area.
Accompanying drawing explanation
Below in conjunction with accompanying drawing and embodiment, the present invention is further detailed explanation:
Fig. 1 is the surface plate figure structure schematic representation of the high withstand voltage field effect transistor of existing non-isolation type;
Fig. 2 is the schematic cross-section of the high withstand voltage field effect transistor of non-isolation type at B-B place and C-C place in Fig. 1;
Fig. 3 is the schematic cross-section of the high withstand voltage field effect transistor of non-isolation type at A-A place in Fig. 1;
Fig. 4 is the surface plate figure structure schematic representation of the high withstand voltage field effect transistor of isolated form of the present invention;
Fig. 5 is the schematic cross-section of the high withstand voltage field effect transistor of isolated form that in Fig. 4, B '-B ' locates and C '-C ' locates;
Fig. 6 is the schematic cross-section of the high withstand voltage field effect transistor of isolated form that in Fig. 4, A '-A ' locates.
Embodiment
The high withstand voltage field effect transistor of isolated form of the present invention, as shown in Figure 5, P-type silicon substrate substrate 101 is formed the drift region 102 of N-type, described drift region 102 comprises drift region, drain region 203, drift region, described drain region 203 is drawn by the first active area 107 of N-type and is formed drain region 201, generate in drift region, drain region 203 and have an oxygen isolation 105, the below of field oxygen isolation 105 forms the first doped region 104 of P type, when drain region 201 adds high pressure, P type first doped region 104 provides the electronics neutralization of hole more easily and in drift region, drain region 203, produce depletion region to improve the withstand voltage of drain region 201.
The well region 103 of P type is formed in P-type silicon substrate substrate 101, well region 103 is drawn by the 3rd active area 108 of P type, source is formed by the second active area 106 of N-type, second active area 106 is connected with the 3rd active area 108 and forms source region 202, be formed with the second doped region 104a of P type below source region 202, the second doped region 104a and field oxygen are isolated between the first doped region 104 under 105 segment distance.
Described source region 202 is positioned at the inside of drift region 102, and well region 103 and P-type silicon substrate substrate 101 are isolated by N-type drift region 102.
Field oxygen isolation 105 is coated with source region polysilicon field plate 109 above the one end in source region 202, source region polysilicon field plate 109 and grid polycrystalline silicon 109a are that same polysilicon forms grid, its one end covers the first doped region 104 on the region in source region 202, and the other end covers the second doped region 104a on the region of drift region, drain region 203.
Field oxygen isolation 105 is coated with drain region polysilicon field plate 110 above the one end in drain region 201, and described drain region polysilicon field plate 110 is connected with the first active area 107 by Metal field plate 112.
Be provided with Metal field plate 113 with Metal field plate 111 at a distance of a segment distance place, described Metal field plate 113 is connected with grid polycrystalline silicon, both forms Metal field plate, again because with gate connected in parallel and reduce resistance.
The domain structure of the high withstand voltage field effect transistor of isolated form of the present invention, as shown in Figure 4, comprise drain region 201, source region 202, drift region, drain region 203, drift region 102, source region polysilicon field plate 109 and grid polycrystalline silicon 109a and drain region polysilicon field plate 110, described source region polysilicon field plate 109 and grid polycrystalline silicon 109a are the U-shaped structure of inside and outside bilayer, and inside and outside bilayer is connected by circular arc field plate; Described drain region polysilicon field plate 110 is also the U-shaped structure of inside and outside bilayer, and inside and outside bilayer is connected by circular arc field plate, and drain region polysilicon field plate 110 is inside and outside source region polysilicon field plate 109 and grid polycrystalline silicon 109a between double-deck U-shaped structure.Described drain region 201 is positioned at closed drain region polysilicon field plate 110, drift region, drain region 203 is at source region polysilicon field plate 109 and between grid polycrystalline silicon 109a and drain region polysilicon field plate 110, source region 202 is positioned at outside closed source region polysilicon field plate 109 and grid polycrystalline silicon 109a, described source region 202 and drain region 201 are positioned at drift region 102, and source region 202 and silicon substrate substrate 101 are isolated by drift region 102.
Wherein, bottom the U-shaped internal layer being positioned at source region polysilicon field plate 109 and grid polycrystalline silicon 109a and drain region polysilicon field plate 110, the structure of the field effect transistor at A '-A ' circular arc place is:
The well region 103 of P type is formed in described P-type silicon substrate substrate 101, well region 103 is drawn by the 3rd active area 108 of P type, source is formed by the second active area 106 of N-type, second active area 106 is connected with the 3rd active area 108 and forms source region 202, is formed with the second doped region 104a of P type below source region 202;
P-type silicon substrate substrate 101 is formed a N-type drift region 102, described drift region 102 comprises drift region, drain region 203, drift region, drain region 203 is drawn by the first active area 107 of N-type and is formed drain region 201, generate in drift region, drain region 203 and have an oxygen isolation 105, the below of field oxygen isolation 105 is formed between the first doped region, doped region 104, first 104 of P type and the second doped region 104a a segment distance.Described drift region 102 is positioned at below source region 202 and drain region 201, one end of field oxygen isolation 105 is positioned on the drift region 102 below drain region 201, the other end is positioned on the drift region 102 below source region 202, first doped region 104 is positioned at outside the drift region 102 below drain region 201 away from the one end in drain region 201, and is connected with silicon substrate substrate 101;
Described source region 202 is positioned at the inside of drift region 102, and well region 103 and the second doped region 104a are positioned at the drift region 102 below source region 202, and are isolated by drift region 102 between silicon substrate substrate 101;
Multiple isolation pressure ring 204 is formed below the field oxygen isolation 105 of not injecting drift region 102.Isolation pressure ring 204 comprises the 3rd doped region 104c of P type and the drift region of N-type, and the 3rd doped region 104c and field oxygen are isolated 105 and is connected, below drift region and to isolate between pressure ring 204 be silicon substrate substrate 101.Spacing between described isolation pressure ring 204 is 1um ~ 20um.
In the high withstand voltage field effect transistor of above-mentioned N-type, convert each implanted layer ionic type, the high withstand voltage field effect transistor of P type can be formed.
The high withstand voltage field effect transistor of isolated form of the present invention can realize the substrate of field effect transistor and the substrate isolation of silicon substrate, and the current potential of the substrate of field effect transistor can not affect by the current potential of silicon substrate substrate, independently add current potential; In domain structure of the present invention, utilize whole encirclement drain region, source region, and use circular sliding slopes around the corner, also increase multiple high withstand voltage isolation pressure ring, can provide far above the withstand voltage field effect transistor of height puncture withstand voltage, avoid this place's high-voltage outside, low pressure current potential is interior, the problem affecting puncture voltage concentrated by power line, ensures to bear height withstand voltage while reduction device area.
Above by specific embodiment to invention has been detailed description, but these are not construed as limiting the invention.Without departing from the principles of the present invention, those skilled in the art can make many distortion and improvement, and these also should be considered as protection scope of the present invention.
Claims (5)
1. the domain structure of the high withstand voltage field effect transistor of isolated form, it is characterized in that, comprise drain region (201), source region (202), drift region, drain region (203), drift region (102), source region polysilicon field plate (109) and grid polycrystalline silicon (109a) and drain region polysilicon field plate (110), described source region polysilicon field plate (109), grid polycrystalline silicon (109a) and drain region polysilicon field plate (110) are closed polygonized structure, and drain region polysilicon field plate (110) is positioned at the inside of source region polysilicon field plate (109) and grid polycrystalline silicon (109a), described drain region (201) is positioned at closed drain region polysilicon field plate (110), drift region, drain region (203) is positioned at source region polysilicon field plate (109) and between grid polycrystalline silicon (109a) and drain region polysilicon field plate (110), source region (202) is positioned at closed source region polysilicon field plate (109) and grid polycrystalline silicon (109a) outward, described source region (202) and drain region (201) are positioned at drift region (102), source region (202) and silicon substrate substrate (101) are isolated by drift region (102),
Described source region polysilicon field plate (109) and grid polycrystalline silicon (109a) are the U-shaped structure of inside and outside bilayer, and inside and outside bilayer is connected by circular arc field plate; Described drain region polysilicon field plate (110) is also the U-shaped structure of inside and outside bilayer, inside and outside bilayer is connected by circular arc field plate, and drain region polysilicon field plate (110) is positioned between the U-shaped structure of inside and outside bilayer of source region polysilicon field plate (109) and grid polycrystalline silicon (109a);
Bottom the U-shaped internal layer being positioned at source region polysilicon field plate (109) and grid polycrystalline silicon (109a) and drain region polysilicon field plate (110), the field effect transistor at circular arc place is:
The well region (103) with the first conduction type is formed in described silicon substrate substrate (101), well region (103) is drawn by the 3rd active area (108) with the first conduction type, source is formed by second active area (106) with the second conduction type, second active area (106) is connected with the 3rd active area (108) and forms source region (202), and source region (202) below is formed with second doped region (104a) with the first conduction type;
The upper formation one of silicon substrate substrate (101) with the first conduction type has the drift region (102) of second conduction type contrary with the first conduction type, described drift region (102) comprises drift region, drain region (203), drift region, described drain region (203) is drawn by first active area (107) with the second conduction type and is formed drain region (201), generate in drift region, drain region (203) and have oxygen isolation (105), the below of field oxygen isolation (105) forms first doped region (104) with the first conduction type, a segment distance is had between first doped region (104) and the second doped region (104a), described drift region (102) is positioned at source region (202) and drain region (201) below, one end of field oxygen isolation (105) is positioned on the drift region (102) of below, drain region (201), the other end is positioned on the drift region (102) of below, source region (202), first doped region (104) is positioned at the drift region (102) of below, drain region (201) outward away from the one end of drain region (201), and be connected with silicon substrate substrate (101),
Described source region (202) is positioned at the inside of drift region (102), well region (103) and the second doped region (104a) are positioned at the drift region (102) of below, source region (202), and are isolated by drift region (102) between silicon substrate substrate (101);
The below, field oxygen isolation (105) not injecting drift region (102) is formed with multiple isolation pressure ring (204), described isolation pressure ring (204) comprises the 3rd doped region (104c) with the first conduction type and the drift region with the second conduction type, described 3rd doped region (104c) isolates (105) and is connected with field oxygen, below drift region and be silicon substrate substrate (101) between isolation pressure ring (204).
2. the domain structure of the high withstand voltage field effect transistor of isolated form according to claim 1, it is characterized in that, be positioned at the U-shaped outer field field effect transistor of source region polysilicon field plate (109) and grid polycrystalline silicon (109a) and drain region polysilicon field plate (110) and except the field effect transistor of the U-shaped internal layer at circular arc place bottom U-shaped internal layer be:
There is in the upper formation one of the silicon substrate substrate (101) with the first conduction type the drift region (102) of second conduction type contrary with the first conduction type, described drift region (102) comprises drift region, drain region (203), drift region, described drain region (203) is drawn by first active area (107) with the second conduction type and is formed drain region (201), generate in drift region, drain region (203) and have oxygen isolation (105), the below of field oxygen isolation (105) forms first doped region (104) with the first conduction type;
The well region (103) with the first conduction type is formed in described silicon substrate substrate (101), well region (103) is drawn by the 3rd active area (108) with the first conduction type, source is formed by second active area (106) with the second conduction type, second active area (106) is connected with the 3rd active area (108) and forms source region (202), below, source region (202) is formed with second doped region (104a) with the first conduction type, second doped region (104a) and field oxygen are isolated between the first doped region (104) under (105) a segment distance,
Described source region (202) is positioned at the inside of drift region (102), and well region (103) and silicon substrate substrate (101) are isolated by drift region (102).
3. the domain structure of the high withstand voltage field effect transistor of isolated form according to claim 2, it is characterized in that, described field oxygen isolation (105) is coated with source region polysilicon field plate (109) above the one end in source region (202), described source region polysilicon field plate (109) and grid polycrystalline silicon (109a) are that same polysilicon forms grid jointly, its one end covers the first doped region (104) on the region in source region (202), and the other end covers the second doped region (104a) on the region of drift region, drain region (203);
Described field oxygen isolation (105) is coated with drain region polysilicon field plate (110) above the one end in drain region (201), and described drain region polysilicon field plate (110) is connected with the first active area (107) by Metal field plate (112);
Be provided with Metal field plate (113) with Metal field plate (111) at a distance of a segment distance place, described Metal field plate (113) is connected with grid polycrystalline silicon.
4. the domain structure of the high withstand voltage field effect transistor of isolated form according to claim 1 and 2, it is characterized in that, described first conduction type is P type, and the second conduction type is N-type, or described first conduction type is N-type, and the second conduction type is P type.
5. the domain structure of the high withstand voltage field effect transistor of isolated form according to claim 1, it is characterized in that, the spacing between described isolation pressure ring (204) is 1um ~ 20um.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201110340126.XA CN103094317B (en) | 2011-11-01 | 2011-11-01 | The domain structure of the high withstand voltage field effect transistor of isolated form |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201110340126.XA CN103094317B (en) | 2011-11-01 | 2011-11-01 | The domain structure of the high withstand voltage field effect transistor of isolated form |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN103094317A CN103094317A (en) | 2013-05-08 |
| CN103094317B true CN103094317B (en) | 2015-10-14 |
Family
ID=48206691
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201110340126.XA Active CN103094317B (en) | 2011-11-01 | 2011-11-01 | The domain structure of the high withstand voltage field effect transistor of isolated form |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN103094317B (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107482003A (en) * | 2016-06-08 | 2017-12-15 | 中芯国际集成电路制造(上海)有限公司 | Domain structure, transistor and its manufacture method of transistor |
Families Citing this family (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104465722B (en) * | 2014-12-09 | 2017-06-06 | 上海华虹宏力半导体制造有限公司 | High-voltage isolating ring structure |
| CN107316903A (en) * | 2016-04-26 | 2017-11-03 | 中芯国际集成电路制造(上海)有限公司 | UHV LDMOS devices |
| CN112271210B (en) * | 2020-10-22 | 2023-04-21 | 吉林华微电子股份有限公司 | Semiconductor power and method for manufacturing the same |
| CN112909083B (en) * | 2021-02-26 | 2023-08-22 | 上海华虹宏力半导体制造有限公司 | High-voltage JFET device structure for improving withstand voltage reliability and manufacturing method thereof |
| CN113851521B (en) * | 2021-08-20 | 2023-08-18 | 上海华虹宏力半导体制造有限公司 | High-voltage field effect transistor structure for improving on-resistance characteristic and manufacturing method thereof |
| CN113948571B (en) * | 2021-10-18 | 2023-08-25 | 上海华虹宏力半导体制造有限公司 | Semiconductor structure and forming method thereof |
Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5040045A (en) * | 1990-05-17 | 1991-08-13 | U.S. Philips Corporation | High voltage MOS transistor having shielded crossover path for a high voltage connection bus |
| CN2773909Y (en) * | 2005-01-18 | 2006-04-19 | 崇贸科技股份有限公司 | Semiconductor field-effect transistor of side-diffusion metal oxide |
| CN1926690A (en) * | 2004-01-16 | 2007-03-07 | 崇贸科技股份有限公司 | Isolated high-voltage LDMOS transistor having a split well structure |
| CN101789041A (en) * | 2010-01-28 | 2010-07-28 | 上海宏力半导体制造有限公司 | Element layout capable of increasing layout efficiency and integration degree |
| CN201540894U (en) * | 2009-11-03 | 2010-08-04 | 苏州远创达科技有限公司 | LDMOS device of multiple field plates |
| CN102097471A (en) * | 2009-12-04 | 2011-06-15 | 美格纳半导体有限会社 | Semiconductor device |
-
2011
- 2011-11-01 CN CN201110340126.XA patent/CN103094317B/en active Active
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5040045A (en) * | 1990-05-17 | 1991-08-13 | U.S. Philips Corporation | High voltage MOS transistor having shielded crossover path for a high voltage connection bus |
| CN1926690A (en) * | 2004-01-16 | 2007-03-07 | 崇贸科技股份有限公司 | Isolated high-voltage LDMOS transistor having a split well structure |
| CN2773909Y (en) * | 2005-01-18 | 2006-04-19 | 崇贸科技股份有限公司 | Semiconductor field-effect transistor of side-diffusion metal oxide |
| CN201540894U (en) * | 2009-11-03 | 2010-08-04 | 苏州远创达科技有限公司 | LDMOS device of multiple field plates |
| CN102097471A (en) * | 2009-12-04 | 2011-06-15 | 美格纳半导体有限会社 | Semiconductor device |
| CN101789041A (en) * | 2010-01-28 | 2010-07-28 | 上海宏力半导体制造有限公司 | Element layout capable of increasing layout efficiency and integration degree |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107482003A (en) * | 2016-06-08 | 2017-12-15 | 中芯国际集成电路制造(上海)有限公司 | Domain structure, transistor and its manufacture method of transistor |
| CN107482003B (en) * | 2016-06-08 | 2020-03-13 | 中芯国际集成电路制造(上海)有限公司 | Layout structure of transistor, transistor and manufacturing method thereof |
Also Published As
| Publication number | Publication date |
|---|---|
| CN103094317A (en) | 2013-05-08 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN103094317B (en) | The domain structure of the high withstand voltage field effect transistor of isolated form | |
| CN100421256C (en) | SOI LIGBT device unit of integrated ESD diode | |
| CN104518031B (en) | Combinable semiconductor devices with high reliability | |
| CN102130168B (en) | Isolated LDMOS (Laterally Diffused Metal Oxide Semiconductor) device and manufacturing method thereof | |
| US7626231B1 (en) | Integrated trench MOSFET and junction barrier schottky rectifier with trench contact structures | |
| JP5472309B2 (en) | Semiconductor device | |
| US20160104766A1 (en) | Power Semiconductor Device with Source Trench and Termination Trench Implants | |
| US20140103416A1 (en) | Semiconductor device having esd protection structure and associated method for manufacturing | |
| US9818743B2 (en) | Power semiconductor device with contiguous gate trenches and offset source trenches | |
| JP2013065749A (en) | Semiconductor device | |
| JP6618615B2 (en) | Laterally diffused metal oxide semiconductor field effect transistor | |
| CN105070756A (en) | Superhigh-voltage LDMOS device structure | |
| CN105679820A (en) | Jfet and manufacturing method thereof | |
| CN104659090B (en) | LDMOS device and manufacture method | |
| CN109755238B (en) | Super junction power device with split-gate structure | |
| CN109755310B (en) | Power transistor with split-gate structure | |
| CN106129105A (en) | Groove power MOSFET and manufacture method | |
| CN104659091A (en) | Ldmos device and manufacturing method thereof | |
| WO2021232806A1 (en) | Trench gate metal oxide semiconductor field effect transistor and manufacturing method therefor | |
| CN107819026B (en) | LDMOS device | |
| CN105140289A (en) | N-type LDMOS device and technical method thereof | |
| CN105679831B (en) | Horizontal proliferation field-effect transistor and its manufacturing method | |
| CN103091533B (en) | Current sampling circuit achieved by laterally diffused metal oxide semiconductor (LDMOS) devices | |
| CN102386227B (en) | Both-way surface field subdued drain electrode isolation double diffused drain metal-oxide -semiconductor field effect transistor (DDDMOS) transistor and method | |
| CN103094319A (en) | Pinch-off voltage reducing structure of dual-channel high voltage junction field effect transistor (FET) and manufacturing method thereof |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| ASS | Succession or assignment of patent right |
Owner name: SHANGHAI HUAHONG GRACE SEMICONDUCTOR MANUFACTURING Free format text: FORMER OWNER: HUAHONG NEC ELECTRONICS CO LTD, SHANGHAI Effective date: 20140108 |
|
| C41 | Transfer of patent application or patent right or utility model | ||
| COR | Change of bibliographic data |
Free format text: CORRECT: ADDRESS; FROM: 201206 PUDONG NEW AREA, SHANGHAI TO: 201203 PUDONG NEW AREA, SHANGHAI |
|
| TA01 | Transfer of patent application right |
Effective date of registration: 20140108 Address after: 201203 Shanghai city Zuchongzhi road Pudong New Area Zhangjiang hi tech Park No. 1399 Applicant after: Shanghai Huahong Grace Semiconductor Manufacturing Corporation Address before: 201206, Shanghai, Pudong New Area, Sichuan Road, No. 1188 Bridge Applicant before: Shanghai Huahong NEC Electronics Co., Ltd. |
|
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant |