CN101789041A - Element layout capable of increasing layout efficiency and integration degree - Google Patents
Element layout capable of increasing layout efficiency and integration degree Download PDFInfo
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- CN101789041A CN101789041A CN201010102424A CN201010102424A CN101789041A CN 101789041 A CN101789041 A CN 101789041A CN 201010102424 A CN201010102424 A CN 201010102424A CN 201010102424 A CN201010102424 A CN 201010102424A CN 101789041 A CN101789041 A CN 101789041A
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Abstract
The invention provides an element layout capable of increasing layout efficiency and integration degree. In the prior art, elements are separated from one another for a certain distance in order to be insulated from one another, and as a result, the integration degree is low due to a complex design rule and the large insulating distance between the elements. Aimed at an isolated LDMOS, the element layout arranges a first isolating structure around the drain of the isolated LDMOS; aimed at a plurality of LDMOSs connected in parallel, the element layout arranges a second isolating structure around the drains of all the LDMOSs connected in parallel; and the diameters of both the first isolating structure and the second isolating structure are the distance from the center of the surrounded LDMOS drain to the center of the LDMOS source. The invention does not need to design a specific design rule for the isolating structures any more, consequently, the layout process is simplified, the layout efficiency is increased, moreover, the distance between the LDMOSs is reduced, and the integration degree of the elements is increased.
Description
Technical field
The present invention relates to the semiconductor design field, relate in particular to a kind of element layout that improves layout efficiency and integrated level.
Background technology
In the semiconductor design process, after completion logic and circuit design, just can carry out layout design (Layout Design).Layout design is the process that the circuit diagram that will design changes into concrete physical layout, its according to the logical and circuit function require, technological level requires and design rule is designed the reticle pattern of using for photoetching.Need define a lot of design rules during layout design, for example the distance (abbreviation device pitch) between the power MOS pipe source electrode of different rated voltages and the drain electrode is different or the varying in size etc. of the power MOS pipe drift region of different rated voltages.
When carrying out layout design, for the power MOS pipe that is operated in high pressure or high frequency, it is particularly important that its insulating Design seems.Now Chang Yong power MOS pipe is LDMOS transistor (Lateral Diffused Medal Oxide Semiconductor; Be called for short LDMOS), LDMOS be used in usually drive or on-off circuit on, it can isolate the single use use that also can a plurality ofly be connected in parallel.The device that comprises isolated LDMOS and/or a plurality of LDMOS that are connected in parallel is when carrying out layout design, need the isolation design that insulate between each included LDMOS and between LDMOS and other member, prior art usually by separate certain distance realize between LDMOS and and other member between the insulation isolation.
Above-mentioned by separate that certain distance realizes between LDMOS and and other member between insulation isolate the following problem that exists: at first, need define design rule at isolation distance, when the drain voltage of LDMOS is inequality, need at the different different isolation distances of drain voltage design, increase the complexity of layout design, reduced layout efficiency; Moreover, reach LDMOS and the spaced apart bigger distance of other member between all LDMOS and realize the insulation isolation, can reduce the integrated level of device.
Therefore, how to provide a kind of efficient that improves the element layout of layout efficiency and integrated level with raising layout design and Butut, and effectively improve the integrated level of device, become the technical matters that industry needs to be resolved hurrily.
Summary of the invention
The object of the present invention is to provide a kind of element layout that improves layout efficiency and integrated level, can improve layout efficiency, and effectively improve the integrated level of device by described domain.
The object of the present invention is achieved like this: a kind of element layout that improves layout efficiency and integrated level, this device comprises isolated LDMOS, this element layout comprises first isolation structure around the drain electrode of this isolated LDMOS, the ring of this first isolation structure directly be around the drain distance at center to source electrode center of LDMOS.
In the element layout of above-mentioned improved layout efficiency and integrated level, this first isolation structure comprises the parallel band that is set in parallel in the drain electrode both sides and is connected the parallel band end and the curved end of parallel band formation closed-loop.
The present invention also provides a kind of element layout that improves layout efficiency and integrated level, this device comprises a plurality of LDMOS that are connected in parallel, this element layout comprises second isolation structure around the drain electrode of all a plurality of LDMOS that are connected in parallel, the ring of this second isolation structure directly be around the distance at LDMOS drain electrode center to source electrode center.
In the element layout of above-mentioned improved layout efficiency and integrated level, this second isolation structure comprises the parallel band and the curved end that is looped around each drain electrode end and is connected successively in the drain electrode outside that is set in parallel in outermost two LDMOS among a plurality of LDMOS that are connected in parallel, and these a plurality of curved ends and parallel band form closed-loop.
In the element layout of above-mentioned improved layout efficiency and integrated level, these a plurality of LDMOS that are connected in parallel have identical rated operational voltage, and its drain electrode center is identical to the distance at source electrode center.
And in the prior art by between the included LDMOS of device and the spaced apart certain distance of LDMOS and other member realizes between LDMOS and and other member between the insulation isolation, thereby cause the layout rules complexity, layout efficiency is low to be compared with the device integrated level is low, the present invention is directed to first isolation structure of isolated LDMOS setting around the drain electrode of this isolated LDMOS, at second isolation structure of a plurality of LDMOS settings that are connected in parallel around the drain electrode of all a plurality of LDMOS that are connected in parallel, the ring of this first isolation structure and second isolation structure directly be around the distance at LDMOS drain electrode center to source electrode center, so need not to formulate independent design rule at isolation structure again, simplified the Butut process and improved layout efficiency; The part of device is served as isolation structure in addition, has reduced the distance between LDMOS, has improved the integrated level of device.
Description of drawings
The element layout that improves layout efficiency and integrated level of the present invention is provided by following embodiment and accompanying drawing.
Fig. 1 is the domain synoptic diagram of first embodiment of the element layout that improves layout efficiency and integrated level of the present invention;
Fig. 2 is the domain synoptic diagram of second embodiment of the element layout that improves layout efficiency and integrated level of the present invention.
Embodiment
Below will be described in further detail the element layout that improves layout efficiency and integrated level of the present invention.
Referring to Fig. 1, it is the domain synoptic diagram of first embodiment of the element layout that improves layout efficiency and integrated level of the present invention, as shown in the figure, the element layout that improves layout efficiency and integrated level of the present invention comprises isolated LDMOS10, LDMOS10 has grid G 1, source S 1 and drain D 1, described element layout also comprises first isolation structure 20 around drain D 1, the ring of described first isolation structure 20 footpath R1 be around the distance L 1 at LDMOS10 drain D 1 center to source S 1 center.Described first isolation structure 20 comprises the parallel band 200 that is set in parallel in the drain electrode both sides and is connected parallel band terminal 200 and the curved end 202 of parallel band 200 formation closed-loops.So can guarantee the insulation isolation between LDMOS10 and other devices, other first isolation structure 20 is as the part of LDMOS10, and it need not to make in addition when carrying out the subsequent technique making again.
In the present embodiment, described LDMOS10 is N type LDMOS.In other embodiments of the invention, described LDMOS10 can be P type LDMOS.
The distance L 1 at described drain D 1 center to source S 1 center can be adjusted accordingly according to the concrete situation (for example drain voltage) of LDMOS10 and process conditions etc.
Referring to Fig. 2, it is the domain synoptic diagram of second embodiment of the element layout that improves layout efficiency and integrated level of the present invention, as shown in the figure, the element layout that improves layout efficiency and integrated level of the present invention comprises a plurality of LDMOS12 that are connected in parallel and around second isolation structure 22 of the drain D 2 of all a plurality of LDMOS12 that are connected in parallel, the ring footpath R2 of described second isolation structure 22 be around the drain distance (not shown) at center to source electrode center of LDMOS.Described second isolation structure 22 comprises the parallel band 220 and the curved end 222 that is looped around each drain D 2 end and is connected successively in the drain electrode outside that is set in parallel in outermost two LDMOS12 among a plurality of LDMOS12 that are connected in parallel, and described a plurality of curved ends 222 form closed-loops with parallel band 220.Described a plurality of LDMOS12 that is connected in parallel has identical rated operational voltage, and its drain D 2 centers are identical to the distance at source electrode center, and described distance is adjusted accordingly with the concrete situation of LDMOS12 and process conditions etc.
In sum, the present invention is directed to isolated LDMOS first isolation structure around the drain electrode of described isolated LDMOS is set, at second isolation structure of a plurality of LDMOS settings that are connected in parallel around the drain electrode of all a plurality of LDMOS that are connected in parallel, the ring of described first isolation structure and second isolation structure directly be around the distance at LDMOS drain electrode center to source electrode center, so need not to design independent design rule at isolation structure again, simplified the Butut process and improved layout efficiency; The part of device is served as isolation structure in addition, has reduced the distance between LDMOS, has improved the integrated level of device.
Claims (5)
1. element layout that can improve layout efficiency and integrated level, this device comprises isolated LDMOS, it is characterized in that, this element layout comprises first isolation structure around the drain electrode of this isolated LDMOS, the ring of this first isolation structure directly be around the drain distance at center to source electrode center of LDMOS.
2. the element layout that improves layout efficiency and integrated level as claimed in claim 1 is characterized in that, this first isolation structure comprises the parallel band that is set in parallel in the drain electrode both sides and is connected the parallel band end and the curved end of parallel band formation closed-loop.
3. element layout that can improve layout efficiency and integrated level, this device comprises a plurality of LDMOS that are connected in parallel, it is characterized in that, this element layout comprises second isolation structure around the drain electrode of all a plurality of LDMOS that are connected in parallel, the ring of this second isolation structure directly be around the distance at LDMOS drain electrode center to source electrode center.
4. the element layout that improves layout efficiency and integrated level as claimed in claim 3, it is characterized in that, this second isolation structure comprises the parallel band and the curved end that is looped around each drain electrode end and is connected successively in the drain electrode outside that is set in parallel in outermost two LDMOS among a plurality of LDMOS that are connected in parallel, and these a plurality of curved ends and parallel band form closed-loop.
5. the element layout that improves layout efficiency and integrated level as claimed in claim 3 is characterized in that, these a plurality of LDMOS that are connected in parallel have identical rated operational voltage, and its drain electrode center is identical to the distance at source electrode center.
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| Application Number | Priority Date | Filing Date | Title |
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| CN201010102424A CN101789041A (en) | 2010-01-28 | 2010-01-28 | Element layout capable of increasing layout efficiency and integration degree |
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| Application Number | Priority Date | Filing Date | Title |
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| CN201010102424A CN101789041A (en) | 2010-01-28 | 2010-01-28 | Element layout capable of increasing layout efficiency and integration degree |
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102751326A (en) * | 2011-04-18 | 2012-10-24 | 汉磊科技股份有限公司 | Power LDMOS device and high voltage device |
| CN103094317A (en) * | 2011-11-01 | 2013-05-08 | 上海华虹Nec电子有限公司 | Isolation type high voltage resistance field effect transistor (FET) and layout structure |
| CN105514102A (en) * | 2014-10-17 | 2016-04-20 | 中芯国际集成电路制造(上海)有限公司 | Layout structure, semiconductor device and electronic apparatus |
| WO2022142370A1 (en) * | 2020-12-31 | 2022-07-07 | 无锡华润上华科技有限公司 | Semiconductor device |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1925170A (en) * | 2005-08-31 | 2007-03-07 | 夏普株式会社 | Lateral double-diffused field effect transistor and integrated circuit having same |
| US20080237739A1 (en) * | 2007-03-26 | 2008-10-02 | Fujitsu Limited | Method of manufacturing a semiconductor device and a semiconductor device |
| CN101465378A (en) * | 2007-12-20 | 2009-06-24 | 夏普株式会社 | Semiconductor device and its manufacturing method |
| CN101499102A (en) * | 2008-02-02 | 2009-08-05 | 北京芯慧同用微电子技术有限责任公司 | Layout designing method and apparatus |
-
2010
- 2010-01-28 CN CN201010102424A patent/CN101789041A/en active Pending
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1925170A (en) * | 2005-08-31 | 2007-03-07 | 夏普株式会社 | Lateral double-diffused field effect transistor and integrated circuit having same |
| US20080237739A1 (en) * | 2007-03-26 | 2008-10-02 | Fujitsu Limited | Method of manufacturing a semiconductor device and a semiconductor device |
| CN101465378A (en) * | 2007-12-20 | 2009-06-24 | 夏普株式会社 | Semiconductor device and its manufacturing method |
| CN101499102A (en) * | 2008-02-02 | 2009-08-05 | 北京芯慧同用微电子技术有限责任公司 | Layout designing method and apparatus |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102751326A (en) * | 2011-04-18 | 2012-10-24 | 汉磊科技股份有限公司 | Power LDMOS device and high voltage device |
| CN103094317A (en) * | 2011-11-01 | 2013-05-08 | 上海华虹Nec电子有限公司 | Isolation type high voltage resistance field effect transistor (FET) and layout structure |
| CN103094317B (en) * | 2011-11-01 | 2015-10-14 | 上海华虹宏力半导体制造有限公司 | The domain structure of the high withstand voltage field effect transistor of isolated form |
| CN105514102A (en) * | 2014-10-17 | 2016-04-20 | 中芯国际集成电路制造(上海)有限公司 | Layout structure, semiconductor device and electronic apparatus |
| WO2022142370A1 (en) * | 2020-12-31 | 2022-07-07 | 无锡华润上华科技有限公司 | Semiconductor device |
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