CN103035603A - 具有等体积的接触凸块的共面阵列的同步降压转换器 - Google Patents

具有等体积的接触凸块的共面阵列的同步降压转换器 Download PDF

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Publication number
CN103035603A
CN103035603A CN2012103679829A CN201210367982A CN103035603A CN 103035603 A CN103035603 A CN 103035603A CN 2012103679829 A CN2012103679829 A CN 2012103679829A CN 201210367982 A CN201210367982 A CN 201210367982A CN 103035603 A CN103035603 A CN 103035603A
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carrier
fet
projection
module according
area
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CN103035603B (zh
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胡安·A·赫布佐默
奥斯瓦尔多·J·洛佩斯
乔纳森·A·诺奎尔
达维德·豪雷吉
马克·E·格拉纳亨
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Texas Instruments Inc
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Texas Instruments Inc
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Abstract

本发明涉及一种经封装电力供应模块(100)，其包含具有第一电力场效应晶体管FET的芯片(110)及具有以导电方式并排附接到导电载体(130)上的第二FET的第二芯片(120)，所述晶体管具有具第一面积(210)的接合垫，且所述载体具有具小于所述第一面积的第二面积(230)的接合垫。附接到所述晶体管接合垫的导电凸块(114、115、124、125)及附接到所述载体接合垫的导电凸块(126)具有相等的体积且是共面的(150)，所述晶体管垫上的所述凸块具有第一高度，且所述载体垫上的所述凸块具有大于所述第一高度的第二高度。

Description

具有等体积的接触凸块的共面阵列的同步降压转换器
技术领域
本发明大体上涉及半导体装置及工艺的领域，且更明确来说，涉及具有等体积的接触凸块的共面阵列的薄、热高效电力供应模块的系统结构及制造方法。
背景技术
DC/DC电力供应电路在流行的电力切换装置家族中，尤其是切换模式电力供应电路的类别。尤其适合新出现的电力递送要求的是具有串联连接且通过共用开关节点耦合在一起的两个电力MOS场效晶体管(FET)的同步降压转换器。在降压转换器中，控制FET芯片连接在供应电压VIN与LC输出滤波器之间，且同步FET芯片连接在LC输出滤波器与接地电位之间。控制FET芯片及同步FET芯片的栅极连接到包括用作所述转换器的驱动器的集成电路(IC)的半导体芯片；所述驱动器又连接到控制器IC。
对于许多今天的电力切换装置来说，电力MOSFET的芯片及驱动器及控制器IC的芯片组装为个别组件。所述装置使用金属引线框，其通常具有由引线围绕的矩形垫。所述垫用作用于附接半导体芯片的衬底，且引线用作输出端子。引线通常在没有悬臂延伸的情况下成形，且以方形扁平无引脚(QFN)或小外形无引脚(SON)装置的方式布置。从芯片到引线的电连接可以若干方式提供。在一个装置家族中，所述连接通过接合导线来提供，归因于其长度及电阻，所述导线可将显著的寄生电感引入到电力电路中。每一组合件通常以塑料包封封装，且经封装的组件用作用于电力供应系统的板组合件的离散建置块。在其它装置家族中，金属线夹代替许多或所有连接导线。相比于导线，这些线夹较宽，且引入较小的寄生电感的电阻。
在其它电力切换装置中，电力MOSFET芯片及驱动器及控制器IC在引线框垫上并排水平组装，所述引线框垫又在所有四个侧上由用作装置输出端子的引线围绕。所述引线以QFN或SON样式定形。芯片与引线之间的电连接通过接合导线提供。所述装置以塑料包封封装。
这些家族的装置为若干毫米厚。为将装置厚度降低到约1.5mm，另一近来引入的电力MOSFET组合件通过提供具有分成用于电力芯片(其中第一及第二端子在一个芯片侧上，且第三端子在相对的芯片侧上)的两个部分的组装垫的引线框来避免连接线夹及导线接合。所述芯片倒装(使用金属凸块或从注射器分配的焊膏)到引线框垫上，使得第一端子接触一个垫部分，且第二端子接触另一个垫部分。两个引线框部分都使边缘被弯曲，使得在倒装之后，所述边缘与第三端子共面；所有三个MOSFET端子可因此附接到印刷电路板(PCB)。在此附接之后，引线框垫远离PCB，但因为其分成用作两个芯片端子的两部分，所以散热片不能附接到所述垫。
在又一近来引进的电力MOSFET组合件中，通过提供具有分成用于电力芯片(其中第一及第二端子在一个裸片侧上，且第三端子在相对裸片侧上)的两个部分的组装垫的引线框来避免连接线夹及导线接合。所述芯片倒装(使用金属凸块或从注射器分配的焊膏)到引线框垫上，使得第一端子接触一个垫部分，且第二端子接触另一垫部分。两个引线框部分都使边缘被弯曲，使得在倒装之后，所述边缘变成与第三端子共面；所有三个MOSFET端子可因此附接到印刷电路板(PCB)。在此附接之后，所述引线框垫远离PCB，但因为其分成用作两个裸片端子的两部分，所以散热片不能附接到所述垫。
在又一近来引进的电力MOSFET封装中，引线框具备分成两部分的平坦垫，其可附接到PCB。电力芯片的第一及第二端子附接到这些垫部分。第三芯片端子(远离引线框垫)与金属线夹接触，所述金属线夹具有朝向引线框的引线弯曲的边缘，从而允许所有三个芯片端子组装在PCB上。所述芯片由足够厚以允许散热片附接到所述芯片以冷却第三芯片端子的金属制成。所述MOSFET封装因此具有三层结构的引线框-芯片-线夹。
另一近来提出的电力MOSFET封装通过没有导线接合或线夹的封装结构来将装置厚度降低到1.0到1.5mm。所述结构要求引线框垫经半蚀刻以形成较厚部分及较薄部分。这意味着，所述引线框不能被冲压。在芯片组装过程期间，垫的共面侧朝下。作为另一要求，需要开发特殊的倒装芯片设备，其能够从底部附接芯片；FET源极附接到较厚垫部分，且FET栅极附接到较薄垫部分。此较薄部分在包封过程期间用封装化合物覆盖。此外，需要单独的零部件来推平具有FET漏极的封装端子，且必须沉积且图案化额外金属层以模拟标准QFN占用面积。
发明内容
申请人认识到市场中广泛分布的电力转换器应用(例如，手持产品、膝上型产品、汽车产品及医疗产品)需要用于MOS场效晶体管(FET)及转换器的封装，所述封装是极薄的(小于1.5mm)，但仍提供接近理论最大值的热效率及电效率。此外，不断上升的成本压力要求封装部件及工艺步骤的根本减少。申请人发现，三层结构的现有MOSFET封装(组合引线框、芯片及线夹的厚度)对于许多新出现的应用来说太厚。此外，这些装置常常负担有寄生电阻及寄生热阻，且因此达不到最大热效率及电效率。作为对消费者友好用途的额外新出现的需要，申请人认识到，电力FET封装应优选地允许到印刷电路板(PCB)的直接实施，而免去首先修改占用面积的麻烦。
当申请人发现并排附接到低成本、导电平坦载体上且可通过共面导电凸块连接到PCB的双层组装的两个FET芯片时，申请人解决了降低高电力MOSFET封装的总厚度的问题及最小化制造成本的问题。所得封装使所有端子位于载体的一个侧上且提供相对的载体侧以用于附接散热片。所述导电凸块优选地源自等体积的焊料球，其已被喷射到针对所述FET展现第一面积且针对载体展现较小的第二面积的接合垫上。选择所述垫面积使得在焊料回流之后，所得的凸起凸块表面的顶端与所述垫面积成反比且位于共用平面(凸块是共面的)中。因为包封是任选的，所以可消除模制过程。
申请人进一步发现，没有引线框及线夹的组装降低寄生电阻及电感，从而导致效率及速度增加。作为意料之外的益处，申请人发现，没有延伸线夹及弯曲边缘的封装降低开关节点电压的恼人“振铃”。
在示范性实施例中，如由载体的大小决定，FET电力切换封装具有5mm的长度及2.5mm的宽度。所述载体具有0.25mm的厚度。由焊接掩模材料围绕的载体接合垫具有约0.07mm2的面积，如由直径为0.3mm的圆形所提供。第一FET(同步或低侧晶体管)具有2.48×2.1mm的尺寸、0.05mm的厚度且漏极向下以导电方式附接在载体上；附接层的厚度为0.02mm。用于源极及栅极的暴露接合垫具有约0.18mm2的面积，如由直径为0.48mm的圆形所提供。第二FET(控制或高侧晶体管)具有1.05×2.1mm的尺寸、0.05mm的厚度且邻近于第一FET而源极向下以导电方式附接在载体上；同样，附接层的厚度为0.02mm。用于漏极及栅极的暴露接合垫具有约0.18mm2的面积，如由直径为0.48mm的圆形所提供。
一个技术优势是，可选择用于同步FET及控制FET的接合垫位置以配置所建立的占用面积。或者，所述垫可以由列及行形成的有序图案排列。
使用低成本喷射技术将直径为0.3mm的焊料球(举例来说，锡/银合金)(产生约0.014mm3的体积)沉积在每一接合垫上。此后，回流所述焊料球，使得经液化的焊料覆盖垫区域且通过表面张力形成具有凸起表面及顶端的凸块。所述顶端在垫区域上的高度与所述垫区域的直径成反比，因为所有凸块具有相等的焊料体积。对于上文引述的垫直径来说，FET垫上的凸块高度为0.15mm，载体垫上的凸块高度为0.22mm。凸块高度之间的0.07mm的差异补偿芯片厚度(0.05mm)与附接层(厚度(0.02mm)的和。由于不同的凸块高度，所有凸块顶端沉积的共用平面上；所述凸块是共面的。在将经封装的电力供应模块组装到PBC之前，模块的厚度为0.47mm，即，载体厚度(0.25mm)与载体焊料凸块高度(0.22mm)的和。
一个技术优势是，与经组装的FET相对的载体侧的暴露金属对于散热片的附接是可用的。在散热片附接到所述载体的情况下，示范性模块可处置上至35A的电流。
附图说明
图1为根据本发明的实施例的封装电力供应模块的底侧的透视图，其说明组装在载体上的两个电力FET芯片。芯片及载体在不同面积的接触垫上具有等体积但不同高度的共面焊料凸块。所述FET芯片具有相同的厚度。
图2描绘图1的模块的顶视图。虚线指示图3中展示的模块切除的位置。
图3说明垂直通过图2的视图的平面的横截面，其揭示作为本发明的实施例的电力供应模块的结构。
图4为针对等体积的焊料凸块展示焊料凸块高度(从接触垫到凸起凸块表面的顶端测量)与所述接触垫的直径(由不可焊接涂层的开口决定)之间的关系的图表。所述关系的参数为凸块体积(0.014mm3)。所述关系允许所述凸块顶端定位在共用平面上。
图5为现有技术中的具有并排组装的两个电力场效晶体管(FET)的同步降压转换器的电路图。
图6描绘根据本发明的具有并排组装的两个FET的同步降压转换器的电路图。
具体实施方式
图1、2及3说明本发明的实例实施例，即，同步降压转换器的通常表示为100的经封装建置块。第一半导体FET芯片110及第二半导体FET芯片120组装在载体板130上。如图1展示，所述组装是并排的且紧密接近。组装层(表示为140)具有厚度141(优选地为约0.02mm)，且是导电且导热的。在此实例中，芯片110具有比芯片120大的面积，因为芯片110包括所述模块的同步(低侧)晶体管(同步FET)，而芯片120包括所述模块的控制(高侧)晶体管(控制FET)。在图1的实例中，芯片110及芯片120具有相等的厚度113，优选约0.05mm；在其它实施例中，芯片110及芯片120可具有不同的厚度，且值可大于或小于0.05mm。
就同步FET及控制FET的物理面积与有源面积的比较来说，应注意，同步降压转换器的工作循环决定控制FET所需的有源面积相对于同步FET所需的有源面积的比率，因为接通状态的电阻RON与有源芯片面积成反比。如果所预期的工作循环在大多数时间(＜0.5)是低的，那么控制FET在大多数操作期间是关断的且不传导；且同步FET在大多数循环时间是传导的。为降低降压转换器的传导损失(PLOSS＝I2RON)，使同步FET芯片110具有等于或大于控制FET芯片120的有源面积的有源面积将会是有利的。因此，同步芯片110还具有等于或大于控制芯片120的物理面积的物理面积。
在图1、2及3的实例中，第一电力FET110具有2.48mm的长度111及2.1mm的宽度112。第二电力FET120具有1.05mm的长度121及与第一晶体管110相同的2.1mm的宽度112。在示范性转换器100中，第一FET使其漏极以导电方式附接到载体130，且第二FET使其源极以导电方式附接到载体130。晶体管110及120都具有由附接凸块填充的具有第一面积的多个接合垫。在转换器100的实例中，所述第一接合垫面积为约0.18mm2，如由直径为0.48mm的圆形所提供。圆形FET垫形状及面积在图2中表示为210，FET垫直径在图3在表示为310。载体130具有具小于所述第一面积的第二面积的多个接合垫，其也由附接凸块填充。在转换器100的实例中，第二接合面积为约0.07mm2，如由直径为0.3mm的圆形所提供。所述圆形载体垫形状及面积在图2中表示为230，所述载体垫直径在图3中表示为330。
所述接合垫区域的周界由绝缘、不可焊接涂层(例如焊接掩模)中的开口决定，所述涂层围绕所述接合垫(所述涂层在图2中由阴影表示，且在图3中表示为301)。在另一方面，所述接合垫区域使表面经调整处理，使得可附接导电材料(例如，导电粘合剂及焊料)；作为实例，所述垫区域可具有与焊料的亲和性(例如，清洁度)且因此可由焊料均匀地打湿。
所有导电凸块具有相同的体积。在图1、2及3的实例中，凸块的体积为约0.014mm3，在焊接的实例中，这可通过回流直径为0.3mm的球形焊料球来实现。
载体130具有长度131及宽度132；载体130的厚度表示为333。在图1的实例中，长度131为5.0mm，且宽度132为2.5mm，且厚度133为约0.25mm。板130是导电且导热、机械坚硬且优选由铜或铜合金制成；或者使用铝、钢或其它金属合金。载体130具有表面130a(其优选具有可焊接冶金配置以促进芯片110及120的组装)，及平行表面130b(见图3)。两个表面优选都是平坦且光滑的。在一些实施例中，表面130b经配置以使得其促进热量传递到环境中；如在图3中由示范性虚线350指示，当表面130b适于附接散热片时，这是一个技术优势。
如上文陈述，晶体管110及120具有具第一面积的多个接合垫，其由导电凸块填充以用于附接到外部部件(例如，PCB)，且载体130具有具小于所述第一面积的第二面积的多个接合垫，其也由导电凸块填充。对于同步FET110来说，用于晶体管源极端子的导电凸块表示为114；源极凸块的填充由虚线119描绘。用于晶体管栅极端子的凸块表示为115。对于控制FET120来说，用于晶体管漏极端子的导电凸块表示为124；漏极凸块的填充由虚线129描绘。用于晶体管栅极端子的凸块表示为125。在示范性转换器100中，有利的是，以行及列组成的有序图案来排列晶体管及载体的导电凸块。具体来说，有利的是，以标准占用面积来排列晶体管凸块以用于附接到PCB。对于晶体管110的垂直凸块行来说，图2的示范性转换器展示0.72mm的中心到中心凸块间距220。对于晶体管110及120的水平凸块列来说，图2的示范性转换器展示0.65mm的中心到中心凸块间距221。对于载体130的凸块(126)的行来说，图2的示范性转换器展示0.5mm的凸块间距231。在其它实施例中，焊接垫及凸块可更任意地布置。
如上文论述，所有导电凸块具有相同的体积。在此条件及回流焊料正打湿接合垫的整个区域的事实之下，图4的图表说明接合垫的面积(由圆形钝化开口的直径(图4的横坐标)表示)与凸起凸块表面的顶端(由回流之后的焊料凸块的高度(图4的纵坐标)表示)之间的关系。图4的数据展示顶端与垫面积之间的关系是线性的，其由线401指示；参数为凸块体积，其给予所述线斜率。因此，顶端在所述垫区域上的高度与垫区域的直径成反比，因为所有凸块具有相等的焊料体积。
图4的特定数据是针对0.014mm3的焊料凸块体积而获得的。此体积可通过回流直径为0.3mm的焊料球来获得。作为工艺的实例，由锡/银合金制成的球被沉积在每一接合垫上、在回流温度下被液化直到垫区域由焊料覆盖。表面张力使熔融合金形成为具有顶端的凸起表面。当焊料温度下降到周围温度时，所述凸块固化。作为实例，图4的数据展示0.18mm2的圆形FET垫区域上的凸块(与0.48mm的垫直径相关)具有0.15mm的高度。FET凸块的此高度在图3中表示为311。图4的数据进一步展示0.07mm2的圆形载体垫区域上的凸块(与0.3mm的垫直径相关)具有0.22mm的高度。载体凸块的此高度在图3中表示为331。
FET垫区域上的凸块高度与载体垫区域上的凸块高度之间的0.07mm的差异补偿芯片厚度(0.05mm)与附接层(厚度(0.02mm)的和。为计算FET处的高度，在载体130的表面130a处开始，粘合剂材料的具有厚度141(0.02mm)的层将具有厚度113(0.05mm)的FET芯片110及120并排附接到载体表面130a上。FET凸块在顶端处展示0.15mm的高度311。因此，在FET处的总高度为0.22mm。这是与上文引述的载体凸块高度331相同的高度。
由于不同的凸块高度，所有的顶端位于在图1中表示为150的共用平面上。所述凸块是共面的。共面性的事实在图3中由虚线340说明。
凸块共面性的特征使得能够进行转换器100到PCB的高良率附接。翻转(倒置)转换器100且使其与PCB的表面对准，直到平面340与PCB表面平行。接着将转换器100降低到PCB上，直到平面340与PCB表面共轴，借此所有倒置凸块顶点触摸PCB表面。所有的凸块都准备好同时附接到PCB表面。
在其它实施例中，FET芯片可能不具有相等的厚度。为获得用于等体积的凸块的凸块共面性，相比于第二FET，对于第一FET来说，用于凸块的接触面积必须是不同的。当将两个FET安装在平坦载体(在平面中的载体表面上)上时，相比于较厚芯片的接触面积，较薄芯片的接触面积必须是较小的(也见图4)。
图1到4中说明的用于通过使凸块高度与用于等体积的凸块的凸块附接面积负相关来实现连接凸块的共面性的方法可一般化到任何载体，所述载体具有带有不位于共用平面上的多个接触垫的表面。作为实例，载体可具有具阶梯的表面，使得接触垫位于不同的平面上。对于此载体，提供等体积的体的供应，其中所述体的材料适于形成连接。将来自此供应的一个体选择为附接到每一接触垫。执行所述附接使得所述体的材料分散在相应的垫区域上且形成具有包括顶端的凸起表面的凸块。当所述垫面积与相应凸块的顶端负相关时，等体积的所有凸块的顶端将位于共用平面上；所述凸块顶端是共面的。
为总结图1到3中论述的示范性转换器封装相比于常规转换器封装的电性改进，将用于包括两个个别包封的电力FET520及510的常规同步降压转换器的图5的电路图与如图1到3中论述的包括用于电力FET620及610未包封的芯片的转换器的图6的电路图进行比较。可通过降低电力损失来实现提高同步降压转换器的效率的目标：
效率＝输出电力/输入电力
＝输入电力/(输入电力-电力损失)。
同步降压转换器中的电力损失由以下等式决定：
电力损失＝IL 2R+PSW
(其中IL＝负载电流，R＝本征电阻，PSW＝切换损失)。可通过沿着两条线路前进来实现降低电力损失及提高效率：降低切换损失PSW且因此降低装置水平的热产生，及提高在板水平的热消散。PSW可通过消除图5的许多地方中存在的归因于基于有线接合、线夹具有垫及引线(端子)的引线框来组装控制FET及同步FET芯片的方法的寄生电感及电阻来降低。此外，将散热片附接到芯片载体的未阻塞表面的可能性有效地支持板水平的热消散。
在图5中，高侧(控制)FET520的芯片由封装521封闭。FET520使其漏极520c被连接到封装漏极端子522，其中所述连接包括寄生电阻RHSD(523)及寄生电感LHSD(524)；端子522又系到输入端子VIN(560)。此外，FET520使其源极520a被连接到封装源极端子525，其中所述连接包括寄生电阻RHSS(526)及寄生电感LHSS(527)；端子525又系到低侧(同步)FET封装511的漏极端子512且与迹线562系在一起作为到负载570的开关节点。最后，FET520使其栅极520b被连接到封装栅极端子528，其中所述连接包括寄生电阻RHSG(529)及寄生电感LHSG(530)；端子528又系到驱动器及控制器540。
在图5中，低侧(同步)FET510的芯片由封装511封闭。FET510使其漏极510c被连接到封装漏极端子512，其中所述连接包括寄生电阻RLSD(513)及寄生电感LLSD(514)；端子512又系到高侧(控制)FET封装521的源极端子525，且与迹线562系在一起作为到负载570的开关节点。此外，FET510使其源极510a被连接到封装源极端子515，其中所述连接包括寄生电阻RLSS(516)及寄生电感LLSS(517)；端子515又系到接地电势561。最后，FET510使其栅极510b被连接到封装栅极端子518，其中所述连接包括寄生电阻RLSG(519)及寄生电感LLSG(531)；端子518又系到驱动器及控制器541。
图5中的转换器图(基于常规组装)与图6中的转换器图(基于通过本发明的概念进行的组装)的比较说明转换器的寄生成分显著降低。封装相关的互连寄生电阻523、526、529、513、516及519、开关节点迹线及封装相关互连寄生电感524、527、530、514、517及531被消除。相反，在图6中，高侧(控制)FET620的芯片及低侧(同步)FET610的芯片并排附接在用作具有非常小的寄生电阻RSW(663)及非常小的寄生电感LSW(664)的开关节点的载体662上。因使用了凸块互连，所述FET端子具有到PBC迹线的直接通道：高侧(控制)FET620的漏极620c通过端子凸块622经由PBC迹线直接系到输入端子VIN(660)；低侧(同步)FET610的源极610a通过端子凸块615经由PBC迹线直接系到接地电势661；高侧(控制)FET620的栅极620b通过端子凸块628经由PBC迹线直接系到驱动器及控制器640；低侧(同步)FET610的栅极610b通过凸块618经由PBC迹线直接系到驱动器及控制器641；且载体通过端子凸块/凸块662a经由PBC迹线直接系到负载670。
图1到3中描述的转换器的紧凑配置进一步使得包括接地环路的较紧的电环路及较短的PBC迹线铺设和互连及因此降低的PBC寄生成为可能。这些消除的寄生物连同上文描述的转换器封装中的实质性寄生消除一起导致转换器电力损失降低且因此提高了转换器效率。这些获益通过经由附接到如图3中指示的未障碍载体表面的散热片对转换器FET的有效冷却而进一步得到增强。
虽然已参考说明性实施例描述了本发明，但此描述无意以限制意义加以理解。在参考所述描述之后，所属领域的技术人员将理解说明性实施例的各种修改及组合以及本发明的其它实施例。作为实例，本发明不仅适用于场效晶体管，而且还适用于其它合适的功率晶体管。
作为另一实例，本发明适用于使垫不位于单个平面内而位于若干平面内但仍需要使这些垫被附接到平面衬底的表面。对于同体积的共面连接器，必须以与垫与衬底之间的距离反关系来选择垫面积。
因此，希望所附权利要求书涵盖任何此类修改或实施例。

Claims (18)

1.一种设备，其包含：
载体，其具有带有多个接触垫的表面，所述垫不位于一平面上；
多个焊料凸块，其具有相同的体积，一凸块附接到每一垫，每一凸块分布在相应的垫区域上且具有带有顶端的凸起表面；且
所述顶端位于共用平面内。
2.根据权利要求1所述的设备，其中所述凸起凸块表面具有球形外形。
3.根据权利要求1所述的设备，其中所述凸起凸块表面是通过焊料回流工艺形成。
4.一种经封装电力供应模块，其包含：
具有第一电力场效晶体管FET的芯片及具有以导电方式并排附接到导电载体上的第二FET的芯片，所述晶体管具有具第一面积的接合垫，且所述载体具有具小于所述第一面积的第二面积的接合垫；及
导电凸块，其附接到所述晶体管接合垫及所述载体接合垫，所述凸块具有相等的体积且共面，所述晶体管垫上的所述凸块具有第一高度，且所述载体垫上的所述凸块具有大于所述第一高度的第二高度。
5.根据权利要求4所述的模块，其中所述第一及第二芯片具有相等的厚度。
6.根据权利要求5所述的模块，其中所述晶体管接合垫位于第一平面内，且所述载体接合垫位于与所述第一平面间隔的第二平面内，所述间隔约等于所述芯片厚度。
7.根据权利要求6所述的模块，其中所述第二凸块高度与所述第一凸块高度之间的差等于所述第一平面与所述第二平面之间的所述间隔。
8.根据权利要求4所述的模块，其中所述载体为由具有可焊接表面的金属制成的平坦板。
9.根据权利要求8所述的模块，其中所述金属包括铜或铝。
10.根据权利要求4所述的模块，其中所述第一及所述第二FET附接到一个载体表面上，而相对的载体表面可用于附接散热片。
11.根据权利要求4所述的模块，其中所述导电凸块为焊料。
12.根据权利要求11所述的模块，其中所述焊料凸块具有约0.014mm3的体积，如直径为0.3mm的焊料球所提供；晶体管接合垫面积约为0.18mm2，如由直径为0.48mm的圆形所提供；及载体接合垫面积约为0.07mm2，如由直径为0.3mm的圆形所提供。
13.根据权利要求4所述的模块，其中所述FET接合垫及所述载体接合垫由不可焊接涂层围绕。
14.根据权利要求13所述的模块，其中所述FET接合垫的所述不可焊接涂层是顺应性的，且足够厚以用作所述凸块之间的应力吸收底部填充。
15.根据权利要求4所述的模块，其中所述晶体管的所述导电凸块以由列及行组成的有序图案排列。
16.根据权利要求15所述的模块，其中所述晶体管凸块以标准占用面积排列。
17.根据权利要求4所述的模块，其中所述第一FET使其漏极以导电方式附接到所述载体，且所述第二FET使其源极以导电方式附接到所述载体。
18.根据权利要求17所述的模块，其中所述第一FET为所述模块的同步(低侧)晶体管，且所述第二FET为所述模块的控制晶体管(高侧)。
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CN104681518B (zh) * 2013-12-03 2018-05-04 英飞凌科技股份有限公司 集成ic封装
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