CN103034897B - 芯片卡和用于制造芯片卡的方法 - Google Patents
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Abstract
本发明涉及一种芯片卡,其包括:卡体(36),所述卡体在其顶侧中设有空腔;插入到空腔中的芯片模块(37),其中芯片模块插入到空腔中,使得芯片模块的模块触点(38)朝向设置在卡体中的天线的天线触点(39),所述天线触点设置在空腔的底部中,并且模块触点和天线触点的电接触通过设置在空腔中的、由接触导体形成的接线(60)来实现,其中接线具有接触导体横截面,所述接触导体横截面的沿着平行于天线触点或模块触点的接触表面设置的横轴线的宽度大于接触导体横截面的沿着垂直于天线触点或模块触点的接触表面设置的纵轴线的高度。此外,本发明涉及一种用于制造芯片卡的方法。
Description
技术领域
本发明涉及一种芯片卡,其包括:卡体,所述卡体在其顶侧中设有空腔;设置在空腔中的卡模块,其中芯片模块插入到空腔中,使得芯片模块的模块触点朝向设置在卡体中的天线的天线触点,所述天线触点设置在空腔的底部中,并且模块触点和天线触点的电接触通过设置在所述空腔中的、由接触导体形成的接线来实现。此外,本发明涉及一种用于制造该芯片卡的方法。
背景技术
从WO 2008/129526中已知一种开始所述类型的芯片卡,其中设置在卡体中的天线的天线触点与插入到空腔中的芯片模块的模块触点触点接通,其中所述天线触点设置在卡体的空腔的底部中。为了建立在芯片模块和设置在卡体中的天线之间的导电连接,首先通过构成天线的线圈的端部设有金属薄片来构成扩大的天线触点。接下来进行构成为细线的连接导体与通过金属薄片构成的天线触点的触点接通。为了随后触点接通通过细线构成的连接导体的自由端部,所述连接导体基本垂直于卡体的顶侧定向并且随后与芯片模块的模块触点触点接通。由于将芯片模块插入或者嵌入到空腔中,得到下述构造,其中模块触点和天线触点朝向彼此地设置并且通过细线构成的连接导体由于将模块插入到空腔中而处于在空腔之内的偶然收缩的构造中。
已知的芯片卡的制造变得相当耗费,因为构成为细线的连接导体与构成天线的天线线圈的端部的直接触点接通是不可能的,并且相反地,首先用于构成在连接导体和天线之间的足够的接触面的金属薄片必须设置在空腔中。此外,在实践中证实,连接导体的自由端部与芯片模块的模块触点的触点接通是复杂的过程,因为首先必须进行将连接导体对准到相对于卡体垂直的延伸部中,并且接下来必须进行连接导体的自由端部的操作,以便将所述自由端部定位成与模块触点重合,作为用于后续的触点接通过程的前提。
发明内容
以现有技术为出发点,本发明的目的基于,提出一种芯片卡或一种用于制造芯片卡的方法,所述芯片卡或所述方法实现芯片卡的简化的制造。
这个目的通过根据本发明的芯片卡和根据本发明的方法得以实现。
根据本发明,接线具有接触导体横截面,所述接触导体横截面的沿着平行于天线触点或模块触点的接触表面设置的横轴线的宽度大于接触导体横截面的沿着垂直于天线触点或模块触点的接触表面设置的纵轴线的高度。
借助以此构成的接触导体,使接线的构成成为可能,所述接触导体相比于具有圆形横截面的细线导体具有实现与天线触点可靠的触点接通的接触表面,而所述接触导体事先不必须设有扩大的连接面。此外,这种接触导体在其纵向延伸上具有相对较大的方向稳定性。为此可能的是,将接触导体定位在连接面上方,即在芯片模块的模块触点或天线触点上方,而不必须为此占据接触导体的自由端部本身。相反地,由于接触导体给定的方向稳定性,接触导体的限定的定向是可能的,而没有固定或者占据接触导体的自由端部。
当作为扁平带形横截面的接触导体横截面具有下边缘和上边缘时,得到连接导体和模块触点或天线触点的可靠的触点接通,所述下边缘和上边缘基本平行于横轴线构成。
在接触导体在空腔中的节约空间的安置和与模块触点或天线触点尤其可靠的触点接通方面,尤其有利的是,接触导体具有宽度至少10倍于高度的横截面。优选的是,连接导体构成为薄膜条。
当接触导体具有至少一个弯折位置时,能够实现接线在空腔中例如通过接触导体的折叠状的褶皱整齐的、节约空间的设置。
当用于形成理论弯折位置的接触导体具有带有减少的横截面面积的弯曲横截面时,可以在制造接线之前通过接触导体的相应的划分已经预先设定理论弯折位置。优选地,通过弯曲横截面具有减小的横截面高度来构成弯曲横截面。
因此,当尤其在通过线导体构成的天线的情况下,形成由构成天线的天线导体的蜿蜒形设置的天线导体端部组成的天线触点接触面时,进一步要求构成在接触导体和设置在卡体中的天线之间的可靠的且尽可能大面积的触点接通。在此优选的是,天线导体的构成接触表面的表面区域设有触点展平部,以便更进一步扩大在天线和接触导体之间的接触面。
但是不同于由线导体组成的天线的实施方式,所有其他的天线实施方式,即尤其是蚀刻或印制的天线,也是可能的,所述天线的天线触点能够与接线触点接通。
当蜿蜒形设置的天线导体的端部具有通过天线导体中间空间彼此间隔的天线导体部段时,其中所述天线导体部段高出空腔的底部,则更进一步扩大在天线导体和接触导体之间的接触面,或者在接触导体和天线导体之间且在蜿蜒形设置的天线导体端部的区域中构成的浸润面。
在芯片卡或者芯片卡的为了完整而设有芯片模块的天线模块中,也与如何与芯片模块进行随后的触点接通的方式无关,具有天线导体部段的蜿蜒形设置的天线端部的上述有利的实施方式是尤其有利的,因为通过蜿蜒形设置的天线导体端部的设计实现尤其导电的触点接通并且同时实现与芯片模块的持久的电接触,所述天线导体部段通过天线导体中间空间彼此分离,其中天线导体部段优选高出空腔的底部,所述天线导体端部优选设有天线导体端部的展平部,以用于构成扩大的接触表面。
在此,天线导体部段的高出空腔的底部的构造尤其引起由焊接材料或也由导电粘合剂形成的连接材料与天线导体端部的接合连接。
此外,尤其是在天线模块的衬底中的天线导体端部区域中通过铣削加工制造的空腔中,得到天线导体端部的无氧化物的表面,所述天线导体端部尽可能地排除在天线导体端部和随后触点接通的芯片模块的连接面之间构成不期望的接触电阻。
根据本发明,为了制造芯片卡,进行芯片模块的借助朝上的模块触点的定位。同样进行卡体的借助朝上的天线触点的定位。在接触导体与模块触点接触之前,进行接触导体的相对于模块触点的定位,使得接触导体与模块触点成一定距离地彼此平行地定向,延伸到与模块触点的重合位置上并且接触导体端部延伸出芯片模块的侧棱边。
为了将接触导体端部与天线触点触点接通,进行接触导体端部与天线触点重合的定位,其中芯片模块平行于卡体的顶侧,并且芯片模块的侧棱边平行地且紧邻空腔的开口边缘地设置。
在接触导体端部触点接通之后,将接触导体端部分离,以用于构成接线,并且芯片模块围绕其侧棱边转动,并且将芯片模块插入到卡体的空腔中,使得模块触点朝向天线触点。
优选的是,将芯片模块的转动与平移运动叠加。
由于使用构成扁平带式的接触导体,适用于将接触导体定位在模块触点或天线触点上方的定向或接触导体的纵向延伸也许是可能的。因此尤其可能的是,进行芯片模块的定位和卡体的定位,使得分别为了触点接通而彼此关联的触点,即分别是天线触点和模块触点,彼此对准地设置,使得在接触导体相应地直线延伸时,接触导体的相对于天线触点或模块触点的适合于随后触点接通的相对定位也许是可能的。
接触导体由于其方向稳定的构造能够同时地相对于模块触点和天线触点定向并且随后触点接通。在发生触点接通之后,通过芯片模块围绕其相邻于空腔的侧边缘设置的侧棱边转动,将芯片模块送到空腔中。在此,作为铰接带式的、与模块触点和天线触点触点接通的接触导体能够辅助引导这个转动运动。
尤其有利的是,在天线触点上方定位接触导体端部且在模块触点上方定位接触导体之前,进行芯片模块的相对于卡体的相对定位,使得卡体和芯片模块设置在两个彼此偏移地设置的、平行的平面中,并且芯片模块设置在卡体之上。以这种方式能够进行接触导体在相应的连接面上方的定位,以及接触导体与连接面,即天线触点和模块触点,在芯片模块和卡体的相对位置上的触点接通,这使得随后将芯片模块插入到卡体的空腔中变得容易。
尤其有利的是,为了在天线触点上方定位接触导体端部和在模块触点上方定位接触导体,分别沿着输送轴线输送接触导体,其中输送轴线分别通过在通过接触导体彼此连接的天线触点和模块触点之间的连接线来限定。由此可能的是,为芯片模块和卡体选择实现接触导体的连续输送的相对设置。由此尤其得到下述可能性,即以节拍法制造芯片卡,其中为了建立在卡体和芯片模块之间的导电连接,将以合适的相对定位彼此定位的部件,即卡体和芯片模块定位在接触导体输送站之前,并且在接触导体从接触导体输送站中进给之后,进行接触导体与天线触点或模块触点的触点接通。
当在接触导体相对于模块触点和天线触点定位之前,在用于构成在卡体和芯片模块之间的接线的接触导体部段中的接触导体设有至少一个理论弯折位置时,由此能够辅助在将芯片模块插入到空腔之后在空腔中限定地设置接线。
可替代地还可能的是,在接触导体与模块触点和天线触点触点接通后并且在通过接触导体端部的分离构成接线后,在进行转动/平移运动叠加的情况下,通过接线的弯曲构成弯折位置。
尤其在下述情况中,即当使用不具有连接材料覆层,尤其是不具有焊接材料涂层的接触导体来形成在卡体和芯片模块之间的接线时,有利的是,在接触导体相对于模块触点和天线触点定位之前,将构成片状的焊料淀积物施加到模块触点和天线触点上。
尤其是为了固定用于随后的焊接过程的焊料淀积物,有利的是,在将焊料淀积物涂覆到模块触点和天线触点上之前,将助焊剂淀积物涂覆到模块触点和天线触点上。
附图说明
下面借助附图详细地阐明根据本发明的方法的优选变形形式和根据本发明的芯片卡的优选实施形式。其中:
图1示出在卡体的第一实施形式的制造期间借助芯片模块的相对于卡体的相对定位的定位阶段;
图2示出接触导体的接触导体输送;
图3示出接触导体在卡体的天线触点或芯片模块的模块触点上方的定位的细节图;
图4示出与用于构成在芯片模块和卡体的天线之间的接线的接触导体的触点接通的触点接通阶段;
图5示出随着将芯片模块摆动到卡体的空腔中的安装阶段;
图6示出具有插入到卡体的空腔中的芯片模块的芯片卡的剖视图;
图7示出具有插入到卡体的空腔中的芯片模块的可替代地实施的芯片卡的剖视图;
图8示出在安装过程期间根据图7中的图示插入到空腔中的芯片模块;
图9示出在卡体中构成的空腔的俯视图;
图10示出图9中示出的空腔的部分剖视图;
图11示出在叠加的摆动/平移运动的第一阶段中的芯片模块;
图12示出在叠加的摆动/平移运动的第二阶段中的芯片模块;
图13示出在叠加的摆动/平移运动的第三阶段中的芯片模块。
具体实施方式
图1示出设置在两个彼此平行的平面中的卡体10和芯片模块11,其中芯片模块11位于设置在卡体10的顶侧12之上的芯片模块容纳部13中。
卡体10具有设置在卡体10中的天线14,所述天线具有用于构成天线线圈的天线导体15,并且为了与芯片模块11触点接通,所述天线导体具有天线触点16、17,所述天线触点设置在构成在卡体10中的空腔19的底部中。
设置在芯片模块容纳部13中的芯片模块11在其在图1中朝上的底侧20上设有模块触点21,22,所述模块触点用于与天线触点16,17触点接通,并且如天线触点16,17一样,所述模块触点的接触表面53指向上地设置。
在图1中示出的芯片模块11在其位于底侧20对面的顶侧上(图6)具有在此没有详细示出的触点装置,所述触点装置实现对数据的直接的数据访问,所述数据储存在芯片模块11的在此没有详细示出的芯片上。设置在芯片模块11的底侧20上的模块触点21,22通过与天线14的天线触点16,17的触点接通实现构成应答器,并且因此代替芯片模块11的外部触点装置或与芯片模块11的外部触点装置并行地通过合适的、在此没有详细示出的读取装置实现对储存在芯片中的数据进行无接触的访问。这种芯片卡还称作双界面卡(DIF),所述芯片卡实现无接触的数据访问和接触的数据访问。
如图2示出,将接触导体23,24输送给由卡体10和芯片模块11组成的部件装置,所述触点导体具有扁平带形横截面25,如在图3中所示,所述扁平带形横截面具有沿着基本平行于天线触点16,17或模块触点21,22的接触表面53延伸的横轴线54的宽度,所述宽度大于扁平带形横截面25的沿着纵轴线55的高度。
由于上述横截面构造,以例如扁平带形构成的接触导体23,24垂直于天线触点16,17的或模块触点21,22的接触表面53具有增大的刚性或相对大的扭弯力矩,使得能够沿在图2中示出的输送方向26基本上直线地输送接触导体23,24或自由的接触导体端部,而不增加接触导体23,24侧向偏移的风险。由此,接触导体23,24的目标明确的输送是可能的,以用于实现与天线触点16,17或模块触点21,22的重合。
接触导体23,24的围绕横轴线54或者围绕平行于天线触点16,17或模块触点21,22的接触表面53的轴线可能的变形证明对于后续的触点接通过程是不重要的,因为借助触点接通工具56进行如在图4中示出的触点接通,为了施加在触点接通期间必需的接触压力,所述触点接通工具总归要将接触导体23,24压向天线触点16,17或模块触点21,22的接触表面53。在进行触点接通之后或在接触导体23,24与模块触点21,22触点接通之后,或还根据触点接通工具56的实施方式,在触点接通期间,能够进行接触导体端部段的分离,以用于构成在相应天线触点16或17和模块触点21或22之间的接线27,28。
图5示出,在形成在天线触点16,17和模块触点21,22之间的接线27,28之后,如何通过围绕芯片模块11的紧邻空腔19的开口边缘29的侧棱边30转动,将芯片模块11送到或者插入到空腔19中。
在图5中示出的制造方法的变形形式中,——其中将芯片模块11定位在芯片模块容纳部13中——,芯片模块容纳部13的平行于侧棱边30的转动棱边31位于卡体10的顶侧12上,或位于在此没有详细示出的、平行于卡体10的顶侧12设置的转动支撑件上,使得转动能够作为限定的运动来进行。
由于芯片模块11转动或将芯片模块11插入到空腔19中,产生通过接触导体部分段构成的接线27,28的折弯或折叠,使得如例如在图6中示出,在将芯片模块11插入到空腔19之后,为构成芯片卡而通过弯折位置形成的接线部段33,34彼此相邻地延伸或者彼此重叠地放置。
如从图7和8中的示出芯片卡58的容纳在卡体36的空腔35中的芯片模块37的图示中清楚看出,在芯片卡的这个实施形式中,构成在模块触点38和由接触导体端部段组成的天线触点39之间的接线40具有多个弯折位置41,使得接线40在当前的情况下被分成四个接线部段42。为了在将芯片模块37以在图8中示意地示出的方式插入到空腔35内时,在限定的位置上构成弯折位置41,为制造接线40所使用的接触导体23,24设有在此没有详细示出的理论弯折位置,所述理论弯折位置能够通过接触导体23,24的线横截面的横截面减小来构成,例如通过引入直线形的冲压件,所述冲压件横向于接触导体23,24的纵向尺寸延伸。
如图8和图9的概览图清楚示出,卡体36的空腔35构成阶梯形,且具有用于支撑芯片模块37的支承边缘43的环绕的支承框架42。支承框架在天线触点39的区域中设有凹处44,所述凹处用于使天线触点39露出,并且同时如从图7和8的概览图中可清楚看出构成用于放置接线40的容纳空间或储藏空间45。
为了在卡体36中固定芯片模块37,在示出的实施例中,芯片模块37的支承边缘43具有粘合剂覆层46,所述粘合剂覆层在将芯片模块37插入到空腔35中同时,实现在将芯片模块37固定在卡体36中。
如在图9和10中示出,通过蜿蜒地设置天线导体48的,形成设置在卡体36中的天线47的天线触点39,其中天线导体48设有展平部51,以用于构成由各个触点部分面49组成的接触表面50。为了形成接触表面50的暴露的、从空腔35的底部52中突出的构造,通过例如通过施加激光形成的烧蚀,去除卡体36的在天线导体中间空间中的或相邻于天线导体48的塑料材料。
需要时,通过施加激光还能够去除位于天线触点上的漆绝缘层。
在图11,12和13中,借助已经在图7和8中示出的芯片模块37的示例示出接线60的可替代的实施方案,所述接线分别在彼此相关联的天线触点39和模块触点38之间延伸。不同于在图7和8中示出的接线40,——所述接线的弯折位置41构成在理论弯折位置上,所述理论弯折位置例如通过已经在接触导体中为了构成接线而存在的横截面减小来限定——,弯折位置61和62以在图11-13阐明的方式构成在接线60上,这在下面涉及。
如在图11中示出,在形成模块触点38和天线触点39之间的接线60之后,进行芯片模块37的沿在图11中标明的方向的转动运动63,其中转动运动与横向运动64叠加或者转动运动与横向运动组合,所述横向运动以大约平行于卡体36的表面来进行。由于芯片模块37的这个随后表示为转动/平移运动的进给运动,在接线60中构成具有在继续进行转动/平移运动时变得更绷紧的条带弧形66的回线65。
沿着将模块触点38与天线触点39连接的力轴线67,在接线60上作用有随着继续的转动/平移运动而增加的弯折载荷,所述弯折载荷根据接线60的线横截面和其弯曲刚度导致接线60在预设的弯折位置61处的弯曲(图12)。
如图13所示,现在能够借助压板68构成其他的弯折位置62,所述压板限定接线60的转向位置,然后在所述转向位置上,在超过在接线60中的弯曲应力的情况下构成第二弯折位置62。
在构成第二弯折位置62之后,然后实施其他的转动/平移运动,使得在运动的结束时,将芯片模块37插入到空腔35中。
Claims (18)
1.芯片卡(58),包括:卡体(10、36),所述卡体在其顶侧(12)中设有空腔(19、35);和插入到所述空腔中的芯片模块(11、37),其中将所述芯片模块插入到所述空腔中,使得所述芯片模块的模块触点(21、22、38)朝向设置在所述卡体中的天线(14、47)的天线触点(16、17、39),所述天线触点设置在所述空腔的底部(52)中,并且通过设置在所述空腔中的、由接触导体(23、24)形成的接线(27、28、40、60)实现所述模块触点和所述天线触点的电接触,
其特征在于,
所述接线沿着其整个长度具有接触导体横截面,所述接触导体横截面的沿着平行于所述天线触点或模块触点的接触表面(53)设置的横轴线(54)的宽度构造得大于所述接触导体横截面的沿着垂直于所述天线触点或所述模块触点的所述接触表面设置的纵轴线(55)的高度,以及所述接触导体(23、24)具有至少一个弯折位置(41、61、62)。
2.根据权利要求1所述的芯片卡,其特征在于,所述接触导体横截面构成为扁平带形横截面(25),其具有基本平行于所述横轴线(54)构成的下边缘和上边缘。
3.根据权利要求1或2所述的芯片卡,其特征在于,所述接触导体横截面具有至少为所述接触导体横截面的所述高度的10倍的宽度。
4.根据权利要求1或2所述的芯片卡,其特征在于,所述接触导体(23、24)构成为薄膜条。
5.根据权利要求1所述的芯片卡,其特征在于,所述接触导体(23、24)具有带有减小的横截面积的弯曲横截面,以用于构成所述弯折位置(41)。
6.根据权利要求5所述的芯片卡,其特征在于,所述弯曲横截面具有减小的横截面高度。
7.根据权利要求1或2所述的芯片卡,
其特征在于,
所述天线触点(39)具有接触表面(50),所述接触表面由构成所述天线(47)的天线导体(48)的蜿蜒形设置的天线导体端部组成。
8.根据权利要求7所述的芯片卡,
其特征在于,
所述天线导体(48)的构成所述接触表面(50)的表面区域具有展平部(51)。
9.根据权利要求6所述的芯片卡,
其特征在于,
所述天线导体(48)具有通过天线导体中间空间彼此间隔的天线导体部段,以用于构成所述天线触点(39),所述天线导体部段突出于所述空腔(35)的所述底部(52)。
10.用于制造芯片卡(58)的方法,所述芯片卡包括:卡体(10、36),所述卡体在其顶侧(12)中设有空腔(19、35)且具有设置在所述卡体中的天线(14,47);以及设置在所述空腔中的芯片模块(11、37),所述方法包括下述方法步骤:
-定位具有朝上的模块触点(21,22,38)的所述芯片模块(11,37);
-定位具有朝上的天线触点(16,17,39)的所述卡体;
-相对于所述模块触点定位具有扁平带形横截面(25)的接触导体(23、24),使得所述接触导体与所述模块触点成一定距离地彼此平行地定向,延伸到与所述模块触点的重合位置上并且接触导体端部延伸出所述芯片模块的侧棱边;
-将所述接触导体端部定位成与所述卡体的所述天线触点重合,其中所述芯片模块平行于所述卡体的所述顶侧,并且所述芯片模块的所述侧棱边(30)平行地且紧邻所述空腔的开口边缘(29)地设置;
-将所述接触导体与所述模块触点触点接通;
-将所述接触导体与所述天线触点触点接通;
-分离所述接触导体端部,以用于构成在所述模块触点和所述天线触点之间的接线(27,28,40,60);
-围绕所述芯片模块的侧棱边转动所述芯片模块,并且将所述芯片模块插入到所述卡体的所述空腔中,使得所述模块触点朝向所述天线触 点。
11.根据权利要求10所述的方法,
其特征在于,
所述芯片模块(11,37)的所述转动与所述芯片模块的平移运动叠加。
12.根据权利要求11所述的方法,
其特征在于,
在将所述接触导体(23,24)在所述天线触点(16,17,39)和在所述模块触点(21,22,38)上方定位之前,进行所述芯片模块(11,37)相对于所述卡体(10,36)的相对定位,使得所述卡体和所述芯片模块设置在两个彼此偏移设置的、平行的平面中,并且所述芯片模块设置在所述卡体之上。
13.根据权利要求12所述的方法,
其特征在于,
将所述芯片模块(11)设置在芯片模块容纳部(13)中,所述芯片模块容纳部设置在所述卡体(10)之上。
14.根据权利要求12或13所述的方法,
其特征在于,
为了在所述天线触点(16,17)上方定位所述接触导体(23,24)并且在所述模块触点(21,22)上方定位所述接触导体,分别沿着输送轴线输送所述接触导体,所述输送轴线分别通过借助所述接触导体彼此连接的天线触点和模块触点来限定。
15.根据权利要求10至13中任一项所述的方法,
其特征在于,
在相对于所述模块触点(21,22)定位所述接触导体(23,24)并且相对于所述天线触点(16,17)定位所述接触导体之前,所述接触导体至少在用于构成接线的接触导体端部的区域中设有至少一个理论弯折位置。
16.根据权利要求10至13中任一项所述的方法,
其特征在于,
在将所述接触导体与所述模块触点(38)和所述天线触点(39)触点接通后并且在通过分离所述接触导体端部构成所述接线(60)之后,在进行转动/平移运动(63、64)叠加的情况下,通过所述接线的弯曲构成弯折位置(61,62)。
17.根据权利要求10至13中任一项所述的方法,
其特征在于,
在相对于所述模块触点(21,22,38)定位所述接触导体(23,24)之前并且在相对于所述天线触点(16,17,39)定位所述接触导体之前,将构成片状的焊料淀积物施加到所述模块触点和/或所述天线触点上。
18.根据权利要求17所述的方法,
其特征在于,
在将所述焊料淀积物涂覆到所述模块触点(21,22,38)和/或所述天线触点(16,17,39)上之前,将助焊剂淀积物涂覆到所述模块触点和/或天线触底上。
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CN103440520B (zh) * | 2013-08-15 | 2016-06-08 | 中电智能卡有限责任公司 | 双界面卡的封装工艺方法及其不干胶带粘起机构 |
FR3030087B1 (fr) * | 2014-12-11 | 2018-04-20 | Idemia France | Module pour cartes a microcircuit, cartes a microcircuit comprenant un tel module et procede de fabrication |
US11203501B2 (en) | 2017-09-29 | 2021-12-21 | Avery Dennison Retail Information Services Llc | Systems and methods for transferring a flexible conductor onto a moving web |
CN117377963A (zh) * | 2021-05-21 | 2024-01-09 | 兰克森控股公司 | 用于集成到智能卡的卡本体中的模块、智能卡、以及将模块植入智能卡的卡本体中的方法 |
Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN1750026A (zh) * | 2004-09-15 | 2006-03-22 | 株式会社Y.B.L | 双界面ic卡 |
Family Cites Families (38)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6442831B1 (en) * | 1993-11-16 | 2002-09-03 | Formfactor, Inc. | Method for shaping spring elements |
DE4431605C2 (de) * | 1994-09-05 | 1998-06-04 | Siemens Ag | Verfahren zur Herstellung eines Chipkartenmoduls für kontaktlose Chipkarten |
DE19500925C2 (de) * | 1995-01-16 | 1999-04-08 | Orga Kartensysteme Gmbh | Verfahren zur Herstellung einer kontaktlosen Chipkarte |
JP2814477B2 (ja) * | 1995-04-13 | 1998-10-22 | ソニーケミカル株式会社 | 非接触式icカード及びその製造方法 |
DE19521111C2 (de) * | 1995-06-09 | 1997-12-18 | Wendisch Karl Heinz | Ausweis-Chipkarte mit Antennenwicklungsinlet |
FR2760113B1 (fr) * | 1997-02-24 | 1999-06-04 | Gemplus Card Int | Procede de fabrication de carte sans contact a antenne bobinee |
US7198190B2 (en) * | 1997-03-12 | 2007-04-03 | Dodge Juhan | Identification device having reusable transponder |
DE19710144C2 (de) * | 1997-03-13 | 1999-10-14 | Orga Kartensysteme Gmbh | Verfahren zur Herstellung einer Chipkarte und nach dem Verfahren hergestellte Chipkarte |
DE19749650C2 (de) * | 1997-11-10 | 2000-01-13 | Meinen Ziegel & Co Gmbh | Verfahren zum Herstellen einer elektrischen Verbindung eines in einer Kavität eines Kartenkörpers einer Chipkarte eingesetzten, elektronische Komponenten aufweisenden Moduls |
JPH11250214A (ja) * | 1998-03-03 | 1999-09-17 | Matsushita Electron Corp | 部品の実装方法とicカード及びその製造方法 |
FR2782822A1 (fr) * | 1998-09-02 | 2000-03-03 | Hitachi Maxell | Module a semi-conducteur et procede de production |
US20020075186A1 (en) * | 2000-12-20 | 2002-06-20 | Hiroki Hamada | Chip antenna and method of manufacturing the same |
GB2371264A (en) * | 2001-01-18 | 2002-07-24 | Pioneer Oriental Engineering L | Smart card with embedded antenna |
US6951596B2 (en) * | 2002-01-18 | 2005-10-04 | Avery Dennison Corporation | RFID label technique |
DE10117994A1 (de) * | 2001-04-10 | 2002-10-24 | Orga Kartensysteme Gmbh | Trägerfolie für elektronische Bauelemente zur Einlaminierung in Chipkarten |
US6425518B1 (en) * | 2001-07-25 | 2002-07-30 | International Business Machines Corporation | Method and apparatus for applying solder to an element on a substrate |
US6857552B2 (en) * | 2003-04-17 | 2005-02-22 | Intercard Limited | Method and apparatus for making smart card solder contacts |
JP2005122678A (ja) * | 2003-09-26 | 2005-05-12 | Toshiba Corp | 携帯可能電子装置 |
US20060238989A1 (en) * | 2005-04-25 | 2006-10-26 | Delaware Capital Formation, Inc. | Bonding and protective method and apparatus for RFID strap |
US7777317B2 (en) * | 2005-12-20 | 2010-08-17 | Assa Abloy Identification Technologies Austria GmbH (Austria) | Card and manufacturing method |
US8240022B2 (en) * | 2006-09-26 | 2012-08-14 | Feinics Amatech Teorowita | Methods of connecting an antenna to a transponder chip |
US7581308B2 (en) * | 2007-01-01 | 2009-09-01 | Advanced Microelectronic And Automation Technology Ltd. | Methods of connecting an antenna to a transponder chip |
US20080179404A1 (en) * | 2006-09-26 | 2008-07-31 | Advanced Microelectronic And Automation Technology Ltd. | Methods and apparatuses to produce inlays with transponders |
US7979975B2 (en) * | 2007-04-10 | 2011-07-19 | Feinics Amatech Teavanta | Methods of connecting an antenna to a transponder chip |
HK1109708A2 (en) * | 2007-04-24 | 2008-06-13 | On Track Innovations Ltd | Interface card and apparatus and process for the formation thereof |
US7980477B2 (en) * | 2007-05-17 | 2011-07-19 | Féinics Amatech Teoranta | Dual interface inlays |
DE102007037167A1 (de) * | 2007-08-07 | 2009-02-19 | Ulrich, Reinhard, Prof.Dipl.-Phys.Dr. | Einlagige Flachspule auf Substrat |
SG150404A1 (en) * | 2007-08-28 | 2009-03-30 | Micron Technology Inc | Semiconductor assemblies and methods of manufacturing such assemblies |
EP2034429A1 (en) * | 2007-09-05 | 2009-03-11 | Assa Abloy AB | Manufacturing method for a card and card obtained by said method |
US8695207B2 (en) * | 2008-06-02 | 2014-04-15 | Nxp B.V. | Method for manufacturing an electronic device |
US8889482B2 (en) * | 2009-06-14 | 2014-11-18 | Jayna Sheats | Methods to fabricate integrated circuits by assembling components |
DE102009043587A1 (de) * | 2009-09-30 | 2011-05-19 | Smartrac Ip B.V. | Funktionelles Laminat |
US20120055013A1 (en) * | 2010-07-13 | 2012-03-08 | Féinics AmaTech Nominee Limited | Forming microstructures and antennas for transponders |
US8870080B2 (en) * | 2010-08-12 | 2014-10-28 | Féinics Amatech Teoranta | RFID antenna modules and methods |
US8314489B2 (en) * | 2010-09-13 | 2012-11-20 | Infineon Technologies Ag | Semiconductor module and method for production thereof |
US20130075134A1 (en) * | 2010-10-11 | 2013-03-28 | Feinics Amatech Nominee Limited | Preparing a substrate for embedding wire |
DE102012205768B4 (de) * | 2012-04-10 | 2019-02-21 | Smartrac Ip B.V. | Transponderlage und Verfahren zu deren Herstellung |
JP2015142059A (ja) * | 2014-01-30 | 2015-08-03 | 株式会社日立製作所 | パワー半導体モジュール |
-
2011
- 2011-10-04 DE DE102011114635A patent/DE102011114635A1/de not_active Ceased
- 2011-12-16 CN CN201110424639.9A patent/CN103034897B/zh not_active Expired - Fee Related
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- 2012-09-27 EP EP12778607.7A patent/EP2764473B1/de active Active
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- 2012-10-03 TW TW101136447A patent/TWI562076B/zh not_active IP Right Cessation
Patent Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN1750026A (zh) * | 2004-09-15 | 2006-03-22 | 株式会社Y.B.L | 双界面ic卡 |
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