CN103022298B - High voltage LED chip with light-guiding pillar and preparation method thereof - Google Patents
High voltage LED chip with light-guiding pillar and preparation method thereof Download PDFInfo
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- CN103022298B CN103022298B CN201210476252.2A CN201210476252A CN103022298B CN 103022298 B CN103022298 B CN 103022298B CN 201210476252 A CN201210476252 A CN 201210476252A CN 103022298 B CN103022298 B CN 103022298B
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Abstract
The present invention is high voltage LED chip with light-guiding pillar and preparation method thereof openly, and feature forms the light-guiding pillar with angle of inclination.The preparation of light-guiding pillar directly etches to form in high voltage LED chip manufacturing process, and etched surface comprises epitaxial loayer side and side of substrate.Light-guiding pillar of the present invention can change incidence angle when light beam is transmitted to air by GaN base light LED material to avoid total reflection, the loss simultaneously light beam can being avoided to cause in this GaN base LED internal repeated reflection, improves the side light extraction efficiency of high voltage LED chip.Have when trapezoid flank angle can ensure evaporation connecting bridge simultaneously and do not occur short circuit, sidewall bright dipping can increase the light-emitting area of every crystal grain, can reduce simultaneously light that crystal grain side sends between crystal grain and crystal grain, between crystal grain and substrate and intra-die there is the loss that catadioptric back and forth causes.
Description
Technical field
The present invention relates to LED chip field, particularly the technology of preparing of high voltage LED chip.
Background technology
Along with the development with multi-quantum pit structure of improving of growth technology, the internal quantum efficiency of high-brightness LED there has been very large improvement.At present, the light extraction efficiency of LED chip has become the principal element of restriction LED luminous efficiency.The technological approaches of the light extraction efficiency of existing raising chip, mainly contains chip plastic technology, distribution bragg (DBR) mirror technology, flip chip technology, surface texture technology and photonic crystal technology.These technology are all at the luminosity that improve GaN base light-emitting diode in varying degrees, but they all concentrate on the light extraction efficiency in the front of improving chip.The character of lumination of light emitting diode is spontaneous radiation, does not have directivity, can be similar to and regard isotropism luminescence as.Therefore, the lateral emitting light extraction efficiency of above technology to LED chip there is no improvement.
The technology of existing raising side light extraction efficiency has hexagon chip and parallelogram chip, by changing the size of polygon interior angle, making can in another side outgoing at the light of chip a certain side generation total reflection, reach the object improving light extraction efficiency, but this polygonal chip profile tool in chip cutting acquires a certain degree of difficulty, and is unfavorable for scale of mass production.
Summary of the invention
For the subject matter that LED chip faces, the invention provides the high voltage LED chip with light-guiding pillar, this structure fabrication is convenient, can improve the light extraction efficiency of high voltage LED chip.The present invention adopts following technical scheme:
A kind of high voltage LED chip with light-guiding pillar, pass through photoetching process, the light-guiding pillar with angle of inclination is formed in the side of high-voltage chip every die unit, described side comprises epitaxial loayer side and side of substrate, and the shape of cross section of light-guiding pillar is waveform, triangle or semicircular periodic structure.
Further improvement, the side of described every die unit has the angle of inclination at trapezoid base angle, and the base angle of trapezoid is 30 °-150 °.
Further improvement, be etched with isolation channel between adjacent two die unit, the degree of depth of isolation channel extends downward sapphire layer.
The present invention also provides a kind of preparation method with the high voltage LED chip of light-guiding pillar, and it comprises the steps:
(1) by photoetching process, utilize inductive couple plasma (ICP) to etch about 11000-15000 degree of depth, go out N-type GaN table top in the surface etch of every LEDs crystal grain, the N-type GaN of every LEDs crystal grain is exposed;
(2) at the SiO of the surface deposition thickness 5000-10000 of epitaxial wafer
2protective layer, and the photoresist protective layer making 4 μm-7 μm on SiO2 layer, to prepare the isolation channel of high voltage LED chip, prepare light guide column structure in the side of every little crystal grain simultaneously;
(3) at epitaxial wafer surface evaporation tin indium oxide (ITO) transparency conducting layer, by photoetching process, adopt method for chemially etching, only retain the ITO transparency conducting layer on P type GaN, in order to improve the uniformity of electric current in P type GaN surface distributed; Afterwards, at epitaxial wafer surface deposition thickness be 2000-7000 SiO
2insulating barrier, by photoetching, wet etching, between groove, electrode connection makes bridge joint insulating barrier;
(4) photoetching process is passed through, P electrode and N electrode is made respectively in described P electrode district and N electrode district, evaporation connecting electrode on bridge joint insulating barrier simultaneously, the P electrode of one LEDs crystal grain is connected by connecting electrode with the N electrode of another LED grain, be connected to form series circuit by connecting electrode between plurality of LEDs crystal grain, form complete high voltage LED chip.
Further, the preparation of isolation channel and light-guiding pillar specifically comprises in step (2): first prepare isolation channel pattern and light-guiding pillar pattern by photoetching process at described photoresist protective layer, and light-guiding pillar pattern is the cross section being distributed in each little crystal edge is waveform, triangle or semicircular periodic structure; Recycling BOE solution etches SiO
2protective layer, makes the GaN between little crystal grain expose, thus by isolation channel pattern and light-guiding pillar design transfer to SiO
2layer; Then inductive couple plasma (ICP) is utilized to etch, by isolation channel pattern and light-guiding pillar design transfer to GaN layer, wherein, in ICP etching process, by regulating etching gas BCl
3and Cl
2ratio, proportion is at 1:1 ~ 1:20, and to form the trapezoid flank angle of every little crystal grain, thus preparation has the light-guiding pillar of laterally inclined angle.
Compared with prior art, beneficial effect of the present invention and advantage: light-guiding pillar can change incidence angle when light beam is transmitted to air by GaN base light LED material to avoid total reflection, the loss simultaneously light beam can being avoided to cause in this GaN base LED internal repeated reflection, reaches the object of the side light extraction efficiency improving high voltage LED chip.Short circuit is there is not in this structure simultaneously with flank angle when can ensure evaporation connecting bridge, sidewall bright dipping can increase the light-emitting area of every crystal grain, can reduce simultaneously light that crystal grain side sends between crystal grain and crystal grain, between crystal grain and substrate and intra-die there is the loss that catadioptric back and forth causes, improve chip brightness thus, improve device reliability.
Accompanying drawing explanation
Fig. 1 is the end view etching high voltage LED chip after N-type GaN table top in execution mode.
Fig. 2 is the end view of high voltage LED chip after isolation channel etching in execution mode.
Fig. 3 is the vertical view of the single die unit of high voltage LED chip after isolation channel etching in execution mode.
Fig. 4 is the end view that in execution mode, insulative bridge makes rear high voltage LED chip.
Fig. 5 is the end view of high voltage LED chip after electrode fabrication in execution mode.
Embodiment
Below in conjunction with drawings and Examples, the present invention is described in detail, but enforcement of the present invention and protection range are not limited thereto.
As Fig. 3 and Fig. 5, there is the high voltage LED chip of light-guiding pillar, comprise epitaxial loayer and substrate, specifically comprise sapphire layer 1, GaN resilient coating 2, N-type GaN3, mqw light emitting layer 4, P type GaN5, the single die unit 6 of high voltage LED chip, the light-guiding pillar 7 at single die unit edge, ITO transparency conducting layer 8, SiO
2insulating barrier 9, P electrode 10, connecting electrode 11, N electrode 12.
As Fig. 3, feature of the present invention passes through etching technics, form the light-guiding pillar 7 with angle of inclination in the side of high-voltage chip every crystal grain list 6, etched surface comprises epitaxial loayer side and side of substrate, and the shape of cross section of light-guiding pillar is waveform, triangle or semicircular periodic structure.The side of described every die unit 6 has the angle of inclination (as Fig. 5) at trapezoid base angle, and the base angle of trapezoid is 30 °-150 °.Be etched with isolation channel between adjacent two die unit, the degree of depth of isolation channel extends downward sapphire layer 1(substrate).
There is the Making programme of the high voltage LED chip of light-guiding pillar:
1, photoetching process is passed through, utilize inductive couple plasma (ICP) to etch about 11000-15000 degree of depth (depending on different epitaxial wafer growth structure, etching depth is different), go out N-type GaN3 table top in the surface etch of every LEDs crystal grain, the N-type GaN3 of every LEDs crystal grain is exposed, as Fig. 1;
2, at the SiO of the surface deposition thickness 5000-10000 of epitaxial wafer
2protective layer, and on SiO2 layer, adopt the higher thick glue of resolution to make the photoresist protective layer of 4 μm-7 μm, to prepare the isolation channel of high voltage LED chip, prepare light guide column structure in the side of every little crystal grain simultaneously.
Concrete preparation method is as follows.First prepare isolation channel pattern and light-guiding pillar 7 pattern by photoetching process at photoresist protective layer, light-guiding pillar pattern is the cross section being distributed in each little crystal edge is leg-of-mutton periodic structure.Recycling BOE solution (HF, NH
4f mixed solution) etch SiO
2protective layer, makes the GaN between little crystal grain expose, thus by isolation channel pattern and light-guiding pillar design transfer to SiO
2layer; After requiring etching, in groove, etching is clean, without SiO
2residual, and light-guiding pillar shape is more complete.Then inductive couple plasma (ICP) is utilized to etch, by isolation channel pattern and light-guiding pillar design transfer to GaN layer.Wherein, in ICP etching process (etched surface comprises epitaxial loayer side and side of substrate), by regulating etching gas BCl
3and Cl
2ratio, proportion is at 1:1 ~ 1:20, and to form the trapezoid flank angle of every little crystal grain, thus preparation has the light-guiding pillar of laterally inclined angle.In order to form many mutual disjunct LED grain, isolation channel needs to etch into sapphire layer 1, and the thickness depending on GaN epitaxial layer determines that etching depth is about 4um-7um, as Fig. 2.After isolation channel etching, the vertical view of single die unit is as Fig. 3, and the cross section of crystal edge is that leg-of-mutton periodic structure is light-guiding pillar 7.
3, at epitaxial wafer surface evaporation tin indium oxide (ITO) transparency conducting layer 8, by photoetching process, adopt method for chemially etching, only retain the ITO on p-type GaN5, in order to improve the uniformity of electric current in P type GaN surface distributed.Afterwards, at epitaxial wafer surface deposition thickness be 2000-7000 SiO
2insulating barrier 9, by photoetching, wet etching, between groove, electrode connection makes bridge joint insulating barrier, causes P, N layer of same LEDs crystal grain be connected and cause electric leakage, as Fig. 4 when connecting electrode makes after preventing.
4, photoetching process is passed through, P electrode 10 and N electrode 12 is made respectively in described P electrode district and N electrode district, evaporation connecting electrode 11 on bridge joint insulating barrier simultaneously, the P electrode 10 of one LEDs crystal grain is connected by connecting electrode with the N electrode 12 of another LED grain, series circuit is connected to form by connecting electrode between plurality of LEDs crystal grain, form complete high voltage LED chip, as Fig. 5.
The principle that the present invention has the light-guiding pillar raising high voltage LED chip luminous efficiency of laterally inclined angle is as follows.When light is from when having the crystal grain side outgoing of light-guiding pillar, owing to there is scattering on coarse exiting surface, more light can fall into the transmissive region of miniature scattering surface, and the bright dipping of crystal grain side is significantly strengthened, thus improves the luminous efficiency of high voltage LED chip.Meanwhile, because light-guiding pillar has trapezoid angle of inclination, the gradient of connecting electrode between crystal grain can be made on the one hand comparatively mild, thus reduce the probability of short circuit; Light can also be reflected towards chip surface direction on the other hand, reduce thus the light that sends of crystal grain side between crystal grain and crystal grain, between crystal grain and substrate and intra-die there is the loss that catadioptric back and forth causes, thus improve the luminous efficiency of high voltage LED chip.
Claims (2)
1. there is a preparation method for the high voltage LED chip of light-guiding pillar, it is characterized in that comprising the steps:
(1) by photoetching process, utilize inductive couple plasma (ICP) to etch 11000-15000 degree of depth, go out N-type GaN table top in the surface etch of every LEDs crystal grain, the N-type GaN of every LEDs crystal grain is exposed;
(2) at the SiO of the surface deposition thickness 5000-10000 of epitaxial wafer
2protective layer, and at SiO
2make the photoresist protective layer of 4 μm-7 μm above layer, to prepare the isolation channel of high voltage LED chip, prepare light guide column structure in the side of every little crystal grain simultaneously;
(3) at epitaxial wafer surface evaporation tin indium oxide (ITO) transparency conducting layer, by photoetching process, adopt method for chemially etching, only retain the ITO transparency conducting layer on P type GaN, in order to improve the uniformity of electric current in P type GaN surface distributed; Afterwards, at epitaxial wafer surface deposition thickness be 2000-7000 SiO
2insulating barrier, by photoetching, wet etching, between groove, electrode connection makes bridge joint insulating barrier;
(4) photoetching process is passed through, P electrode and N electrode is made respectively at P type GaN and N-type GaN, evaporation connecting electrode on bridge joint insulating barrier simultaneously, the P electrode of one LEDs crystal grain is connected by connecting electrode with the N electrode of another LED grain, be connected to form series circuit by connecting electrode between plurality of LEDs crystal grain, form complete high voltage LED chip.
2. the preparation method with the high voltage LED chip of light-guiding pillar according to claim 1, is characterized in that the preparation of isolation channel and light-guiding pillar in step (2) specifically comprises:
First prepare isolation channel pattern and light-guiding pillar pattern by photoetching process at described photoresist protective layer, light-guiding pillar pattern is the cross section being distributed in each little crystal edge is waveform, triangle or semicircular periodic structure; Recycling BOE solution etches SiO
2protective layer, makes the GaN between little crystal grain expose, thus by isolation channel pattern and light-guiding pillar design transfer to SiO
2layer; Then inductive couple plasma (ICP) is utilized to etch, by isolation channel pattern and light-guiding pillar design transfer to GaN layer, wherein, in ICP etching process, by regulating etching gas BCl
3and Cl
2ratio, proportion is at 1:1 ~ 1:20, and to form the trapezoid flank angle of every little crystal grain, thus preparation has the light-guiding pillar of laterally inclined angle.
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| CN108417678B (en) * | 2018-03-16 | 2021-06-04 | 厦门市三安光电科技有限公司 | Light emitting diode structure and manufacturing method thereof |
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| CN102222740A (en) * | 2010-04-19 | 2011-10-19 | Lg伊诺特有限公司 | Light emitting device, method of manufacturing the same, light emitting device package and lighting system |
| CN202948966U (en) * | 2012-11-22 | 2013-05-22 | 华南理工大学 | High-voltage light-emitting diode (LED) chip with light guide columns |
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| CN102222740A (en) * | 2010-04-19 | 2011-10-19 | Lg伊诺特有限公司 | Light emitting device, method of manufacturing the same, light emitting device package and lighting system |
| CN202948966U (en) * | 2012-11-22 | 2013-05-22 | 华南理工大学 | High-voltage light-emitting diode (LED) chip with light guide columns |
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