CN102983811B - A kind of pierce circuit - Google Patents
A kind of pierce circuit Download PDFInfo
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- CN102983811B CN102983811B CN201210483518.6A CN201210483518A CN102983811B CN 102983811 B CN102983811 B CN 102983811B CN 201210483518 A CN201210483518 A CN 201210483518A CN 102983811 B CN102983811 B CN 102983811B
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Abstract
The embodiment of the present invention relates to a kind of pierce circuit.Described circuit comprises first branch's oscillating circuit, the second branch's oscillating circuit and NOR gate; Described first branch's oscillating circuit, for generation of first branch's oscillator signal; Described second branch's oscillating circuit, for generation of second branch's oscillator signal; Described NOR gate, for using described first branch's oscillating circuit and second branch's oscillator signal as input, outputting oscillation signal.The embodiment of the present invention relates to two-way oscillator signal, and carries out NOR-operation to it and obtain oscillator signal, and described oscillator signal has maximum duty cycle signal, and this signal is by the temperature of described pierce circuit, voltage and process variations influence.
Description
Technical field
The present invention relates to multimedia field of oscillators, particularly relate to a kind of pierce circuit.
Background technology
Fig. 1 shows a kind of existing pierce circuit figure.Current source I5 and field effect transistor MP1 provides bias current, by carrying out to electric capacity C1 the function that discharge and recharge can realize oscillator.Suppose that signal OSC initial value is low level, such field effect transistor MN5 by, bias current charges to C1.This process makes MN1 conducting until node voltage NODE1 is elevated to, and then node voltage NODE2 becomes low level.Then by the amplification of field effect transistor MP5 and the shaping of inverter I1 ~ I4, signal OSC has become high level.Field effect transistor MN5 conducting subsequently, electric capacity C1 discharges, and node voltage NODE2 becomes high level, and then OSC becomes low level.Go round and begin again like this, create oscillator signal OSC.Fig. 2 is the simulation result schematic diagram of the waveform of oscillator shown in Fig. 1.
The shortcoming of existing scheme is that the duty ratio of oscillator signal is little, and oscillator signal is subject to the impact of oscillator temperature, voltage and manufacturing technology level.
Summary of the invention
For the problems referred to above, the embodiment of the present invention proposes a kind of pierce circuit.
In first aspect, described pierce circuit comprises first branch's oscillating circuit, the second branch's oscillating circuit and NOR gate, and described first branch's oscillating circuit, for generation of first branch's oscillator signal; Described second branch's oscillating circuit, for generation of second branch's oscillator signal; Described NOR gate, for using described first branch's oscillating circuit and second branch's oscillator signal as input, outputting oscillation signal.
In second aspect, described pierce circuit comprises current mirror, current source, charge-discharge circuit, the first comparison circuit, the second comparison circuit and the first logic gates and the second logic gates; Wherein, current mirror has the first branch road, the second branch road, the 3rd branch road and the 4th branch road; First branch road is connected with current source; Second branch road connects charge-discharge circuit; Described 3rd branch road is connected with the first comparator, and described 4th branch road is connected with described second comparator; Described charge-discharge circuit is connected with described first comparison circuit and described second comparison circuit common gate; The discharge and recharge of charge-discharge circuit to electric capacity changes the grid voltage of described charge-discharge circuit, the first comparison circuit and the second comparison circuit, so that the first comparison circuit and the second comparison circuit break-make and the first node on described first comparison circuit and the upset of the Section Point on the second comparison circuit and produce first branch's oscillator signal and second branch's oscillator signal respectively, first branch's oscillator signal is exported by the first logic gates; Second branch's oscillator signal is exported by the second logic gates; The output signal of the first logic gates controls charge-discharge circuit; The output signal of the first logic gates controls the transmission of second branch's oscillator signal to the second logic gates; 3rd logic gates based on described first branch's oscillator signal and second branch's oscillator signal, outputting oscillation signal.
Embodiment of the present invention design two-way oscillator signal, and carry out NOR-operation to it and obtain oscillator signal, described oscillator signal has maximum duty cycle signal, and this signal is by the temperature of described pierce circuit, voltage and process variations influence.
Accompanying drawing explanation
Fig. 1 is a kind of existing pierce circuit figure;
Fig. 2 is the simulation result schematic diagram of the waveform of oscillator shown in Fig. 1;
Fig. 3 A is a kind of pierce circuit schematic diagram of the embodiment of the present invention;
Fig. 3 B is the another kind of pierce circuit schematic diagram of the embodiment of the present invention;
Fig. 3 C is another pierce circuit schematic diagram of the embodiment of the present invention;
Fig. 3 D is another pierce circuit schematic diagram of the embodiment of the present invention;
Fig. 4 is the simulation result schematic diagram of the waveform of oscillator shown in Fig. 3;
Fig. 5 is the another kind of schematic diagram of the pierce circuit of the embodiment of the present invention.
Embodiment
Below by drawings and Examples, the technical scheme of the embodiment of the present invention is described in further detail.
Fig. 3 A is the pierce circuit schematic diagram of the embodiment of the present invention.Liang Ge branch oscillating circuit is comprised: the first vibration branch road and the second vibration branch road in Fig. 3 A.Described first vibration branch road is for generation of the first branch oscillator signal NODE1, and it is similar to the OSC oscillator signal in Fig. 1.Described second vibration branch road produces the second oscillator signal NODE2.
Described first vibration branch road comprises current source I10, resistance R1, field effect transistor MN2, MN3, MN4, MN5, MP1, MP3, MP4, MP5, MP6, inverter I1 ~ I4.MP1, MP3, MP4 form current mirror, and the first field effect transistor MP1 is positioned on the first branch road, and the 3rd field effect transistor MP3 is positioned on the 3rd branch road, and the 4th field effect transistor MP4 is positioned on the 4th branch road.Current source I10 is positioned on the first branch road.5th field effect transistor MN2 and the 7th field effect transistor MN3 common gate, and be connected on the 3rd branch road and the 4th branch road.MN3 and the 8th field effect transistor MN8 forms the first (the second) charge-discharge circuit to electric capacity C1.MN2 forms the first comparison circuit.MP5 forms the 5th branch road of current source, MN4 and MN5 forms second current mirror, and MP6 is the amplifying circuit of NODE3 signal, and MP5, MN4 and MN5 are configured to the biasing circuit that MP6 provides bias voltage.
Described second vibration branch road comprises current source I10, resistance R2, field effect transistor MN1, MN6, MN7, MP1, MP2, MP7, MP8, inverter I5 ~ I8.6th field effect transistor MN1 is connected on second branch road of current mirror of the first field effect transistor MP1 and the second field effect transistor MP2 composition mentioned above, and the grid of MN1 is connected with the grid of MN2 and MN3, and MN1 forms the second comparison circuit.MP8 forms the amplifying circuit of NODE4 signal.MN6 forms the 3rd branch road on the current source of MN4 and MN5, and provides bias voltage for MP8.
The grid of MP7 connects the output from I3, and the drain electrode of MP7 is connected to the grid of MP8.
Suppose that the output signal initial value of NODE1 is low, MN8 ends, and MN3 charges to C1.The charging of C1 can cause the grid voltage of MN1 and MN2 to raise, and and then by MN1 and MN2 conducting.When the On current of MN1 and MN2 is increasing, to such an extent as to NODE4 and NODE3 can overturn and be dragged down.This energizing signal amplifies by MP8 and MP6 respectively, and outputs to the second logic gates I5-I8 and the first logic gates I1-I4.When the output signal of NODE1 becomes high, MN8 conducting, to C1 electric discharge, drags down the grid voltage of MN1 and MN2, turns off MN1 and MN2, NODE4 and NODE3 and is elevated.Thus, the vibration of circuit is achieved.
In this circuit, R2 is less than R1, and like this when signal RAMP rising becomes large, first node voltage NODE4 becomes low level than node voltage NODE3, and then first node voltage NODE2 becomes high level than node voltage NODE1.Get the trailing edge of node voltage NODE1 and the rising edge of NODE2, by NOR gate I9, maximum duty cycle signal MAX_DUTY can be produced.The effect of MP7 and MN7 is, when NODE1 becomes high level, forces NODE2 to become low level at once, so only needs NODE1 and NODE2 can produce MAX_DUTY by NOR gate I9, simplify design.And resistance capacitance required little in this circuit, area is less.
When temperature, supply voltage and technique change, the absolute change trend of node voltage NODE3 with NODE4 is consistent, but change is but very little relatively.Consequent maximum duty cycle signal MAX_DUTY does not change with temperature, supply voltage and technique change substantially.
Fig. 4 is the simulation result schematic diagram of the waveform of oscillator shown in Fig. 3 A.Simulation result shows, is the MAX_DUTY of 92% for duty ratio representative value, when temperature, supply voltage and technique change, the maximum fluctuation of MAX_DUTY is only ± and 1%.
Fig. 3 B is the another kind of pierce circuit schematic diagram of the embodiment of the present invention.In figure 3b, first vibration branch road comprises current source I10, resistance R1, field effect transistor MN2, MN3, MN4, MN5, MN8, MP1, MP3, MP4, MP5, MP6, inverter I1 ~ I2, described second vibration branch road comprises current source I10, resistance R2, field effect transistor MN1, MN6, MN7, MP1, MP2, MP7, MP8, inverter I3 ~ I4.The place being different from Fig. 3 A is that inverter is 2.
Fig. 3 C is another pierce circuit schematic diagram of the embodiment of the present invention.In Fig. 3 C, first vibration branch road comprises current source I10, resistance R1, field effect transistor MN2, MN3, MN4, MN5, MN8, MP1, MP3, MP4, MP5, MP6, inverter I1 ~ I6, described second vibration branch road comprises current source I10, resistance R2, field effect transistor MN1, MN6, MN7, MP1, MP2, MP7, MP8, inverter I7 ~ I12.The place being different from Fig. 3 A is that inverter is 6.
Fig. 3 D is another pierce circuit schematic diagram of the embodiment of the present invention.In Fig. 3 D, the first vibration branch road comprises current source I10, resistance R1, field effect transistor MN2, MN3, MN4, MN5, MN8, MP1, MP3, MP4, MP5, MP6, inverter I1 ~ I4, described second vibration branch road comprises current source I10, resistance R2, field effect transistor MN1, MN6, MN7, MN9, MP1, MP2, MP7, MP8, MP9, inverter I5 ~ I8.The place being different from Fig. 3 A is that MP8 have employed independent biasing circuit, and MP9 is as another branch of the current mirror of MP1-MP4, and MN6 is serially connected in this another branch, the current mirror that MN6 and MN9 is formed, thus for MP8 provides bias voltage.
Fig. 5 is the another kind of schematic diagram of the pierce circuit of the embodiment of the present invention.Described pierce circuit comprises first branch's oscillating circuit, the second branch's oscillating circuit and NOR gate, and described first branch's oscillating circuit, for generation of first branch's oscillator signal; Described second branch's oscillating circuit, for generation of second branch's oscillator signal; Described NOR gate, for using described first branch's oscillating circuit and second branch's oscillator signal as input, outputting oscillation signal.
Preferably, described first branch's oscillating circuit produces first branch's oscillator signal, is specially: described first branch's oscillating circuit produces first branch's oscillator signal according to first node voltage; Described second branch's oscillating circuit produces second branch's oscillator signal, is specially: described second branch's oscillating circuit produces second branch's oscillator signal according to Section Point voltage.
Preferably, first branch's oscillating circuit comprises identical constant-current source with second branch's oscillating circuit.
Preferably, described first node voltage is consistent with the absolute change trend of described Section Point voltage and relatively change very little.
The embodiment of the present invention relates to two-way branch oscillating circuit to produce two-way branch oscillator signal, and NOR-operation is carried out to it obtain oscillator signal, described oscillator signal has maximum duty cycle signal, and this signal is by the temperature of described pierce circuit, voltage and process variations influence.
It should be noted last that, above embodiment is only in order to illustrate technical scheme of the present invention and unrestricted, although with reference to preferred embodiment to invention has been detailed description, those of ordinary skill in the art is to be understood that, can modify to technical scheme of the present invention or equivalent replacement, and not depart from the spirit and scope of technical solution of the present invention.
Claims (7)
1. a pierce circuit, is characterized in that, described pierce circuit comprises first branch's oscillating circuit, second branch's oscillating circuit and the 3rd logic gates;
Wherein, described first branch's oscillating circuit comprises: constant-current source (I10), the first current mirror (MP1, MP3, MP4), the first charge-discharge circuit (MN3 and MN8, C1), the first comparison circuit (MN2) and the first logic gates, for generation of first branch's oscillator signal;
Described second branch's oscillating circuit comprises: constant-current source (I10), the second current mirror (MP1, MP2), the second charge-discharge circuit (MN3, MN8, C1), the second comparison circuit (MN1) and the second logic gates, for generation of second branch's oscillator signal;
Described first branch's oscillating circuit comprises identical constant-current source with described second branch's oscillating circuit; First charge-discharge circuit and the second charge-discharge circuit are for sharing charge-discharge circuit; The resistance value (R1) of the first comparison circuit is different from the resistance value (R2) of the second comparison circuit;
Described 3rd logic gates (I9) for using described first branch's oscillator signal and second branch's oscillator signal as input, outputting oscillation signal.
2. pierce circuit as claimed in claim 1, is characterized in that,
Described first branch's oscillating circuit produces first branch's oscillator signal, is specially:
Described first branch's oscillating circuit produces first branch's oscillator signal according to first node voltage;
Described second branch's oscillating circuit produces second branch's oscillator signal, is specially:
Described second branch's oscillating circuit produces second branch's oscillator signal according to Section Point voltage.
3. a pierce circuit, is characterized in that, described pierce circuit comprises current mirror, current source, charge-discharge circuit, the first comparison circuit, the second comparison circuit, the first logic gates, the second logic gates and the 3rd logic gates;
Current mirror comprises the first branch road, the second branch road, the 3rd branch road and the 4th branch road:
First branch road comprises the first field effect transistor (MP1) and current source;
Second branch road comprises the second field effect transistor (MP2) and the second comparison circuit;
3rd branch road comprises the 3rd field effect transistor (MP3) and the first comparison circuit;
4th branch road comprises the 4th field effect transistor (MP4) and charge-discharge circuit;
First comparison circuit is connected on the 3rd branch road, and comprises resistance (R1) and the 5th field effect transistor (MN2);
Second comparison circuit is connected on the second branch road, and comprises resistance (R2) and the 6th field effect transistor (MN1);
Charge-discharge circuit comprises: the 7th field effect transistor (MN3), electric capacity, with the 8th field effect transistor (MN8) of Capacitance parallel connection, the 7th field effect transistor (MN3) and capacitances in series are connected on the 4th branch road;
In addition, the 7th field effect transistor is connected with the 5th field effect transistor of the first comparison circuit and the 6th field effect transistor common gate of the second comparison circuit;
The output signal of the first logic gates controls charge-discharge circuit; The output signal of the first logic gates controls the transmission of second branch's oscillator signal to the second logic gates;
By the discharge and recharge of electric capacity in charge-discharge circuit, the vibration of realizing circuit:
When the first logic gates output signal is for time low, charge-discharge circuit capacitor charging, the grid voltage of the 5th field effect transistor and the 6th field effect transistor is caused to raise, make the 5th field effect transistor and the 6th field effect transistor conducting, and then the 5th field effect transistor drain voltage and the 6th field effect transistor drain voltage upset, first gate voltage output signal uprise; Charge-discharge circuit discharges, the grid voltage of the 5th field effect transistor and the 6th field effect transistor is caused to reduce, 5th field effect transistor and the 6th field effect transistor are turned off, so the drain voltage upset of the drain voltage of the 5th field effect transistor and the 6th field effect transistor, the vibration of realizing circuit;
First branch's oscillator signal is exported by the first logic gates; Second branch's oscillator signal is exported by the second logic gates;
3rd logic gates based on described first branch's oscillator signal and second branch's oscillator signal, outputting oscillation signal.
4. pierce circuit as claimed in claim 3, it is characterized in that, also comprise the first amplifier circuit (MP6) and/or the second amplifier circuit (MP8), first amplifier circuit is between described first comparison circuit and described first logic gates, and the second amplifier circuit is between described second comparison circuit and described second logic gates.
5. pierce circuit as claimed in claim 4, it is characterized in that, described pierce circuit also comprises the first biasing circuit (MN4, and/or the second biasing circuit (MN6 MN5), MN9), described first biasing circuit is connected with the first amplifier circuit, and for providing bias voltage for described first amplifier circuit, described second biasing circuit is connected with the second amplifier circuit for providing bias voltage for described second amplifier circuit.
6. pierce circuit as claimed in claim 5, is characterized in that, the first biasing circuit and the second biasing circuit adopt current mirror.
7. pierce circuit as claimed in claim 6, is characterized in that, described first biasing circuit and described second biasing circuit common current mirror.
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| CN201210483518.6A CN102983811B (en) | 2012-11-23 | 2012-11-23 | A kind of pierce circuit |
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| CN201210483518.6A CN102983811B (en) | 2012-11-23 | 2012-11-23 | A kind of pierce circuit |
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| CN102983811A CN102983811A (en) | 2013-03-20 |
| CN102983811B true CN102983811B (en) | 2016-04-27 |
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| CN103546121B (en) * | 2013-10-28 | 2016-04-27 | 无锡中感微电子股份有限公司 | Rc oscillator |
| CN113092856B (en) * | 2021-03-11 | 2022-01-04 | 广芯微电子（广州）股份有限公司 | Oscillator circuit for detecting LC resonance frequency |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN101286733A (en) * | 2008-05-26 | 2008-10-15 | 北京中星微电子有限公司 | An oscillator with low voltage and low power consumption |
| CN102394607A (en) * | 2011-08-30 | 2012-03-28 | 无锡中星微电子有限公司 | High-precision oscillator |
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| JP2005322958A (en) * | 2004-05-06 | 2005-11-17 | Nec Electronics Corp | Class d amplifier |
| US7102380B2 (en) * | 2004-07-07 | 2006-09-05 | Kao Richard F C | High speed integrated circuit |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101286733A (en) * | 2008-05-26 | 2008-10-15 | 北京中星微电子有限公司 | An oscillator with low voltage and low power consumption |
| CN102394607A (en) * | 2011-08-30 | 2012-03-28 | 无锡中星微电子有限公司 | High-precision oscillator |
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